[tests] More tests

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

sw/device/tests/BUILD

@@ -6519,7 +6519,7 @@ test_suite(
             test_harness = "//sw/host/tests/chip/rv_dm:access_after_hw_reset",
         ),
         deps = [
-            "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+            "//hw/top:dt",
             "//sw/device/lib/dif:rstmgr",
             "//sw/device/lib/runtime:hart",
             "//sw/device/lib/runtime:log",
@@ -6989,9 +6989,10 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:mmio",
@@ -7008,9 +7009,10 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:mmio",
@@ -7158,14 +7160,17 @@ opentitan_binary(
         "rv_core_ibex_epmp_test.S",
         "rv_core_ibex_epmp_test.c",
     ],
-    exec_env = {
-        "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
-        "//hw/top_earlgrey:fpga_cw340_rom_with_fake_keys": None,
-    },
+    exec_env = dicts.add(
+        {
+            "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
+            "//hw/top_earlgrey:fpga_cw340_rom_with_fake_keys": None,
+        },
+        DARJEELING_TEST_ENVS,
+    ),
     kind = "ram",
     linker_script = "//sw/device/silicon_creator/manuf/lib:sram_program_linker_script",
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/runtime:log",
@@ -7291,12 +7296,14 @@ opentitan_binary(
     kind = "ram",
     linker_script = "//sw/device/silicon_creator/manuf/lib:sram_program_linker_script",
     deps = [
+        "//hw/top:dt",
         "//hw/top:pwm_c_regs",
         "//hw/top:rv_timer_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/dif:flash_ctrl",
+        "//sw/device/lib/dif:pwm",
+        "//sw/device/lib/dif:rv_timer",
         "//sw/device/lib/runtime:log",
         "//sw/device/lib/runtime:pmp",
         "//sw/device/lib/testing:flash_ctrl_testutils",
@@ -7319,14 +7326,17 @@ opentitan_test(
             ["//hw/top_earlgrey:sim_verilator"],
         ),
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
+        "//hw/top:dt",
         "//hw/top:pwm_c_regs",
         "//hw/top:rv_timer_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/dif:flash_ctrl",
+        "//sw/device/lib/dif:pwm",
+        "//sw/device/lib/dif:rv_timer",
         "//sw/device/lib/runtime:log",
         "//sw/device/lib/runtime:pmp",
         "//sw/device/lib/testing:flash_ctrl_testutils",
@@ -7601,7 +7611,7 @@ opentitan_test(
         test_harness = "//sw/host/tests/chip/sram_ctrl:sram_ctrl_lc_escalation",
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:mmio",

sw/device/tests/rv_core_ibex_epmp_test.c

@@ -2,6 +2,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "hw/top/dt/dt_pinmux.h"     // Generated
+#include "hw/top/dt/dt_sram_ctrl.h"  // Generated
 #include "sw/device/lib/arch/device.h"
 #include "sw/device/lib/base/csr.h"
 #include "sw/device/lib/dif/dif_uart.h"
@@ -16,8 +18,6 @@
 #include "sw/device/silicon_creator/lib/dbg_print.h"
 #include "sw/device/silicon_creator/lib/epmp_defs.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-
 OTTF_DEFINE_TEST_CONFIG();
 
 /**
@@ -196,8 +196,9 @@ static void pmp_setup_machine_area(void) {
   // but is in a lower PMP register so region 15's configuration
   // will be ignored in this area.
   const uint32_t kRodataEnd = (uint32_t)__rodata_end;
-  const uint32_t kSramEnd = TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR +
-                            TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES;
+  const uint32_t kSramEnd =
+      dt_sram_ctrl_memory_base(kDtSramCtrlMain, kDtSramCtrlMemoryRam) +
+      dt_sram_ctrl_memory_size(kDtSramCtrlMain, kDtSramCtrlMemoryRam);
 
   CSR_WRITE(CSR_REG_PMPADDR8, tor_address(kRodataEnd));
   CSR_WRITE(CSR_REG_PMPADDR9, tor_address(kSramEnd));
@@ -266,8 +267,7 @@ static void pmp_setup_test_locations(void) {
  */
 static void setup_uart(void) {
   // Initialise DIF handles
-  CHECK_DIF_OK(dif_pinmux_init(
-      mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR), &pinmux));
+  CHECK_DIF_OK(dif_pinmux_init_from_dt(kDtPinmuxAon, &pinmux));
 
   // Initialise UART console.
   pinmux_testutils_init(&pinmux);

sw/device/tests/rv_core_ibex_mem_test.c

@@ -17,10 +17,17 @@
  * Two MMIO registers from two different devices are written to and read from.
  */
 
+#include "hw/top/dt/dt_flash_ctrl.h"  // Generated
+#include "hw/top/dt/dt_pinmux.h"      // Generated
+#include "hw/top/dt/dt_pwm.h"         // Generated
+#include "hw/top/dt/dt_rom_ctrl.h"    // Generated
+#include "hw/top/dt/dt_rv_timer.h"    // Generated
 #include "sw/device/lib/arch/boot_stage.h"
 #include "sw/device/lib/arch/device.h"
 #include "sw/device/lib/base/csr.h"
 #include "sw/device/lib/dif/dif_flash_ctrl.h"
+#include "sw/device/lib/dif/dif_pwm.h"
+#include "sw/device/lib/dif/dif_rv_timer.h"
 #include "sw/device/lib/dif/dif_uart.h"
 #include "sw/device/lib/runtime/ibex.h"
 #include "sw/device/lib/runtime/log.h"
@@ -36,15 +43,14 @@
 #include "hw/top/flash_ctrl_regs.h"
 #include "hw/top/pwm_regs.h"
 #include "hw/top/rv_timer_regs.h"
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 OTTF_DEFINE_TEST_CONFIG();
 
 enum {
   // Search within this ROM region to find `c.jr x1`, so execution can be
-  // tested.
-  kRomTestLocStart = TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + 0x400,
-  kRomTestLocEnd = TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + 0x500,
+  // tested. ROM base address will be computed at runtime.
+  kRomTestLocOffset = 0x400,
+  kRomTestLocSize = 0x100,
   kRomTestLocContent = 0x8082,
 
   // Number of bytes per page.
@@ -57,23 +63,9 @@ enum {
   // The start page used by this test. Points to the start of the owner
   // partition in bank 1, otherwise known as owner partition B.
   kBank1StartPageNum = 256 + kRomExtPageCount,
-
-  kFlashTestLoc = TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR +
-                  kBank1StartPageNum * kFlashBytesPerPage,
 };
 
-// The flash test location is set to the encoding of `jalr x0, 0(x1)`
-// so execution can be tested.
-const uint32_t kFlashTestLocContent = 0x00008067;
-void (*flash_test_gadget)(void) = (void (*)(void))kFlashTestLoc;
-
-volatile uint32_t *kMMIOTestLoc1 =
-    (uint32_t *)(TOP_EARLGREY_RV_TIMER_BASE_ADDR +
-                 RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET);
 const uint32_t kMMIOTestLoc1Content = 0x126d8c15;  // a random value
-
-volatile uint32_t *kMMIOTestLoc2 =
-    (uint32_t *)(TOP_EARLGREY_PWM_AON_BASE_ADDR + PWM_DUTY_CYCLE_0_REG_OFFSET);
 const uint32_t kMMIOTestLoc2Content = 0xe4210e64;  // a random value
 
 /**
@@ -84,8 +76,7 @@ static void setup_uart(void) {
   static dif_pinmux_t pinmux;
 
   // Initialise DIF handles
-  CHECK_DIF_OK(dif_pinmux_init(
-      mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR), &pinmux));
+  CHECK_DIF_OK(dif_pinmux_init_from_dt(kDtPinmuxAon, &pinmux));
 
   // Initialise UART console.
   pinmux_testutils_init(&pinmux);
@@ -113,13 +104,16 @@ static void use_icache(bool enable) {
  */
 static void setup_flash(void) {
   // Create a PMP region for the flash
+  uintptr_t flash_mem_base =
+      dt_flash_ctrl_memory_base(kDtFlashCtrl, kDtFlashCtrlMemoryMem);
+  size_t flash_mem_size =
+      dt_flash_ctrl_memory_size(kDtFlashCtrl, kDtFlashCtrlMemoryMem);
   pmp_region_config_t config = {
       .lock = kPmpRegionLockLocked,
       .permissions = kPmpRegionPermissionsReadWriteExecute,
   };
-  pmp_region_configure_napot_result_t result = pmp_region_configure_napot(
-      8, config, TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR,
-      TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES);
+  pmp_region_configure_napot_result_t result =
+      pmp_region_configure_napot(8, config, flash_mem_base, flash_mem_size);
   CHECK(result == kPmpRegionConfigureNapotOk,
         "Load configuration failed, error code = %d", result);
   // When running as ROM_EXT, ROM configures the flash memory to be readonly.
@@ -132,9 +126,7 @@ static void setup_flash(void) {
 
   // Initialise the flash controller.
   dif_flash_ctrl_state_t flash_ctrl;
-  CHECK_DIF_OK(dif_flash_ctrl_init_state(
-      &flash_ctrl,
-      mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR)));
+  CHECK_DIF_OK(dif_flash_ctrl_init_state_from_dt(&flash_ctrl, kDtFlashCtrl));
 
   CHECK_STATUS_OK(flash_ctrl_testutils_wait_for_init(&flash_ctrl));
 
@@ -158,6 +150,8 @@ static void setup_flash(void) {
       dif_flash_ctrl_set_exec_enablement(&flash_ctrl, kDifToggleEnabled));
 
   // Write the wanted value to flash
+  uintptr_t kFlashTestLoc =
+      flash_mem_base + kBank1StartPageNum * kFlashBytesPerPage;
   CHECK_STATUS_OK(flash_ctrl_testutils_erase_and_write_page(
       /*flash_state=*/&flash_ctrl,
       /*byte_address=*/kFlashTestLoc,
@@ -167,16 +161,31 @@ static void setup_flash(void) {
       /*word_count=*/1));
 }
 
-/**
- * The entry point of the SRAM test.
- */
 bool test_main(void) {
   setup_uart();
 
+  // Initialize MMIO peripherals to get their base addresses
+  dif_rv_timer_t rv_timer;
+  CHECK_DIF_OK(dif_rv_timer_init_from_dt(kDtRvTimer, &rv_timer));
+  volatile uint32_t *kMMIOTestLoc1 =
+      (uint32_t *)((uintptr_t)rv_timer.base_addr +
+                   RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET);
+
+  dif_pwm_t pwm;
+  CHECK_DIF_OK(dif_pwm_init_from_dt(kDtPwmAon, &pwm));
+  volatile uint32_t *kMMIOTestLoc2 =
+      (uint32_t *)((uintptr_t)pwm.base_addr + PWM_DUTY_CYCLE_0_REG_OFFSET);
+
   // ROM access is blocked in the silicon owner stage.
   if (kBootStage != kBootStageOwner) {
     LOG_INFO("Testing Load from ROM Location.");
 
+    // Get ROM base address
+    uintptr_t rom_base =
+        dt_rom_ctrl_memory_base(kDtRomCtrl, kDtRomCtrlMemoryRom);
+    uintptr_t kRomTestLocStart = rom_base + kRomTestLocOffset;
+    uintptr_t kRomTestLocEnd = kRomTestLocStart + kRomTestLocSize;
+
     // For the execution test we a specific `c.jr x1` (i.e. function return)
     // instruction. Since the address can vary between ROM builds, we scan a
     // small region to find it.
@@ -221,6 +230,11 @@ bool test_main(void) {
   setup_flash();
 
   LOG_INFO("Check flash load");
+  uintptr_t flash_mem_base =
+      dt_flash_ctrl_memory_base(kDtFlashCtrl, kDtFlashCtrlMemoryMem);
+  uintptr_t kFlashTestLoc =
+      flash_mem_base + kBank1StartPageNum * kFlashBytesPerPage;
+  void (*flash_test_gadget)(void) = (void (*)(void))kFlashTestLoc;
   load = *(volatile const uint32_t *)kFlashTestLoc;
   CHECK(
       load == kFlashTestLocContent,

sw/device/tests/rv_dm_access_after_hw_reset.c

@@ -2,14 +2,13 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "hw/top/dt/dt_rstmgr.h"  // Generated
 #include "sw/device/lib/runtime/log.h"
 #include "sw/device/lib/testing/rstmgr_testutils.h"
 #include "sw/device/lib/testing/test_framework/check.h"
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 #include "sw/device/lib/testing/test_framework/ottf_utils.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-
 /*
   - Wait for host to perform debugger tests
   - Once the host side confirms, do a SW reset of the chip
@@ -37,8 +36,7 @@ static void chip_sw_reset(void) {
 }
 
 bool test_main(void) {
-  CHECK_DIF_OK(dif_rstmgr_init(
-      mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr));
+  CHECK_DIF_OK(dif_rstmgr_init_from_dt(kDtRstmgrAon, &rstmgr));
 
   // Check if there was a HW reset caused by the software.
   dif_rstmgr_reset_info_bitfield_t rst_info;

sw/device/tests/sram_ctrl_lc_escalation_test.c

@@ -17,6 +17,9 @@
  * through the debug module.
  */
 
+#include "hw/top/dt/dt_alert_handler.h"  // Generated
+#include "hw/top/dt/dt_lc_ctrl.h"        // Generated
+#include "hw/top/dt/dt_sram_ctrl.h"      // Generated
 #include "sw/device/lib/arch/device.h"
 #include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/mmio.h"
@@ -30,7 +33,6 @@
 #include "sw/device/silicon_creator/lib/drivers/retention_sram.h"
 
 #include "hw/top/sram_ctrl_regs.h"  // Generated.
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 static const uint32_t kStatusRegMask = kDifSramCtrlStatusBusIntegErr |
                                        kDifSramCtrlStatusInitErr |
@@ -69,11 +71,8 @@ static bool write_read_data(mmio_region_t sram_region, uint32_t data) {
 }
 
 status_t configure_srams(void) {
-  uint32_t base_addr;
-  base_addr = TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR;
-  TRY(dif_sram_ctrl_init(mmio_region_from_addr(base_addr), &sram_ctrl_main));
-  base_addr = TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR;
-  TRY(dif_sram_ctrl_init(mmio_region_from_addr(base_addr), &sram_ctrl_ret));
+  TRY(dif_sram_ctrl_init_from_dt(kDtSramCtrlMain, &sram_ctrl_main));
+  TRY(dif_sram_ctrl_init_from_dt(kDtSramCtrlRetAon, &sram_ctrl_ret));
 
   dif_sram_ctrl_status_bitfield_t status_main;
   dif_sram_ctrl_status_bitfield_t status_ret;
@@ -91,9 +90,7 @@ status_t configure_srams(void) {
 }
 
 status_t configure_alert_handler(void) {
-  TRY(dif_alert_handler_init(
-      mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR),
-      &alert_handler));
+  TRY(dif_alert_handler_init_from_dt(kDtAlertHandler, &alert_handler));
 
   dif_alert_handler_escalation_phase_t esc_phases[] = {{
       .phase = kDifAlertHandlerClassStatePhase0,
@@ -111,7 +108,9 @@ status_t configure_alert_handler(void) {
   };
 
   TRY(dif_alert_handler_configure_alert(
-      &alert_handler, kTopEarlgreyAlertIdLcCtrlFatalBusIntegError,
+      &alert_handler,
+      dt_lc_ctrl_alert_to_alert_id(kDtLcCtrlFirst,
+                                   kDtLcCtrlAlertFatalBusIntegError),
       kDifAlertHandlerClassA, kDifToggleEnabled, kDifToggleEnabled));
   TRY(dif_alert_handler_configure_class(&alert_handler, kDifAlertHandlerClassA,
                                         class_config, kDifToggleEnabled,
@@ -123,17 +122,17 @@ status_t configure_alert_handler(void) {
 OTTF_DEFINE_TEST_CONFIG(.enable_uart_flow_control = true);
 
 bool test_main(void) {
-  CHECK_DIF_OK(dif_lc_ctrl_init(
-      mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR), &lc_ctrl));
+  CHECK_DIF_OK(dif_lc_ctrl_init_from_dt(kDtLcCtrlFirst, &lc_ctrl));
 
   CHECK_STATUS_OK(configure_alert_handler());
   CHECK_STATUS_OK(configure_srams());
 
   // Read and Write to/from SRAMs. Main SRAM will use the address of the
   // buffer that has been allocated. Ret SRAM can start at the owner section.
   sram_buffer_addr_main = (uintptr_t)&sram_buffer_main;
-  sram_buffer_addr_ret = TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR +
-                         offsetof(retention_sram_t, owner);
+  sram_buffer_addr_ret =
+      dt_sram_ctrl_memory_base(kDtSramCtrlRetAon, kDtSramCtrlMemoryRam) +
+      offsetof(retention_sram_t, owner);
 
   mmio_region_t sram_region_main = mmio_region_from_addr(sram_buffer_addr_main);
   mmio_region_t sram_region_ret = mmio_region_from_addr(sram_buffer_addr_ret);