[hw,pwm,dv] Templify DV for module_instance_name

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

hw/ip_templates/pwm/dv/README.md.tpl

@@ -40,7 +40,7 @@ that are common across the project:
 
 ${"###"} Global types & methods
 All common types and methods defined at the package level can be found in
-`pwm_env_pkg`. Some of them in use are:
+`${module_instance_name}_env_pkg`. Some of them in use are:
 ```systemverilog
 parameter uint NUM_PWM_CHANNELS = 6;
 
@@ -96,8 +96,8 @@ It can be created manually by invoking [`regtool`](../../../../../util/reggen/do
 ${"###"} Stimulus strategy
 ${"####"} Test sequences
 All test sequences reside in `hw/ip/pwm/dv/env/seq_lib`.
-The `pwm_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point.
-All test sequences are extended from `pwm_base_vseq`.
+The `${module_instance_name}_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point.
+All test sequences are extended from `${module_instance_name}_base_vseq`.
 It provides commonly-used handles, variables, functions and tasks that the test sequences can simple use / call.
 
 Some of the most commonly-used tasks / functions are as follows:
@@ -115,7 +115,7 @@ The functional coverage plan can be found here: [coverageplan](#testplan)
 
 ${"###"} Self-checking strategy
 ${"####"} Scoreboard
-The `pwm_scoreboard` is primarily used for transaction-by-transaction checking.
+The `${module_instance_name}_scoreboard` is primarily used for transaction-by-transaction checking.
 It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
 * item_fifo[NUM_PWM_CHANNELS]: the FIFO w.r.t channels receives the dut items sent by the pwm_monitor
 * exp_item                   : It is used to store the expected item constructed from tl address and data channels.
@@ -131,7 +131,7 @@ For blink and heart beat mode after an item is compared successfully the scorebo
 If an error is found the scoreboard will throw an error.
 
 ${"####"} Assertions
-* TLUL assertions: The `tb/pwm_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance.
+* TLUL assertions: The `tb/${module_instance_name}_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance.
 * Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
 
 

hw/ip_templates/pwm/dv/env/pwm_env.core.tpl

@@ -12,30 +12,30 @@ filesets:
       - ${instance_vlnv(f"lowrisc:ip:{module_instance_name}:0.1")}
       - lowrisc:dv:pwm_monitor
     files:
-      - pwm_env_pkg.sv
-      - pwm_env_cfg.sv: {is_include_file: true}
-      - pwm_env_cov.sv: {is_include_file: true}
-      - pwm_virtual_sequencer.sv: {is_include_file: true}
-      - pwm_scoreboard.sv: {is_include_file: true}
-      - pwm_env.sv: {is_include_file: true}
-      - seq_lib/pwm_vseq_list.sv: {is_include_file: true}
-      - seq_lib/pwm_base_vseq.sv: {is_include_file: true}
-      - seq_lib/pwm_common_vseq.sv: {is_include_file: true}
-      - seq_lib/pwm_phase_vseq.sv: {is_include_file: true}
-      - seq_lib/pwm_smoke_vseq.sv: {is_include_file: true}
-      - seq_lib/pwm_rand_output_vseq.sv: {is_include_file: true}
-      - seq_lib/pwm_heartbeat_wrap_vseq.sv: {is_include_file: true}
-      - seq_lib/pwm_perf_vseq.sv: {is_include_file: true}
-      - seq_lib/pwm_regwen_vseq.sv: {is_include_file: true}
-      - seq_lib/pwm_stress_all_vseq.sv: {is_include_file: true}
+      - ${module_instance_name}_env_pkg.sv
+      - ${module_instance_name}_env_cfg.sv: {is_include_file: true}
+      - ${module_instance_name}_env_cov.sv: {is_include_file: true}
+      - ${module_instance_name}_virtual_sequencer.sv: {is_include_file: true}
+      - ${module_instance_name}_scoreboard.sv: {is_include_file: true}
+      - ${module_instance_name}_env.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_vseq_list.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_base_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_common_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_phase_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_smoke_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_rand_output_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_heartbeat_wrap_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_perf_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_regwen_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_stress_all_vseq.sv: {is_include_file: true}
     file_type: systemVerilogSource
 
 generate:
   ral:
     generator: ralgen
     parameters:
-      name: pwm
-      ip_hjson: ../../data/pwm.hjson
+      name: ${module_instance_name}
+      ip_hjson: ../../data/${module_instance_name}.hjson
     position: prepend
 
 targets:

hw/ip_templates/pwm/dv/env/pwm_env.sv renamed to hw/ip_templates/pwm/dv/env/pwm_env.sv.tpl

@@ -2,13 +2,13 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-class pwm_env extends cip_base_env #(
-    .CFG_T              (pwm_env_cfg),
-    .COV_T              (pwm_env_cov),
-    .VIRTUAL_SEQUENCER_T(pwm_virtual_sequencer),
-    .SCOREBOARD_T       (pwm_scoreboard)
+class ${module_instance_name}_env extends cip_base_env #(
+    .CFG_T              (${module_instance_name}_env_cfg),
+    .COV_T              (${module_instance_name}_env_cov),
+    .VIRTUAL_SEQUENCER_T(${module_instance_name}_virtual_sequencer),
+    .SCOREBOARD_T       (${module_instance_name}_scoreboard)
   );
-  `uvm_component_utils(pwm_env)
+  `uvm_component_utils(${module_instance_name}_env)
   `uvm_component_new
 
   // One monitor for each channel; the monitors operate independently.
@@ -28,7 +28,7 @@ class pwm_env extends cip_base_env #(
     // generate core clock (must slower than bus clock)
     if (!uvm_config_db#(virtual clk_rst_if)
         ::get(this, "", "clk_rst_core_vif", cfg.clk_rst_core_vif)) begin
-      `uvm_fatal(`gfn, "\n  pwm_env: failed to get clk_rst_core_vif from uvm_config_db")
+      `uvm_fatal(`gfn, "\n  ${module_instance_name}_env: failed to get clk_rst_core_vif from uvm_config_db")
     end
 
     cfg.clk_rst_core_vif.set_freq_mhz(cfg.get_clk_core_freq());
@@ -46,4 +46,4 @@ class pwm_env extends cip_base_env #(
     end
   endfunction : connect_phase
 
-endclass : pwm_env
+endclass : ${module_instance_name}_env

hw/ip_templates/pwm/dv/env/pwm_env_cfg.sv renamed to hw/ip_templates/pwm/dv/env/pwm_env_cfg.sv.tpl

@@ -2,8 +2,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-class pwm_env_cfg extends cip_base_env_cfg #(.RAL_T(pwm_reg_block));
-  `uvm_object_utils_begin(pwm_env_cfg)
+class ${module_instance_name}_env_cfg extends cip_base_env_cfg #(.RAL_T(${module_instance_name}_reg_block));
+  `uvm_object_utils_begin(${module_instance_name}_env_cfg)
   `uvm_object_utils_end
 
   `uvm_object_new
@@ -26,10 +26,10 @@ class pwm_env_cfg extends cip_base_env_cfg #(.RAL_T(pwm_reg_block));
 
   // Return the scaled core clock frequency in MHz.
   extern virtual function int get_clk_core_freq();
-endclass : pwm_env_cfg
+endclass : ${module_instance_name}_env_cfg
 
-function void pwm_env_cfg::initialize(bit [31:0] csr_base_addr = '1);
-  list_of_alerts = pwm_env_pkg::LIST_OF_ALERTS;
+function void ${module_instance_name}_env_cfg::initialize(bit [31:0] csr_base_addr = '1);
+  list_of_alerts = ${module_instance_name}_env_pkg::LIST_OF_ALERTS;
   super.initialize(csr_base_addr);
 
   // Set up the configuration for each of the monitors.
@@ -46,7 +46,7 @@ function void pwm_env_cfg::initialize(bit [31:0] csr_base_addr = '1);
 endfunction
 
 // Return the scaled core clock frequency in MHz.
-function int pwm_env_cfg::get_clk_core_freq();
+function int ${module_instance_name}_env_cfg::get_clk_core_freq();
   real scaled = clk_rst_vif.clk_freq_mhz * clk_scale / 1024;
   `DV_CHECK_FATAL(clk_rst_vif.clk_freq_mhz > 0)
   `DV_CHECK_FATAL(scaled > 0)

hw/ip_templates/pwm/dv/env/pwm_env_cov.sv renamed to hw/ip_templates/pwm/dv/env/pwm_env_cov.sv.tpl

@@ -8,11 +8,11 @@
  * Covergroups may also be wrapped inside helper classes if needed.
  */
 
-class pwm_env_cov extends cip_base_env_cov #(.CFG_T(pwm_env_cfg));
-  `uvm_component_utils(pwm_env_cov)
+class ${module_instance_name}_env_cov extends cip_base_env_cov #(.CFG_T(${module_instance_name}_env_cfg));
+  `uvm_component_utils(${module_instance_name}_env_cov)
 
   // the base class provides the following handles for use:
-  // pwm_env_cfg: cfg
+  // ${module_instance_name}_env_cfg: cfg
 
   // covergroups
 

hw/ip_templates/pwm/dv/env/pwm_env_pkg.sv renamed to hw/ip_templates/pwm/dv/env/pwm_env_pkg.sv.tpl

@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-package pwm_env_pkg;
+package ${module_instance_name}_env_pkg;
   import uvm_pkg::*;
   import top_pkg::*;
   import dv_utils_pkg::*;
@@ -12,10 +12,10 @@ package pwm_env_pkg;
   import dv_base_reg_pkg::*;
   import csr_utils_pkg::*;
   import pwm_monitor_pkg::*;
-  import pwm_reg_pkg::*;
-  import pwm_ral_pkg::*;
+  import ${module_instance_name}_reg_pkg::*;
+  import ${module_instance_name}_ral_pkg::*;
 
-  parameter uint PWM_NUM_CHANNELS = pwm_reg_pkg::NOutputs;
+  parameter uint PWM_NUM_CHANNELS = ${module_instance_name}_reg_pkg::NOutputs;
 
   `include "uvm_macros.svh"
   `include "dv_macros.svh"
@@ -73,11 +73,11 @@ package pwm_env_pkg;
   endfunction
 
   // Package sources
-  `include "pwm_env_cfg.sv"
-  `include "pwm_env_cov.sv"
-  `include "pwm_virtual_sequencer.sv"
-  `include "pwm_scoreboard.sv"
-  `include "pwm_env.sv"
-  `include "pwm_vseq_list.sv"
+  `include "${module_instance_name}_env_cfg.sv"
+  `include "${module_instance_name}_env_cov.sv"
+  `include "${module_instance_name}_virtual_sequencer.sv"
+  `include "${module_instance_name}_scoreboard.sv"
+  `include "${module_instance_name}_env.sv"
+  `include "${module_instance_name}_vseq_list.sv"
 
-endpackage : pwm_env_pkg
+endpackage : ${module_instance_name}_env_pkg

hw/ip_templates/pwm/dv/env/pwm_scoreboard.sv renamed to hw/ip_templates/pwm/dv/env/pwm_scoreboard.sv.tpl

@@ -2,12 +2,12 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-class pwm_scoreboard extends cip_base_scoreboard #(
-      .CFG_T(pwm_env_cfg),
-      .RAL_T(pwm_reg_block),
-      .COV_T(pwm_env_cov)
+class ${module_instance_name}_scoreboard extends cip_base_scoreboard #(
+      .CFG_T(${module_instance_name}_env_cfg),
+      .RAL_T(${module_instance_name}_reg_block),
+      .COV_T(${module_instance_name}_env_cov)
      );
-  `uvm_component_utils(pwm_scoreboard)
+  `uvm_component_utils(${module_instance_name}_scoreboard)
   `uvm_component_new
 
   // TLM agent FIFOs.
@@ -85,16 +85,16 @@ class pwm_scoreboard extends cip_base_scoreboard #(
   // configuration registers.
   extern function void generate_exp_item(ref pwm_item item, input int unsigned channel);
 
-endclass : pwm_scoreboard
+endclass : ${module_instance_name}_scoreboard
 
-function void pwm_scoreboard::build_phase(uvm_phase phase);
+function void ${module_instance_name}_scoreboard::build_phase(uvm_phase phase);
   super.build_phase(phase);
   for (int i = 0; i < PWM_NUM_CHANNELS; i++) begin
     item_fifo[i] = new($sformatf("item_fifo[%0d]", i), this);
   end
 endfunction
 
-task pwm_scoreboard::run_phase(uvm_phase phase);
+task ${module_instance_name}_scoreboard::run_phase(uvm_phase phase);
   super.run_phase(phase);
   if (cfg.en_scb) begin
     // For each PWM output create one checker process and one clock/output monitor process.
@@ -112,14 +112,14 @@ task pwm_scoreboard::run_phase(uvm_phase phase);
   end
 endtask
 
-function void pwm_scoreboard::check_phase(uvm_phase phase);
+function void ${module_instance_name}_scoreboard::check_phase(uvm_phase phase);
   super.check_phase(phase);
   for (int i = 0; i < PWM_NUM_CHANNELS; i++) begin
     `DV_EOT_PRINT_TLM_FIFO_CONTENTS(pwm_item, item_fifo[i])
   end
 endfunction
 
-task pwm_scoreboard::process_tl_access(tl_seq_item   item,
+task ${module_instance_name}_scoreboard::process_tl_access(tl_seq_item   item,
                                        tl_channels_e channel,
                                        string        ral_name);
   string txt;
@@ -271,7 +271,7 @@ task pwm_scoreboard::process_tl_access(tl_seq_item   item,
   end
 endtask
 
-function void pwm_scoreboard::reset(string kind = "HARD");
+function void ${module_instance_name}_scoreboard::reset(string kind = "HARD");
   super.reset(kind);
   `uvm_info(`gfn, "Reset flushing all channels", UVM_MEDIUM)
   for (int unsigned channel = 0; channel < PWM_NUM_CHANNELS; channel++) begin
@@ -281,7 +281,7 @@ function void pwm_scoreboard::reset(string kind = "HARD");
 endfunction
 
 // Monitor whether the TL-UL clock is running and whether the PWM output is changing.
-task pwm_scoreboard::monitor_clock(int channel);
+task ${module_instance_name}_scoreboard::monitor_clock(int channel);
   forever begin
     // The core clock is always running so we may use this to monitor whether the TL-UL bus clock
     // is gated.
@@ -299,14 +299,14 @@ endtask
 // We allow a little difference in the timing of the blink state transitions until we've
 // synchronized to this PWM output. Until that point a mismatch may legitimately occur between
 // the observed and predicted cycles.
-function bit pwm_scoreboard::blink_state_untrusted(int unsigned channel);
+function bit ${module_instance_name}_scoreboard::blink_state_untrusted(int unsigned channel);
   // Until we've synchronized, drift is permitted in either direction.
   return !synchronized[channel] &&
             (blink_cnt[channel] < SettleTime || ignore_state_change[channel] > 0);
 endfunction
 
 // Adjust channel state to synchronize with the monitor/DUT output.
-function void pwm_scoreboard::synchronize_blink_state(int unsigned channel);
+function void ${module_instance_name}_scoreboard::synchronize_blink_state(int unsigned channel);
   `uvm_info(`gfn, $sformatf("Synchronizing on channel %0d (ignore %0d blink_cnt %0d)", channel,
                             ignore_state_change[channel], blink_cnt[channel]), UVM_MEDIUM)
   if (ignore_state_change[channel] > 0) begin
@@ -331,7 +331,7 @@ function void pwm_scoreboard::synchronize_blink_state(int unsigned channel);
   ignore_state_change[channel] = 0;
 endfunction
 
-task pwm_scoreboard::compare_trans(int unsigned channel);
+task ${module_instance_name}_scoreboard::compare_trans(int unsigned channel);
   pwm_item compare_item = new($sformatf("expected_item_%0d", channel));
   pwm_item input_item   = new($sformatf("input_item_%0d", channel));
   // Count of predictions made.
@@ -436,7 +436,7 @@ task pwm_scoreboard::compare_trans(int unsigned channel);
 endtask : compare_trans
 
 // Advance the blink state at the end of the 'BLINK_PARAM.X+1' or 'BLINK_PARAM.Y+1' pulse cycles.
-function void pwm_scoreboard::advance_blink_state(int unsigned channel);
+function void ${module_instance_name}_scoreboard::advance_blink_state(int unsigned channel);
   `uvm_info(`gfn, $sformatf("Advancing blink state for channel %0d", channel), UVM_HIGH)
   if (channel_param[channel].HtbtEn) begin
     dc_mod_e dc_mod = (duty_cycle[channel].A > duty_cycle[channel].B) ? LargeA : LargeB;
@@ -500,7 +500,7 @@ function void pwm_scoreboard::advance_blink_state(int unsigned channel);
   end
 endfunction
 
-function void pwm_scoreboard::generate_exp_item(ref pwm_item item, input int unsigned channel);
+function void ${module_instance_name}_scoreboard::generate_exp_item(ref pwm_item item, input int unsigned channel);
   uint beats_cycle     = 0;
   uint period          = 0;
   uint active_cycles   = 0;

hw/ip_templates/pwm/dv/env/pwm_virtual_sequencer.sv

@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ${module_instance_name}_virtual_sequencer extends cip_base_virtual_sequencer #(
+  .CFG_T(${module_instance_name}_env_cfg),
+  .COV_T(${module_instance_name}_env_cov)
+);
+
+  `uvm_component_utils(${module_instance_name}_virtual_sequencer)
+  `uvm_component_new
+
+endclass : ${module_instance_name}_virtual_sequencer