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[crypto] Add rv_core_ibex function that checks CPUCTRL config
The CPUCTRL Ibex register contains two security-relevant entries (dummy_instr_en and data_ind_timing). As these two security features should be enabled when using CryptoLib, the newly added function checks whether they are enabled. Signed-off-by: Pascal Nasahl <[email protected]>
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sw/device/lib/crypto/drivers/rv_core_ibex.c

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@@ -25,8 +25,37 @@ enum {
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* CSR_REG_CPUCTRL[0] is the iCache configuration field.
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*/
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kCpuctrlICacheMask = 1,
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/**
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* Mask for extracting cpuctrl_csr[1] and cpuctrl_csr[2] is 0b11.
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*/
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kMask = 0x3,
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/**
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* The first item is cpuctrl_csr[1].
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*/
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kIdx = 0x1,
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/**
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* cpuctrl_csr[1] and cpuctrl_csr[2] should be set to 0b11.
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*/
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kExpectedConfig = 0x3,
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};
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hardened_bool_t ibex_check_security_config(void) {
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uint32_t cpuctrl_csr;
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CSR_READ(CSR_REG_CPUCTRL, &cpuctrl_csr);
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// Check if cpuctrl_csr[1] (data_ind_timing) and cpuctrl_csr[2]
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// (dummy_instr_en) is set to 1 (enabled).
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bitfield_field32_t cpuctrl_mask = {.mask = kMask, .index = kIdx};
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uint32_t cpuctrl_cfg = bitfield_field32_read(cpuctrl_csr, cpuctrl_mask);
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if (launder32(cpuctrl_cfg) != kExpectedConfig) {
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return kHardenedBoolFalse;
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}
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HARDENED_CHECK_EQ(cpuctrl_cfg, kExpectedConfig);
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return kHardenedBoolTrue;
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}
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/**
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* Blocks until data is ready in the RND register.
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*/

sw/device/lib/crypto/drivers/rv_core_ibex.h

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@@ -31,6 +31,19 @@ status_t ibex_disable_icache(hardened_bool_t *icache_enabled);
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*/
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void ibex_restore_icache(hardened_bool_t icache_enabled);
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/**
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* Checks if the expected Ibex Security Features are enabled.
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*
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* This function reads Ibex cpuctrl register and checks, whether the following
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* security features are enabled:
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* - data_ind_timing
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* - dummy_instr_en
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*
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* @returns Whether the config matches the expected secure config.
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*/
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OT_WARN_UNUSED_RESULT
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hardened_bool_t ibex_check_security_config(void);
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/**
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* Get random data from the EDN0 interface.
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*

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