[csrng/rtl] Remove the pdata FIFO from ctr_drbg_upd

This commit removes the pdata FIFO from the csrng_ctr_drbg_upd stage. As
a consquence, pdata for the final step is now taken from the request
fifo right at the request port of this module. This requires the
internal control logic to wait for the block_encrypt module to process
all three requests until the upstream req_rdy_o can be asserted. This
change, however, does not reduce performance/throughput of the CSRNG.

Signed-off-by: Florian Glaser <[email protected]>

Author: glaserf

hw/ip/csrng/data/csrng.hjson

@@ -773,15 +773,6 @@
                 This bit will stay set until the next reset.
                 '''
         }
-        { bits: "8",
-          name: "SFIFO_PDATA_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                pdata FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
         { bits: "9",
           name: "SFIFO_FINAL_ERR",
           desc: '''

hw/ip/csrng/doc/registers.md

@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
 Hardware detection of error conditions status register
 - Offset: `0x54`
 - Reset default: `0x0`
-- Reset mask: `0x77f0fffb`
+- Reset mask: `0x77f0fefb`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_UPDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_PDATA_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_UPDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
 ```
 
 |  Bits  |  Type  |  Reset  | Name                                                |
@@ -585,7 +585,7 @@ Hardware detection of error conditions status register
 |   11   |   ro   |   0x0   | [SFIFO_GRCSTAGE_ERR](#err_code--sfifo_grcstage_err) |
 |   10   |   ro   |   0x0   | [SFIFO_GBENCACK_ERR](#err_code--sfifo_gbencack_err) |
 |   9    |   ro   |   0x0   | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err)       |
-|   8    |   ro   |   0x0   | [SFIFO_PDATA_ERR](#err_code--sfifo_pdata_err)       |
+|   8    |        |         | Reserved                                            |
 |   7    |   ro   |   0x0   | [SFIFO_BENCACK_ERR](#err_code--sfifo_bencack_err)   |
 |   6    |   ro   |   0x0   | [SFIFO_BENCREQ_ERR](#err_code--sfifo_bencreq_err)   |
 |   5    |   ro   |   0x0   | [SFIFO_UPDREQ_ERR](#err_code--sfifo_updreq_err)     |
@@ -698,12 +698,6 @@ final FIFO. The type of error is reflected in the type status
 bits (bits 28 through 30 of this register).
 This bit will stay set until the next reset.
 
-### ERR_CODE . SFIFO_PDATA_ERR
-This bit will be set to one when an error has been detected for the
-pdata FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
 ### ERR_CODE . SFIFO_BENCACK_ERR
 This bit will be set to one when an error has been detected for the
 bencack FIFO. The type of error is reflected in the type status

hw/ip/csrng/dv/env/csrng_env_pkg.sv

@@ -61,7 +61,6 @@ package csrng_env_pkg;
     sfifo_updreq_error   = 5,
     sfifo_bencreq_error  = 6,
     sfifo_bencack_error  = 7,
-    sfifo_pdata_error    = 8,
     sfifo_final_error    = 9,
     sfifo_gbencack_error = 10,
     sfifo_grcstage_error = 11,
@@ -90,7 +89,6 @@ package csrng_env_pkg;
     sfifo_updreq_err        = 5,
     sfifo_bencreq_err       = 6,
     sfifo_bencack_err       = 7,
-    sfifo_pdata_err         = 8,
     sfifo_final_err         = 9,
     sfifo_gbencack_err      = 10,
     sfifo_grcstage_err      = 11,
@@ -116,7 +114,6 @@ package csrng_env_pkg;
     sfifo_updreq_err_test   = 31,
     sfifo_bencreq_err_test  = 32,
     sfifo_bencack_err_test  = 33,
-    sfifo_pdata_err_test    = 34,
     sfifo_final_err_test    = 35,
     sfifo_gbencack_err_test = 36,
     sfifo_grcstage_err_test = 37,
@@ -144,7 +141,6 @@ package csrng_env_pkg;
     SFIFO_UPDREQ_ERR   = 5,
     SFIFO_BENCREQ_ERR  = 6,
     SFIFO_BENCACK_ERR  = 7,
-    SFIFO_PDATA_ERR    = 8,
     SFIFO_FINAL_ERR    = 9,
     SFIFO_GBENCACK_ERR = 10,
     SFIFO_GRCSTAGE_ERR = 11,
@@ -183,7 +179,6 @@ package csrng_env_pkg;
     sfifo_grcstage = 4,
     sfifo_gbencack = 5,
     sfifo_final    = 6,
-    sfifo_pdata    = 7,
     sfifo_bencack  = 8,
     sfifo_bencreq  = 9,
     sfifo_updreq   = 10,

hw/ip/csrng/dv/env/csrng_path_if.sv

@@ -19,7 +19,7 @@ interface csrng_path_if
                                             ".u_csrng_cmd_stage.", fifo_name, "_", which_path};
       "sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
                                                                fifo_name, "_", which_path};
-      "sfifo_updreq", "sfifo_bencreq", "sfifo_bencack", "sfifo_pdata", "sfifo_final": return
+      "sfifo_updreq", "sfifo_bencreq", "sfifo_bencack", "sfifo_final": return
         {core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
       "sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits":
         return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1),

hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv

@@ -102,7 +102,7 @@ class csrng_err_vseq extends csrng_base_vseq;
       sfifo_cmd_err, sfifo_genbits_err, sfifo_rcstage_err, sfifo_keyvrc_err,
       sfifo_bencreq_err, sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
       sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, sfifo_updreq_err,
-      sfifo_bencack_err, sfifo_pdata_err, sfifo_ggenreq_err: begin
+      sfifo_bencack_err, sfifo_ggenreq_err: begin
         fld = csr.get_field_by_name(fld_name);
         fifo_base_path = fld_name.substr(0, last_index-1);
 
@@ -115,7 +115,7 @@ class csrng_err_vseq extends csrng_base_vseq;
                   UVM_MEDIUM)
 
         if (cfg.which_err_code == sfifo_updreq_err || cfg.which_err_code == sfifo_bencack_err ||
-            cfg.which_err_code == sfifo_pdata_err || cfg.which_err_code == sfifo_ggenreq_err) begin
+            cfg.which_err_code == sfifo_ggenreq_err) begin
           force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts, fld,
                                         1'b1, cfg.which_fifo_err);
 
@@ -263,8 +263,8 @@ class csrng_err_vseq extends csrng_base_vseq;
         value2 = fifo_err_value[1][path_key];
 
         if (cfg.which_err_code == fifo_read_error &&
-           ((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_pdata) ||
-            (cfg.which_fifo == sfifo_bencack) || (cfg.which_fifo == sfifo_updreq)))
+           ((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack) ||
+            (cfg.which_fifo == sfifo_updreq)))
         begin
           force_fifo_err_exception(path1, path2, 1'b1, 1'b0, 1'b0, fld, 1'b1);
 
@@ -305,7 +305,7 @@ class csrng_err_vseq extends csrng_base_vseq;
       end
       sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_rcstage_err_test,
       sfifo_keyvrc_err_test, sfifo_updreq_err_test, sfifo_bencreq_err_test, sfifo_bencack_err_test,
-      sfifo_pdata_err_test, sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
+      sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
       sfifo_ggenreq_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test,
       sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_gen_sm_err_test,
       drbg_updbe_sm_err_test, drbg_updob_sm_err_test, aes_cipher_sm_err_test, cmd_gen_cnt_err_test,

hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv

@@ -223,8 +223,7 @@ class csrng_intr_vseq extends csrng_base_vseq;
       sfifo_cmd_error, sfifo_genbits_error, sfifo_rcstage_error,
       sfifo_keyvrc_error, sfifo_bencreq_error, sfifo_final_error, sfifo_gbencack_error,
       sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error,
-      sfifo_cmdid_error, sfifo_updreq_error, sfifo_bencack_error, sfifo_pdata_error,
-      sfifo_ggenreq_error: begin
+      sfifo_cmdid_error, sfifo_updreq_error, sfifo_bencack_error, sfifo_ggenreq_error: begin
         fifo_base_path = fld_name.substr(0, last_index-1);
 
         foreach (path_exts[i]) begin
@@ -233,7 +232,6 @@ class csrng_intr_vseq extends csrng_base_vseq;
         end
         if (cfg.which_fatal_err == sfifo_updreq_error ||
             cfg.which_fatal_err == sfifo_bencack_error ||
-            cfg.which_fatal_err == sfifo_pdata_error ||
             cfg.which_fatal_err == sfifo_ggenreq_error) begin
           force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts,
                                         ral.intr_state.cs_fatal_err, 1'b1, cfg.which_fifo_err);
@@ -312,8 +310,8 @@ class csrng_intr_vseq extends csrng_base_vseq;
         value2 = fifo_err_value[1][path_key];
 
         if (cfg.which_fatal_err == fifo_read_error &&
-           ((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_pdata) ||
-            (cfg.which_fifo == sfifo_bencack) || (cfg.which_fifo == sfifo_updreq)))
+           ((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack) ||
+            (cfg.which_fifo == sfifo_updreq)))
         begin
           force_fifo_err_exception(path1, path2, value1, value2, 1'b0, ral.intr_state.cs_fatal_err,
                                    1'b1);

hw/ip/csrng/rtl/csrng_core.sv

@@ -145,8 +145,6 @@ module csrng_core import csrng_pkg::*; #(
   logic [2:0]                  ctr_drbg_upd_sfifo_bencreq_err;
   logic                        ctr_drbg_upd_sfifo_bencack_err_sum;
   logic [2:0]                  ctr_drbg_upd_sfifo_bencack_err;
-  logic                        ctr_drbg_upd_sfifo_pdata_err_sum;
-  logic [2:0]                  ctr_drbg_upd_sfifo_pdata_err;
   logic                        ctr_drbg_upd_sfifo_final_err_sum;
   logic [2:0]                  ctr_drbg_upd_sfifo_final_err;
   logic                        ctr_drbg_gen_sfifo_gbencack_err_sum;
@@ -439,7 +437,6 @@ module csrng_core import csrng_pkg::*; #(
          ctr_drbg_upd_sfifo_updreq_err_sum ||
          ctr_drbg_upd_sfifo_bencreq_err_sum ||
          ctr_drbg_upd_sfifo_bencack_err_sum ||
-         ctr_drbg_upd_sfifo_pdata_err_sum ||
          ctr_drbg_upd_sfifo_final_err_sum ||
          ctr_drbg_gen_sfifo_gbencack_err_sum ||
          ctr_drbg_gen_sfifo_grcstage_err_sum ||
@@ -465,8 +462,6 @@ module csrng_core import csrng_pkg::*; #(
          err_code_test_bit[6];
   assign ctr_drbg_upd_sfifo_bencack_err_sum = (|ctr_drbg_upd_sfifo_bencack_err) ||
          err_code_test_bit[7];
-  assign ctr_drbg_upd_sfifo_pdata_err_sum = (|ctr_drbg_upd_sfifo_pdata_err) ||
-         err_code_test_bit[8];
   assign ctr_drbg_upd_sfifo_final_err_sum = (|ctr_drbg_upd_sfifo_final_err) ||
          err_code_test_bit[9];
   assign ctr_drbg_gen_sfifo_gbencack_err_sum = (|ctr_drbg_gen_sfifo_gbencack_err) ||
@@ -503,7 +498,6 @@ module csrng_core import csrng_pkg::*; #(
          ctr_drbg_gen_sfifo_grcstage_err[2] ||
          ctr_drbg_gen_sfifo_gbencack_err[2] ||
          ctr_drbg_upd_sfifo_final_err[2] ||
-         ctr_drbg_upd_sfifo_pdata_err[2] ||
          ctr_drbg_upd_sfifo_bencack_err[2] ||
          ctr_drbg_upd_sfifo_bencreq_err[2] ||
          ctr_drbg_upd_sfifo_updreq_err[2] ||
@@ -520,7 +514,6 @@ module csrng_core import csrng_pkg::*; #(
          ctr_drbg_gen_sfifo_grcstage_err[1] ||
          ctr_drbg_gen_sfifo_gbencack_err[1] ||
          ctr_drbg_upd_sfifo_final_err[1] ||
-         ctr_drbg_upd_sfifo_pdata_err[1] ||
          ctr_drbg_upd_sfifo_bencack_err[1] ||
          ctr_drbg_upd_sfifo_bencreq_err[1] ||
          ctr_drbg_upd_sfifo_updreq_err[1] ||
@@ -537,7 +530,6 @@ module csrng_core import csrng_pkg::*; #(
          ctr_drbg_gen_sfifo_grcstage_err[0] ||
          ctr_drbg_gen_sfifo_gbencack_err[0] ||
          ctr_drbg_upd_sfifo_final_err[0] ||
-         ctr_drbg_upd_sfifo_pdata_err[0] ||
          ctr_drbg_upd_sfifo_bencack_err[0] ||
          ctr_drbg_upd_sfifo_bencreq_err[0] ||
          ctr_drbg_upd_sfifo_updreq_err[0] ||
@@ -576,10 +568,6 @@ module csrng_core import csrng_pkg::*; #(
   assign hw2reg.err_code.sfifo_bencack_err.de = cs_enable_fo[9] &&
          ctr_drbg_upd_sfifo_bencack_err_sum;
 
-  assign hw2reg.err_code.sfifo_pdata_err.d = 1'b1;
-  assign hw2reg.err_code.sfifo_pdata_err.de = cs_enable_fo[10] &&
-         ctr_drbg_upd_sfifo_pdata_err_sum;
-
   assign hw2reg.err_code.sfifo_final_err.d = 1'b1;
   assign hw2reg.err_code.sfifo_final_err.de = cs_enable_fo[11] &&
          ctr_drbg_upd_sfifo_final_err_sum;
@@ -1314,7 +1302,6 @@ module csrng_core import csrng_pkg::*; #(
     .fifo_updreq_err_o     (ctr_drbg_upd_sfifo_updreq_err),
     .fifo_bencreq_err_o    (ctr_drbg_upd_sfifo_bencreq_err),
     .fifo_bencack_err_o    (ctr_drbg_upd_sfifo_bencack_err),
-    .fifo_pdata_err_o      (ctr_drbg_upd_sfifo_pdata_err),
     .fifo_final_err_o      (ctr_drbg_upd_sfifo_final_err),
     .sm_block_enc_req_err_o(drbg_updbe_sm_err),
     .sm_block_enc_rsp_err_o(drbg_updob_sm_err)
@@ -1526,8 +1513,8 @@ module csrng_core import csrng_pkg::*; #(
   logic               unused_state_db_inst_state;
 
   assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[27:26]) ||
-                                    err_code_test_bit[2];
-  assign unused_enable_fo = cs_enable_fo[4];
+                                    err_code_test_bit[8] || err_code_test_bit[2];
+  assign unused_enable_fo = cs_enable_fo[10] | cs_enable_fo[4];
   assign unused_reg2hw_genbits = (|reg2hw.genbits.q);
   assign unused_int_state_val = (|reg2hw.int_state_val.q);
   assign unused_reseed_interval = reg2hw.reseed_interval.qe;