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[darjeeling] No clk_div_2 clock
Signed-off-by: Robert Schilling <[email protected]>
1 parent eaf6d2c commit a3cc851

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41 files changed

+122
-660
lines changed

‎hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson‎

Lines changed: 2 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -54,14 +54,6 @@
5454
]
5555
derived_srcs:
5656
[
57-
{
58-
name: io_div2
59-
aon: no
60-
freq: "500000000"
61-
ref: false
62-
div: "2"
63-
src: io
64-
}
6557
{
6658
name: io_div4
6759
aon: no
@@ -96,7 +88,6 @@
9688
clk_aon_powerup: aon
9789
clk_main_powerup: main
9890
clk_io_powerup: io
99-
clk_io_div2_powerup: io_div2
10091
}
10192
}
10293
{
@@ -143,7 +134,6 @@
143134
clocks:
144135
{
145136
clk_io_div4_peri: io_div4
146-
clk_io_div2_peri: io_div2
147137
clk_aon_peri: aon
148138
}
149139
}
@@ -232,20 +222,6 @@
232222
parent: por_aon
233223
clock: io
234224
}
235-
{
236-
name: por_io_div2
237-
gen: true
238-
type: top
239-
domains:
240-
[
241-
Aon
242-
]
243-
shadowed: false
244-
sw: false
245-
path: rstmgr_aon_resets.rst_por_io_div2_n
246-
parent: por_aon
247-
clock: io_div2
248-
}
249225
{
250226
name: por_io_div4
251227
gen: true
@@ -303,20 +279,6 @@
303279
parent: lc_src
304280
clock: io
305281
}
306-
{
307-
name: lc_io_div2
308-
gen: true
309-
type: top
310-
domains:
311-
[
312-
Aon
313-
]
314-
shadowed: false
315-
sw: false
316-
path: rstmgr_aon_resets.rst_lc_io_div2_n
317-
parent: lc_src
318-
clock: io_div2
319-
}
320282
{
321283
name: lc_io_div4
322284
gen: true
@@ -747,7 +709,7 @@
747709
clock_srcs:
748710
{
749711
clk_i: io_div4
750-
scan_clk_i: io_div2
712+
scan_clk_i: io_div4
751713
}
752714
clock_group: peri
753715
reset_connections:
@@ -765,7 +727,7 @@
765727
clock_connections:
766728
{
767729
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
768-
scan_clk_i: clkmgr_aon_clocks.clk_io_div2_peri
730+
scan_clk_i: clkmgr_aon_clocks.clk_io_div4_peri
769731
}
770732
memory: {}
771733
param_list:
@@ -3032,7 +2994,6 @@
30322994
clk_aon_i: aon
30332995
clk_main_i: main
30342996
clk_io_i: io
3035-
clk_io_div2_i: io_div2
30362997
clk_io_div4_i: io_div4
30372998
}
30382999
clock_group: powerup
@@ -3062,7 +3023,6 @@
30623023
clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup
30633024
clk_main_i: clkmgr_aon_clocks.clk_main_powerup
30643025
clk_io_i: clkmgr_aon_clocks.clk_io_powerup
3065-
clk_io_div2_i: clkmgr_aon_clocks.clk_io_div2_powerup
30663026
clk_io_div4_i: clkmgr_aon_clocks.clk_io_div4_powerup
30673027
}
30683028
param_decl: {}
@@ -3261,11 +3221,6 @@
32613221
name: lc_io
32623222
domain: Aon
32633223
}
3264-
rst_io_div2_ni:
3265-
{
3266-
name: lc_io_div2
3267-
domain: Aon
3268-
}
32693224
rst_io_div4_ni:
32703225
{
32713226
name: lc_io_div4
@@ -3286,11 +3241,6 @@
32863241
name: por_io
32873242
domain: Aon
32883243
}
3289-
rst_root_io_div2_ni:
3290-
{
3291-
name: por_io_div2
3292-
domain: Aon
3293-
}
32943244
rst_root_io_div4_ni:
32953245
{
32963246
name: por_io_div4
@@ -20896,7 +20846,6 @@
2089620846
clocks:
2089720847
{
2089820848
clk_io_div4_peri: io_div4
20899-
clk_io_div2_peri: io_div2
2090020849
clk_aon_peri: aon
2090120850
}
2090220851
}
@@ -20920,7 +20869,6 @@
2092020869
clocks:
2092120870
{
2092220871
clk_io_div4_peri: io_div4
20923-
clk_io_div2_peri: io_div2
2092420872
clk_aon_peri: aon
2092520873
}
2092620874
}
@@ -20944,7 +20892,6 @@
2094420892
clocks:
2094520893
{
2094620894
clk_io_div4_peri: io_div4
20947-
clk_io_div2_peri: io_div2
2094820895
clk_aon_peri: aon
2094920896
}
2095020897
}
@@ -21014,7 +20961,6 @@
2101420961
clocks:
2101520962
{
2101620963
clk_io_div4_peri: io_div4
21017-
clk_io_div2_peri: io_div2
2101820964
clk_aon_peri: aon
2101920965
}
2102020966
}
@@ -21041,7 +20987,6 @@
2104120987
clk_aon_powerup: aon
2104220988
clk_main_powerup: main
2104320989
clk_io_powerup: io
21044-
clk_io_div2_powerup: io_div2
2104520990
}
2104620991
}
2104720992
clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup
@@ -21067,7 +21012,6 @@
2106721012
clk_aon_powerup: aon
2106821013
clk_main_powerup: main
2106921014
clk_io_powerup: io
21070-
clk_io_div2_powerup: io_div2
2107121015
}
2107221016
}
2107321017
clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup

‎hw/top_darjeeling/data/top_darjeeling.hjson‎

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,6 @@
6767
// src: From which clock source is the clock derived
6868
// div: Ratio between derived clock and source clock
6969
derived_srcs: [
70-
{ name: "io_div2", aon: "no", div: 2, src: "io", freq: "500000000" }
7170
{ name: "io_div4", aon: "no", div: 4, src: "io", freq: "250000000" }
7271
],
7372

@@ -150,12 +149,10 @@
150149
{ name: "sys_src", gen: false, type: "int", clock: "io_div4" }
151150
{ name: "por", gen: true, type: "top", parent: "por_aon", clock: "main" }
152151
{ name: "por_io", gen: true, type: "top", parent: "por_aon", clock: "io" }
153-
{ name: "por_io_div2", gen: true , type: "top", parent: "por_aon", clock: "io_div2" }
154152
{ name: "por_io_div4", gen: true , type: "top", parent: "por_aon", clock: "io_div4" }
155153
{ name: "lc", gen: true, type: "top", parent: "lc_src", clock: "main" }
156154
{ name: "lc_aon", gen: true, type: "top", parent: "lc_src", clock: "aon" }
157155
{ name: "lc_io", gen: true, type: "top", parent: "lc_src", clock: "io" }
158-
{ name: "lc_io_div2", gen: true, type: "top", parent: "lc_src", clock: "io_div2" }
159156
{ name: "lc_io_div4", gen: true, type: "top", parent: "lc_src", clock: "io_div4" }
160157
{ name: "sys", gen: true, type: "top", parent: "sys_src", clock: "main" }
161158
{ name: "spi_device", gen: true, type: "top", parent: "lc_src", clock: "io_div4", sw: true }
@@ -312,7 +309,7 @@
312309
},
313310
{ name: "spi_device",
314311
type: "spi_device",
315-
clock_srcs: {clk_i: "io_div4", scan_clk_i: "io_div2"},
312+
clock_srcs: {clk_i: "io_div4", scan_clk_i: "io_div4"},
316313
clock_group: "peri",
317314
reset_connections: {rst_ni: "spi_device"},
318315
base_addr: {
@@ -478,7 +475,7 @@
478475
group: "powerup"
479476
},
480477
clk_por_i: "io_div4", clk_aon_i: "aon", clk_main_i: "main", clk_io_i: "io",
481-
clk_io_div2_i: "io_div2", clk_io_div4_i: "io_div4"
478+
clk_io_div4_i: "io_div4"
482479
},
483480
clock_group: "powerup",
484481
reset_connections: {
@@ -519,12 +516,10 @@
519516
reset_connections: {rst_ni: "lc_io_div4",
520517
rst_aon_ni: "lc_aon"
521518
rst_io_ni: "lc_io",
522-
rst_io_div2_ni: "lc_io_div2",
523519
rst_io_div4_ni: "lc_io_div4",
524520
rst_main_ni: "lc",
525521
rst_root_ni: "por_io_div4",
526522
rst_root_io_ni: "por_io",
527-
rst_root_io_div2_ni: "por_io_div2",
528523
rst_root_io_div4_ni: "por_io_div4",
529524
rst_root_main_ni: "por",
530525
},

‎hw/top_darjeeling/dv/autogen/rstmgr_tgl_excl.cfg‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,9 @@
1515
//=========================================================
1616
-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_n[1]
1717
-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_n[1]
18-
-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div2_n[1]
1918
-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div4_n[1]
2019
-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_aon_n[1]
2120
-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_n[1]
22-
-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_div2_n[1]
2321
-node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_n[0]
2422
-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_device_n[0]
2523
-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_host0_n[0]

‎hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,9 @@
3737
{clock: "clk_main_i", reset: "rst_main_ni"},
3838
{clock: "clk_io_i", reset: "rst_io_ni"},
3939
{clock: "clk_aon_i", reset: "rst_aon_ni"},
40-
{clock: "clk_io_div2_i", reset: "rst_io_div2_ni", internal: true},
4140
{clock: "clk_io_div4_i", reset: "rst_io_div4_ni", internal: true},
4241
{reset: "rst_root_main_ni"},
4342
{reset: "rst_root_io_ni"},
44-
{reset: "rst_root_io_div2_ni"},
4543
{reset: "rst_root_io_div4_ni"},
4644
]
4745
bus_interfaces: [
@@ -70,7 +68,7 @@
7068
{ name: "NumSwGateableClocks",
7169
desc: "Number of SW gateable clocks",
7270
type: "int",
73-
default: "2",
71+
default: "1",
7472
local: "true"
7573
},
7674
{ name: "NumHintableClocks",
@@ -85,9 +83,6 @@
8583
{ name: "CLKMGR.ENABLE.IO_DIV4",
8684
desc: "Gating of IO_DIV4 peripheral clock."
8785
}
88-
{ name: "CLKMGR.ENABLE.IO_DIV2",
89-
desc: "Gating of IO_DIV2 peripheral clock."
90-
}
9186
{ name: "CLKMGR.HINT.AES",
9287
desc: "Gating of AES transactional clock."
9388
}
@@ -446,15 +441,6 @@
446441
1 CLK_IO_DIV4_PERI is enabled.
447442
'''
448443
}
449-
{
450-
bits: "1",
451-
name: "CLK_IO_DIV2_PERI_EN",
452-
resval: 1,
453-
desc: '''
454-
0 CLK_IO_DIV2_PERI is disabled.
455-
1 CLK_IO_DIV2_PERI is enabled.
456-
'''
457-
}
458444
]
459445
// the CLK_ENABLE register cannot be written.
460446
// During top level randomized tests, it is possible to disable the clocks and then access

‎hw/top_darjeeling/ip_autogen/clkmgr/data/top_darjeeling_clkmgr.ipconfig.hjson‎

Lines changed: 0 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -31,21 +31,6 @@
3131
}
3232
derived_clks:
3333
{
34-
io_div2:
35-
{
36-
name: io_div2
37-
aon: false
38-
freq: 500000000
39-
ref: false
40-
div: 2
41-
src:
42-
{
43-
name: io
44-
aon: no
45-
freq: "1000000000"
46-
ref: false
47-
}
48-
}
4934
io_div4:
5035
{
5136
name: io_div4
@@ -104,11 +89,6 @@
10489
src_name: io
10590
endpoint_ip: rstmgr_aon
10691
}
107-
clk_io_div2_powerup:
108-
{
109-
src_name: io_div2
110-
endpoint_ip: rstmgr_aon
111-
}
11292
clk_aon_infra:
11393
{
11494
src_name: aon
@@ -160,11 +140,6 @@
160140
src_name: io_div4
161141
endpoint_ip: uart0
162142
}
163-
clk_io_div2_peri:
164-
{
165-
src_name: io_div2
166-
endpoint_ip: spi_device
167-
}
168143
}
169144
hint_clks:
170145
{
@@ -206,7 +181,6 @@
206181
io:
207182
[
208183
io
209-
io_div2
210184
io_div4
211185
]
212186
}

‎hw/top_darjeeling/ip_autogen/clkmgr/doc/interfaces.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
<!-- BEGIN CMDGEN util/regtool.py --interfaces ./hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson -->
44
Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`clkmgr`** has the following hardware interfaces defined
55
- Primary Clock: **`clk_i`**
6-
- Other Clocks: **`clk_main_i`**, **`clk_io_i`**, **`clk_aon_i`**, **`clk_io_div2_i`**, **`clk_io_div4_i`**
6+
- Other Clocks: **`clk_main_i`**, **`clk_io_i`**, **`clk_aon_i`**, **`clk_io_div4_i`**
77
- Bus Device Interfaces (TL-UL): **`tl`**
88
- Bus Host Interfaces (TL-UL): *none*
99
- Peripheral Pins for Chip IO: *none*

‎hw/top_darjeeling/ip_autogen/clkmgr/doc/registers.md‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -169,19 +169,18 @@ Enable jittery clock
169169
Clock enable for software gateable clocks.
170170
These clocks are directly controlled by software.
171171
- Offset: `0x18`
172-
- Reset default: `0x3`
173-
- Reset mask: `0x3`
172+
- Reset default: `0x1`
173+
- Reset mask: `0x1`
174174

175175
### Fields
176176

177177
```wavejson
178-
{"reg": [{"name": "CLK_IO_DIV4_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_IO_DIV2_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
178+
{"reg": [{"name": "CLK_IO_DIV4_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}
179179
```
180180

181181
| Bits | Type | Reset | Name | Description |
182182
|:------:|:------:|:-------:|:--------------------|:---------------------------------------------------------------|
183-
| 31:2 | | | | Reserved |
184-
| 1 | rw | 0x1 | CLK_IO_DIV2_PERI_EN | 0 CLK_IO_DIV2_PERI is disabled. 1 CLK_IO_DIV2_PERI is enabled. |
183+
| 31:1 | | | | Reserved |
185184
| 0 | rw | 0x1 | CLK_IO_DIV4_PERI_EN | 0 CLK_IO_DIV4_PERI is disabled. 1 CLK_IO_DIV4_PERI is enabled. |
186185

187186
## CLK_HINTS

‎hw/top_darjeeling/ip_autogen/clkmgr/dv/README.md‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ All common types and methods defined at the package level can be found in
4242
`clkmgr_env_pkg`. Some of them in use are:
4343

4444
```systemverilog
45-
localparam int NUM_PERI = 2;
45+
localparam int NUM_PERI = 1;
4646
localparam int NUM_TRANS = 4;
4747
localparam int NUM_ALERTS = 2;
4848
@@ -52,8 +52,7 @@ All common types and methods defined at the package level can be found in
5252
typedef virtual clkmgr_if clkmgr_vif;
5353
typedef virtual clk_rst_if clk_rst_vif;
5454
typedef enum int {
55-
PeriIoDiv4,
56-
PeriIoDiv2
55+
PeriIoDiv4
5756
} peri_e;
5857
typedef enum int {TransAes, TransHmac, TransKmac, TransOtbn} trans_e;
5958
```

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