Skip to content

Commit edfade4

Browse files
h-filalih-filali
committed
[hw/otbn] Add scripts for PROLEAD leakage analysis
Signed-off-by: Hakim Filali <hfilali@lowrisc.org>
1 parent aecee2e commit edfade4

File tree

5 files changed

+492
-0
lines changed

5 files changed

+492
-0
lines changed

‎hw/ip/otbn/pre_sca/prolead/evaluate.sh‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
#!/bin/bash
2+
# Copyright lowRISC contributors (OpenTitan project).
3+
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
# Script for evaluating e.g. the secure adder implementation
7+
# cipher core using PROLEAD.
8+
9+
set -e
10+
11+
case "$1" in
12+
hpc2_and)
13+
TOP_MODULE=otbn_hpc2_and_sca_wrapper
14+
;;
15+
hpc2o)
16+
TOP_MODULE=otbn_hpc2o_sca_wrapper
17+
;;
18+
hpc3_and)
19+
TOP_MODULE=otbn_hpc3_and_sca_wrapper
20+
;;
21+
hpc3o)
22+
TOP_MODULE=otbn_hpc3o_sca_wrapper
23+
;;
24+
*)
25+
# Default case.
26+
TOP_MODULE=otbn_hpc3o_sca_wrapper
27+
;;
28+
esac
29+
if [[ "$#" -gt 1 ]]; then
30+
NETLIST_DIR=$2
31+
else
32+
NETLIST_DIR="${REPO_TOP}/hw/ip/otbn/pre_syn/syn_out/latest/generated"
33+
fi
34+
35+
perl -i -pe "s/(\d+)'h0+/ join(', ', ('1\\'b0') x \$1) /ge" ${NETLIST_DIR}/${TOP_MODULE}_netlist.v
36+
37+
# Create results directory.
38+
OUT_DIR_PREFIX="out/${TOP_MODULE}"
39+
OUT_DIR=$(date +"${OUT_DIR_PREFIX}_%Y_%m_%d_%H_%M_%S")
40+
mkdir -p ${OUT_DIR}
41+
rm -f out/latest
42+
ln -s "${OUT_DIR#out/}" out/latest
43+
44+
echo ${REPO_TOP}/hw/ip/otbn/pre_sca/prolead/server_config_${TOP_MODULE}.json
45+
46+
# Launch the tool.
47+
PROLEAD -l ${REPO_TOP}/hw/ip/otbn/pre_sca/prolead/nang45.json \
48+
-n nang45 \
49+
-d ${NETLIST_DIR}/${TOP_MODULE}_netlist.v \
50+
-m ${TOP_MODULE} \
51+
-rf ${OUT_DIR} \
52+
-c ${REPO_TOP}/hw/ip/otbn/pre_sca/prolead/server_config_${TOP_MODULE}.json

‎hw/ip/otbn/pre_sca/prolead/server_config_otbn_hpc2_and_sca_wrapper.json‎

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,110 @@
1+
{
2+
"performance": {
3+
"max_number_of_threads": "half",
4+
"minimize_probing_sets": "aggressive"
5+
},
6+
"simulation": {
7+
"groups": [
8+
"2'h$",
9+
"2'h0"
10+
],
11+
"number_of_clock_cycles": 6,
12+
"always_random_inputs": [
13+
"rand_i"
14+
],
15+
"input_sequence": [
16+
{
17+
"signals": [
18+
{
19+
"name": "share0_i[1:0]",
20+
"value": "2'h0"
21+
},
22+
{
23+
"name": "share1_i[1:0]",
24+
"value": "2'h0"
25+
},
26+
{
27+
"name": "en_i",
28+
"value": "1'b0"
29+
},
30+
{
31+
"name": "rst_ni",
32+
"value": "1'b1"
33+
}
34+
]
35+
},
36+
{
37+
"signals": [
38+
{
39+
"name": "share0_i[1:0]",
40+
"value": "2'h0"
41+
},
42+
{
43+
"name": "share1_i[1:0]",
44+
"value": "2'h0"
45+
},
46+
{
47+
"name": "en_i",
48+
"value": "1'b0"
49+
},
50+
{
51+
"name": "rst_ni",
52+
"value": "1'b0"
53+
}
54+
]
55+
},
56+
{
57+
"signals": [
58+
{
59+
"name": "share0_i[1:0]",
60+
"value": "group_in0[1:0]"
61+
},
62+
{
63+
"name": "share1_i[1:0]",
64+
"value": "group_in1[1:0]"
65+
},
66+
{
67+
"name": "en_i",
68+
"value": "1'b1"
69+
},
70+
{
71+
"name": "rst_ni",
72+
"value": "1'b1"
73+
}
74+
]
75+
},
76+
{
77+
"signals": [
78+
{
79+
"name": "share0_i[1:0]",
80+
"value": "2'h0"
81+
},
82+
{
83+
"name": "share1_i[1:0]",
84+
"value": "2'h0"
85+
},
86+
{
87+
"name": "en_i",
88+
"value": "1'b0"
89+
},
90+
{
91+
"name": "rst_ni",
92+
"value": "1'b1"
93+
}
94+
]
95+
}
96+
],
97+
"number_of_simulations": 1536000,
98+
"number_of_simulations_per_step": 128000
99+
},
100+
"hardware": {
101+
"clock_signal_name": "clk_i"
102+
},
103+
"side_channel_analysis": {
104+
"order": 1,
105+
"transitional_leakage": true,
106+
"clock_cycles": [
107+
"3-6"
108+
]
109+
}
110+
}

‎hw/ip/otbn/pre_sca/prolead/server_config_otbn_hpc2o_sca_wrapper.json‎

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,110 @@
1+
{
2+
"performance": {
3+
"max_number_of_threads": "half",
4+
"minimize_probing_sets": "aggressive"
5+
},
6+
"simulation": {
7+
"groups": [
8+
"3'h$",
9+
"3'h0"
10+
],
11+
"number_of_clock_cycles": 6,
12+
"always_random_inputs": [
13+
"rand_i"
14+
],
15+
"input_sequence": [
16+
{
17+
"signals": [
18+
{
19+
"name": "share0_i[2:0]",
20+
"value": "3'h0"
21+
},
22+
{
23+
"name": "share1_i[2:0]",
24+
"value": "3'h0"
25+
},
26+
{
27+
"name": "en_i",
28+
"value": "1'b0"
29+
},
30+
{
31+
"name": "rst_ni",
32+
"value": "1'b1"
33+
}
34+
]
35+
},
36+
{
37+
"signals": [
38+
{
39+
"name": "share0_i[2:0]",
40+
"value": "3'h0"
41+
},
42+
{
43+
"name": "share1_i[2:0]",
44+
"value": "3'h0"
45+
},
46+
{
47+
"name": "en_i",
48+
"value": "1'b0"
49+
},
50+
{
51+
"name": "rst_ni",
52+
"value": "1'b0"
53+
}
54+
]
55+
},
56+
{
57+
"signals": [
58+
{
59+
"name": "share0_i[2:0]",
60+
"value": "group_in0[2:0]"
61+
},
62+
{
63+
"name": "share1_i[2:0]",
64+
"value": "group_in1[2:0]"
65+
},
66+
{
67+
"name": "en_i",
68+
"value": "1'b1"
69+
},
70+
{
71+
"name": "rst_ni",
72+
"value": "1'b1"
73+
}
74+
]
75+
},
76+
{
77+
"signals": [
78+
{
79+
"name": "share0_i[2:0]",
80+
"value": "3'h0"
81+
},
82+
{
83+
"name": "share1_i[2:0]",
84+
"value": "3'h0"
85+
},
86+
{
87+
"name": "en_i",
88+
"value": "1'b0"
89+
},
90+
{
91+
"name": "rst_ni",
92+
"value": "1'b1"
93+
}
94+
]
95+
}
96+
],
97+
"number_of_simulations": 1536000,
98+
"number_of_simulations_per_step": 128000
99+
},
100+
"hardware": {
101+
"clock_signal_name": "clk_i"
102+
},
103+
"side_channel_analysis": {
104+
"order": 1,
105+
"transitional_leakage": true,
106+
"clock_cycles": [
107+
"3-6"
108+
]
109+
}
110+
}

‎hw/ip/otbn/pre_sca/prolead/server_config_otbn_hpc3_and_sca_wrapper.json‎

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,110 @@
1+
{
2+
"performance": {
3+
"max_number_of_threads": "half",
4+
"minimize_probing_sets": "aggressive"
5+
},
6+
"simulation": {
7+
"groups": [
8+
"2'h$",
9+
"2'h0"
10+
],
11+
"number_of_clock_cycles": 5,
12+
"always_random_inputs": [
13+
"rand_i[1:0]"
14+
],
15+
"input_sequence": [
16+
{
17+
"signals": [
18+
{
19+
"name": "share0_i[1:0]",
20+
"value": "2'h0"
21+
},
22+
{
23+
"name": "share1_i[1:0]",
24+
"value": "2'h0"
25+
},
26+
{
27+
"name": "en_i",
28+
"value": "1'b0"
29+
},
30+
{
31+
"name": "rst_ni",
32+
"value": "1'b1"
33+
}
34+
]
35+
},
36+
{
37+
"signals": [
38+
{
39+
"name": "share0_i[1:0]",
40+
"value": "2'h0"
41+
},
42+
{
43+
"name": "share1_i[1:0]",
44+
"value": "2'h0"
45+
},
46+
{
47+
"name": "en_i",
48+
"value": "1'b0"
49+
},
50+
{
51+
"name": "rst_ni",
52+
"value": "1'b0"
53+
}
54+
]
55+
},
56+
{
57+
"signals": [
58+
{
59+
"name": "share0_i[1:0]",
60+
"value": "group_in0[1:0]"
61+
},
62+
{
63+
"name": "share1_i[1:0]",
64+
"value": "group_in1[1:0]"
65+
},
66+
{
67+
"name": "en_i",
68+
"value": "1'b1"
69+
},
70+
{
71+
"name": "rst_ni",
72+
"value": "1'b1"
73+
}
74+
]
75+
},
76+
{
77+
"signals": [
78+
{
79+
"name": "share0_i[1:0]",
80+
"value": "2'h0"
81+
},
82+
{
83+
"name": "share1_i[1:0]",
84+
"value": "2'h0"
85+
},
86+
{
87+
"name": "en_i",
88+
"value": "1'b0"
89+
},
90+
{
91+
"name": "rst_ni",
92+
"value": "1'b1"
93+
}
94+
]
95+
}
96+
],
97+
"number_of_simulations": 1536000,
98+
"number_of_simulations_per_step": 128000
99+
},
100+
"hardware": {
101+
"clock_signal_name": "clk_i"
102+
},
103+
"side_channel_analysis": {
104+
"order": 1,
105+
"transitional_leakage": true,
106+
"clock_cycles": [
107+
"3-5"
108+
]
109+
}
110+
}

0 commit comments

Comments
 (0)