[hw,ac_range_check,dv] Templify the DV code for ipgen generation

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

hw/ip_templates/ac_range_check/dv/README.md.tpl

@@ -43,7 +43,7 @@ ${"###"} Compile-time configurations
 [list compile time configurations, if any and what are they used for]
 
 ${"###"} Global types & methods
-All common types and methods defined at the package level can be found in `ac_range_check_env_pkg`.
+All common types and methods defined at the package level can be found in `${module_instance_name}_env_pkg`.
 Some of them in use are:
 ```systemverilog
 [list a few parameters, types & methods; no need to mention all]
@@ -77,7 +77,7 @@ This helps increase the likelihood of hitting the design corners that would othe
 This object aims to provide such run-time controls.
 
 ${"####"} Env cfg
-The `ac_range_check_env_cfg`, environment configuration object provides access to the following elements:
+The `${module_instance_name}_env_cfg`, environment configuration object provides access to the following elements:
 * Build-time controls to configure the UVM environment composition during the `build_phase`
 * Downstream agent configuration objects for ease of lookup from any environment component
   * This includes the `tl_agent_cfg` objects for both TL interfaces

hw/ip_templates/ac_range_check/dv/ac_range_check_sim.core.tpl

@@ -13,8 +13,8 @@ filesets:
 
   files_dv:
     depend:
-      - ${instance_vlnv("lowrisc:dv:ac_range_check_test")}
-      - ${instance_vlnv("lowrisc:dv:ac_range_check_sva")}
+      - ${instance_vlnv(f"lowrisc:dv:{module_instance_name}_test")}
+      - ${instance_vlnv(f"lowrisc:dv:{module_instance_name}_sva")}
     files:
       - tb/tb.sv
     file_type: systemVerilogSource

hw/ip_templates/ac_range_check/dv/ac_range_check_sim_cfg.hjson.tpl

@@ -15,7 +15,7 @@
   tool: xcelium
 
   // Fusesoc core file used for building the file list.
-  fusesoc_core: ${instance_vlnv("lowrisc:dv:ac_range_check_sim:0.1")}
+  fusesoc_core: ${instance_vlnv(f"lowrisc:dv:{module_instance_name}_sim:0.1")}
 
   // Testplan hjson file.
   testplan: "{self_dir}/../data/${module_instance_name}_testplan.hjson"
@@ -33,7 +33,7 @@
                 "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
 
   // Add additional tops for simulation.
-  sim_tops: ["ac_range_check_bind"]
+  sim_tops: ["${module_instance_name}_bind"]
 
   // Default iterations for all tests - each test entry can override this.
   reseed: 50

hw/ip_templates/ac_range_check/dv/env/ac_range_check_dut_cfg.sv renamed to hw/ip_templates/ac_range_check/dv/env/ac_range_check_dut_cfg.sv.tpl

@@ -6,7 +6,7 @@
 // repeating the variable declaration multiple times. On the other hand, their constraints must not
 // be contained in this file, but directly in the files where they are needed as this may lead to
 // some conflicts.
-class ac_range_check_dut_cfg extends uvm_object;
+class ${module_instance_name}_dut_cfg extends uvm_object;
   rand tl_main_vars_t  tl_main_vars;
   rand bit [TL_DW-1:0] range_base[NUM_RANGES];  // Granularity is 32-bit words, 2-LSBs are ignored
   rand bit [TL_DW-1:0] range_limit[NUM_RANGES]; // Granularity is 32-bit words, 2-LSBs are ignored
@@ -19,25 +19,25 @@ class ac_range_check_dut_cfg extends uvm_object;
   extern function void do_print(uvm_printer printer);
 
   // UVM Factory Registration Macro
-  `uvm_object_utils_begin (ac_range_check_dut_cfg)
+  `uvm_object_utils_begin (${module_instance_name}_dut_cfg)
     `uvm_field_sarray_int(range_base, UVM_DEFAULT)
     `uvm_field_sarray_int(range_limit, UVM_DEFAULT)
   `uvm_object_utils_end
-endclass : ac_range_check_dut_cfg
+endclass : ${module_instance_name}_dut_cfg
 
 
-function ac_range_check_dut_cfg::new(string name="");
+function ${module_instance_name}_dut_cfg::new(string name="");
   super.new(name);
 endfunction : new
 
-function void ac_range_check_dut_cfg::post_randomize();
+function void ${module_instance_name}_dut_cfg::post_randomize();
   if (uvm_top.get_report_verbosity_level() >= UVM_HIGH) begin
     this.print();
   end
 endfunction : post_randomize
 
 // Some types are unsupported by the macros and have to be implemented manually
-function void ac_range_check_dut_cfg::do_print(uvm_printer printer);
+function void ${module_instance_name}_dut_cfg::do_print(uvm_printer printer);
   `uvm_info(this.get_name(), "do_print function has been called", UVM_DEBUG);
   super.do_print(printer);
 

hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.core.tpl

@@ -2,7 +2,7 @@ CAPI=2:
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: ${instance_vlnv("lowrisc:dv:ac_range_check_env:0.1")}
+name: ${instance_vlnv(f"lowrisc:dv:{module_instance_name}_env:0.1")}
 description: "AC_RANGE_CHECK DV UVM environment"
 filesets:
   files_dv:
@@ -12,24 +12,24 @@ filesets:
       - lowrisc:dv:dv_base_reg
       - lowrisc:dv:dv_lib
     files:
-      - ac_range_check_env_pkg.sv
-      - ac_range_check_dut_cfg.sv: {is_include_file: true}
-      - ac_range_check_env_cfg.sv: {is_include_file: true}
-      - ac_range_check_env_cov.sv: {is_include_file: true}
-      - ac_range_check_virtual_sequencer.sv: {is_include_file: true}
-      - ac_range_check_scoreboard.sv: {is_include_file: true}
-      - ac_range_check_env.sv: {is_include_file: true}
-      - seq_lib/ac_range_check_vseq_list.sv: {is_include_file: true}
-      - seq_lib/ac_range_check_base_vseq.sv: {is_include_file: true}
-      - seq_lib/ac_range_check_common_vseq.sv: {is_include_file: true}
-      - seq_lib/ac_range_check_smoke_vseq.sv: {is_include_file: true}
+      - ${module_instance_name}_env_pkg.sv
+      - ${module_instance_name}_dut_cfg.sv: {is_include_file: true}
+      - ${module_instance_name}_env_cfg.sv: {is_include_file: true}
+      - ${module_instance_name}_env_cov.sv: {is_include_file: true}
+      - ${module_instance_name}_virtual_sequencer.sv: {is_include_file: true}
+      - ${module_instance_name}_scoreboard.sv: {is_include_file: true}
+      - ${module_instance_name}_env.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_vseq_list.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_base_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_common_vseq.sv: {is_include_file: true}
+      - seq_lib/${module_instance_name}_smoke_vseq.sv: {is_include_file: true}
     file_type: systemVerilogSource
 
 generate:
   ral:
     generator: ralgen
     parameters:
-      name: ac_range_check
+      name: ${module_instance_name}
       ip_hjson: ../../data/${module_instance_name}.hjson
 
 targets:

hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.sv renamed to hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.sv.tpl

@@ -2,13 +2,13 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-class ac_range_check_env extends cip_base_env #(
-    .CFG_T              (ac_range_check_env_cfg),
-    .COV_T              (ac_range_check_env_cov),
+class ${module_instance_name}_env extends cip_base_env #(
+    .CFG_T              (${module_instance_name}_env_cfg),
+    .COV_T              (${module_instance_name}_env_cov),
     .VIRTUAL_SEQUENCER_T(ac_range_check_virtual_sequencer),
     .SCOREBOARD_T       (ac_range_check_scoreboard)
   );
-  `uvm_component_utils(ac_range_check_env)
+  `uvm_component_utils(${module_instance_name}_env)
 
   tl_agent tl_unfilt_agt;
   tl_agent tl_filt_agt;
@@ -17,14 +17,14 @@ class ac_range_check_env extends cip_base_env #(
   extern function new(string name="", uvm_component parent=null);
   extern function void build_phase(uvm_phase phase);
   extern function void connect_phase(uvm_phase phase);
-endclass : ac_range_check_env
+endclass : ${module_instance_name}_env
 
 
-function ac_range_check_env::new(string name="", uvm_component parent=null);
+function ${module_instance_name}_env::new(string name="", uvm_component parent=null);
   super.new(name, parent);
 endfunction : new
 
-function void ac_range_check_env::build_phase(uvm_phase phase);
+function void ${module_instance_name}_env::build_phase(uvm_phase phase);
   super.build_phase(phase);
 
   // Create Unfiltered TL agent
@@ -38,7 +38,7 @@ function void ac_range_check_env::build_phase(uvm_phase phase);
   cfg.tl_filt_agt_cfg.en_cov = cfg.en_cov;
 endfunction : build_phase
 
-function void ac_range_check_env::connect_phase(uvm_phase phase);
+function void ${module_instance_name}_env::connect_phase(uvm_phase phase);
   super.connect_phase(phase);
   if (cfg.en_scb) begin
     tl_unfilt_agt.monitor.a_chan_port.connect(scoreboard.tl_unfilt_a_chan_fifo.analysis_export);

hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cfg.sv renamed to hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cfg.sv.tpl

@@ -2,13 +2,13 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_reg_block));
+class ${module_instance_name}_env_cfg extends cip_base_env_cfg #(.RAL_T(${module_instance_name}_reg_block));
 
   // External component config objects
   rand tl_agent_cfg tl_unfilt_agt_cfg;
   rand tl_agent_cfg tl_filt_agt_cfg;
 
-  `uvm_object_utils_begin(ac_range_check_env_cfg)
+  `uvm_object_utils_begin(${module_instance_name}_env_cfg)
     `uvm_field_object(tl_unfilt_agt_cfg, UVM_DEFAULT)
     `uvm_field_object(tl_filt_agt_cfg, UVM_DEFAULT)
   `uvm_object_utils_end
@@ -18,15 +18,15 @@ class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_re
 
   // Class specific methods
   extern function void initialize(bit [31:0] csr_base_addr = '1);
-endclass : ac_range_check_env_cfg
+endclass : ${module_instance_name}_env_cfg
 
 
-function ac_range_check_env_cfg::new(string name="");
+function ${module_instance_name}_env_cfg::new(string name="");
   super.new(name);
 endfunction : new
 
-function void ac_range_check_env_cfg::initialize(bit [31:0] csr_base_addr = '1);
-  list_of_alerts = ac_range_check_env_pkg::LIST_OF_ALERTS;
+function void ${module_instance_name}_env_cfg::initialize(bit [31:0] csr_base_addr = '1);
+  list_of_alerts = ${module_instance_name}_env_pkg::LIST_OF_ALERTS;
   super.initialize(csr_base_addr);
 
   // Set shadow register error status

hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cov.sv renamed to hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cov.sv.tpl

@@ -8,27 +8,27 @@
  * Covergroups may also be wrapped inside helper classes if needed.
  */
 
-class ac_range_check_env_cov extends cip_base_env_cov #(.CFG_T(ac_range_check_env_cfg));
-  `uvm_component_utils(ac_range_check_env_cov)
+class ${module_instance_name}_env_cov extends cip_base_env_cov #(.CFG_T(${module_instance_name}_env_cfg));
+  `uvm_component_utils(${module_instance_name}_env_cov)
 
   // The base class provides the following handles for use:
-  // ac_range_check_env_cfg: cfg
+  // ${module_instance_name}_env_cfg: cfg
 
   // Covergroups
   // TODO MVy [add covergroups here]
 
   // Standard SV/UVM methods
   extern function new(string name, uvm_component parent);
   extern function void build_phase(uvm_phase phase);
-endclass : ac_range_check_env_cov
+endclass : ${module_instance_name}_env_cov
 
 
-function ac_range_check_env_cov::new(string name, uvm_component parent);
+function ${module_instance_name}_env_cov::new(string name, uvm_component parent);
   super.new(name, parent);
   // TODO MVy [instantiate covergroups here]
 endfunction : new
 
-function void ac_range_check_env_cov::build_phase(uvm_phase phase);
+function void ${module_instance_name}_env_cov::build_phase(uvm_phase phase);
   super.build_phase(phase);
   // TODO MVy [or instantiate covergroups here]
   // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky

hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_pkg.sv.tpl

@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-package ac_range_check_env_pkg;
+package ${module_instance_name}_env_pkg;
   // Dep packages
   import uvm_pkg::*;
   import top_pkg::*;
@@ -12,7 +12,7 @@ package ac_range_check_env_pkg;
   import cip_base_pkg::*;
   import dv_base_reg_pkg::*;
   import csr_utils_pkg::*;
-  import ac_range_check_ral_pkg::*;
+  import ${module_instance_name}_ral_pkg::*;
 
   // Macro includes
   `include "uvm_macros.svh"
@@ -80,11 +80,11 @@ package ac_range_check_env_pkg;
   endfunction : get_csr_idx
 
   // Package sources
-  `include "ac_range_check_dut_cfg.sv"
-  `include "ac_range_check_env_cfg.sv"
-  `include "ac_range_check_env_cov.sv"
-  `include "ac_range_check_virtual_sequencer.sv"
-  `include "ac_range_check_scoreboard.sv"
-  `include "ac_range_check_env.sv"
-  `include "ac_range_check_vseq_list.sv"
-endpackage : ac_range_check_env_pkg
+  `include "${module_instance_name}_dut_cfg.sv"
+  `include "${module_instance_name}_env_cfg.sv"
+  `include "${module_instance_name}_env_cov.sv"
+  `include "${module_instance_name}_virtual_sequencer.sv"
+  `include "${module_instance_name}_scoreboard.sv"
+  `include "${module_instance_name}_env.sv"
+  `include "${module_instance_name}_vseq_list.sv"
+endpackage : ${module_instance_name}_env_pkg