[hw,soc_proxy,rtl] Implement dummy register to keep reg port

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -12198,7 +12198,7 @@
               {
                 hart: 0x22030000
               }
-              size_byte: 0x10
+              size_byte: 0x20
             }
           ]
           xbar: false

hw/top_darjeeling/doc/memory_map.md

@@ -30,7 +30,7 @@ The main address space, shared between the CPU and DM
 | pinmux_aon        | default     | `0x30460000`   | `0x800`        | `0x200`        | pinmux_aon                       |
 | aon_timer_aon     | default     | `0x30470000`   | `0x40`         | `0x10`         | aon_timer_aon                    |
 | ast               | default     | `0x30480000`   | `0x400`        | `0x100`        | ast                              |
-| soc_proxy         | core        | `0x22030000`   | `0x10`         | `0x4`          | core device on soc_proxy         |
+| soc_proxy         | core        | `0x22030000`   | `0x20`         | `0x8`          | core device on soc_proxy         |
 | sram_ctrl_ret_aon | regs        | `0x30500000`   | `0x40`         | `0x10`         | regs device on sram_ctrl_ret_aon |
 | rv_dm             | regs        | `0x21200000`   | `0x10`         | `0x4`          | regs device on rv_dm             |
 | rv_dm             | mem         | `0x40000`      | `0x1000`       | `0x400`        | mem device on rv_dm              |

hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv

@@ -26,7 +26,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h211e1000, 32'h211e107f}
     }},
     '{"soc_proxy__core", '{
-        '{32'h22030000, 32'h2203000f}
+        '{32'h22030000, 32'h2203001f}
     }},
     '{"soc_proxy__ctn", '{
         '{32'h40000000, 32'hbfffffff}

hw/top_darjeeling/dv/autogen/xbar_tgl_excl.cfg

@@ -43,7 +43,7 @@
 -node tb.dut*.u_rom_ctrl1 regs_tl_*i.a_address[23:21]
 -node tb.dut*.u_rom_ctrl1 regs_tl_*i.a_address[28:25]
 -node tb.dut*.u_rom_ctrl1 regs_tl_*i.a_address[31:30]
--node tb.dut*.u_soc_proxy core_tl_*i.a_address[15:4]
+-node tb.dut*.u_soc_proxy core_tl_*i.a_address[15:5]
 -node tb.dut*.u_soc_proxy core_tl_*i.a_address[24:18]
 -node tb.dut*.u_soc_proxy core_tl_*i.a_address[28:26]
 -node tb.dut*.u_soc_proxy core_tl_*i.a_address[31:30]

hw/top_darjeeling/ip/soc_proxy/data/soc_proxy.hjson

@@ -313,7 +313,23 @@
 
   registers: {
     core: [
-      // no CSRs defined yet
+      {
+        name: "DUMMY"
+        desc: '''
+              Dummy register to keep the device port.
+              Always returns 0.
+              '''
+        swaccess: "ro"
+        hwaccess: "none"
+        fields: [
+          {
+            name: "dummy"
+            desc: "Dummy field"
+            bits: "0"
+            resval: 0
+          }
+        ]
+      }
     ]
   }
 

hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy_core_reg_top.sv

@@ -21,7 +21,7 @@ module soc_proxy_core_reg_top (
 
   import soc_proxy_reg_pkg::* ;
 
-  localparam int AW = 4;
+  localparam int AW = 5;
   localparam int DW = 32;
   localparam int DBW = DW/8;                    // Byte Width
 
@@ -52,9 +52,9 @@ module soc_proxy_core_reg_top (
 
   // also check for spurious write enables
   logic reg_we_err;
-  logic [3:0] reg_we_check;
+  logic [4:0] reg_we_check;
   prim_reg_we_check #(
-    .OneHotWidth(4)
+    .OneHotWidth(5)
   ) u_prim_reg_we_check (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
@@ -159,6 +159,7 @@ module soc_proxy_core_reg_top (
   logic alert_test_recov_alert_external_1_wd;
   logic alert_test_recov_alert_external_2_wd;
   logic alert_test_recov_alert_external_3_wd;
+  logic dummy_qs;
 
   // Register instances
   // R[intr_state]: V(False)
@@ -706,13 +707,19 @@ module soc_proxy_core_reg_top (
   assign reg2hw.alert_test.recov_alert_external_3.qe = alert_test_qe;
 
 
+  // R[dummy]: V(False)
+  // constant-only read
+  assign dummy_qs = 1'h0;
 
-  logic [3:0] addr_hit;
+
+
+  logic [4:0] addr_hit;
   always_comb begin
     addr_hit[0] = (reg_addr == SOC_PROXY_INTR_STATE_OFFSET);
     addr_hit[1] = (reg_addr == SOC_PROXY_INTR_ENABLE_OFFSET);
     addr_hit[2] = (reg_addr == SOC_PROXY_INTR_TEST_OFFSET);
     addr_hit[3] = (reg_addr == SOC_PROXY_ALERT_TEST_OFFSET);
+    addr_hit[4] = (reg_addr == SOC_PROXY_DUMMY_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -723,7 +730,8 @@ module soc_proxy_core_reg_top (
               ((addr_hit[0] & (|(SOC_PROXY_CORE_PERMIT[0] & ~reg_be))) |
                (addr_hit[1] & (|(SOC_PROXY_CORE_PERMIT[1] & ~reg_be))) |
                (addr_hit[2] & (|(SOC_PROXY_CORE_PERMIT[2] & ~reg_be))) |
-               (addr_hit[3] & (|(SOC_PROXY_CORE_PERMIT[3] & ~reg_be)))));
+               (addr_hit[3] & (|(SOC_PROXY_CORE_PERMIT[3] & ~reg_be))) |
+               (addr_hit[4] & (|(SOC_PROXY_CORE_PERMIT[4] & ~reg_be)))));
   end
 
   // Generate write-enables
@@ -802,6 +810,7 @@ module soc_proxy_core_reg_top (
     reg_we_check[1] = intr_enable_we;
     reg_we_check[2] = intr_test_we;
     reg_we_check[3] = alert_test_we;
+    reg_we_check[4] = 1'b0;
   end
 
   // Read data return
@@ -852,6 +861,10 @@ module soc_proxy_core_reg_top (
         reg_rdata_next[28] = '0;
       end
 
+      addr_hit[4]: begin
+        reg_rdata_next[0] = dummy_qs;
+      end
+
       default: begin
         reg_rdata_next = '1;
       end

hw/top_darjeeling/ip/soc_proxy/rtl/soc_proxy_reg_pkg.sv

@@ -11,10 +11,10 @@ package soc_proxy_reg_pkg;
   parameter int NumAlerts = 29;
 
   // Address widths within the block
-  parameter int CoreAw = 4;
+  parameter int CoreAw = 5;
 
   // Number of registers for every interface
-  parameter int NumRegsCore = 4;
+  parameter int NumRegsCore = 5;
 
   // Alert indices
   typedef enum int {
@@ -204,10 +204,11 @@ package soc_proxy_reg_pkg;
   } soc_proxy_core_hw2reg_t;
 
   // Register offsets for core interface
-  parameter logic [CoreAw-1:0] SOC_PROXY_INTR_STATE_OFFSET = 4'h 0;
-  parameter logic [CoreAw-1:0] SOC_PROXY_INTR_ENABLE_OFFSET = 4'h 4;
-  parameter logic [CoreAw-1:0] SOC_PROXY_INTR_TEST_OFFSET = 4'h 8;
-  parameter logic [CoreAw-1:0] SOC_PROXY_ALERT_TEST_OFFSET = 4'h c;
+  parameter logic [CoreAw-1:0] SOC_PROXY_INTR_STATE_OFFSET = 5'h 0;
+  parameter logic [CoreAw-1:0] SOC_PROXY_INTR_ENABLE_OFFSET = 5'h 4;
+  parameter logic [CoreAw-1:0] SOC_PROXY_INTR_TEST_OFFSET = 5'h 8;
+  parameter logic [CoreAw-1:0] SOC_PROXY_ALERT_TEST_OFFSET = 5'h c;
+  parameter logic [CoreAw-1:0] SOC_PROXY_DUMMY_OFFSET = 5'h 10;
 
   // Reset values for hwext registers and their fields for core interface
   parameter logic [31:0] SOC_PROXY_INTR_TEST_RESVAL = 32'h 0;
@@ -248,15 +249,17 @@ package soc_proxy_reg_pkg;
     SOC_PROXY_INTR_STATE,
     SOC_PROXY_INTR_ENABLE,
     SOC_PROXY_INTR_TEST,
-    SOC_PROXY_ALERT_TEST
+    SOC_PROXY_ALERT_TEST,
+    SOC_PROXY_DUMMY
   } soc_proxy_core_id_e;
 
   // Register width information to check illegal writes for core interface
-  parameter logic [3:0] SOC_PROXY_CORE_PERMIT [4] = '{
+  parameter logic [3:0] SOC_PROXY_CORE_PERMIT [5] = '{
     4'b 1111, // index[0] SOC_PROXY_INTR_STATE
     4'b 1111, // index[1] SOC_PROXY_INTR_ENABLE
     4'b 1111, // index[2] SOC_PROXY_INTR_TEST
-    4'b 1111  // index[3] SOC_PROXY_ALERT_TEST
+    4'b 1111, // index[3] SOC_PROXY_ALERT_TEST
+    4'b 0001  // index[4] SOC_PROXY_DUMMY
   };
 
 endpackage

hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson

@@ -386,7 +386,7 @@
           {
             hart: 0x22030000
           }
-          size_byte: 0x10
+          size_byte: 0x20
         }
       ]
       xbar: false

hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_cover.cfg

@@ -41,7 +41,7 @@
 -node tb.dut tl_rom_ctrl1__regs_o.a_address[31:30]
 -node tb.dut tl_peri_o.a_address[27:23]
 -node tb.dut tl_peri_o.a_address[31:30]
--node tb.dut tl_soc_proxy__core_o.a_address[15:4]
+-node tb.dut tl_soc_proxy__core_o.a_address[15:5]
 -node tb.dut tl_soc_proxy__core_o.a_address[24:18]
 -node tb.dut tl_soc_proxy__core_o.a_address[28:26]
 -node tb.dut tl_soc_proxy__core_o.a_address[31:30]

hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv

@@ -29,7 +29,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h30000000, 32'h307fffff}
     }},
     '{"soc_proxy__core", '{
-        '{32'h22030000, 32'h2203000f}
+        '{32'h22030000, 32'h2203001f}
     }},
     '{"soc_proxy__ctn", '{
         '{32'h40000000, 32'hbfffffff}