[clkmgr,dv] Gate more extclk test logic

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

hw/ip_templates/clkmgr/dv/env/clkmgr_env.core.tpl

@@ -24,7 +24,9 @@ filesets:
       - seq_lib/clkmgr_base_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_clk_status_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_common_vseq.sv: {is_include_file: true}
+    % if len(derived_clks) > 0:
       - seq_lib/clkmgr_extclk_vseq.sv: {is_include_file: true}
+    % endif
       - seq_lib/clkmgr_frequency_timeout_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_frequency_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_peri_vseq.sv: {is_include_file: true}

hw/ip_templates/clkmgr/dv/env/clkmgr_if.sv.tpl

@@ -77,7 +77,11 @@ interface clkmgr_if (
     clk_enables_csr = '{
 % for clk in [c for c in reversed(typed_clocks['sw_clks'].values())]:
 <% sep = "" if loop.last else "," %>\
+    % if len(typed_clocks['sw_clks']) == 1:
+      ${clk['src_name']}_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.q${sep}
+    % else:
       ${clk['src_name']}_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.clk_${clk['src_name']}_peri_en.q${sep}
+    % endif
 % endfor
     };
 
@@ -178,6 +182,7 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
     io_clk_byp_ack = value;
   endfunction
 
+% endif
   function automatic void force_high_starting_count(clk_mesr_e clk);
     `uvm_info("clkmgr_if", $sformatf("Forcing count of %0s to all 1.", clk.name()), UVM_MEDIUM)
     case (clk)
@@ -188,7 +193,6 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
     endcase
   endfunction
 
-% endif
   task automatic init(mubi_hintables_t idle, prim_mubi_pkg::mubi4_t scanmode,
     % if len(derived_clks) > 0:
                       lc_ctrl_pkg::lc_tx_t lc_debug_en = lc_ctrl_pkg::Off,

hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv.tpl

@@ -85,7 +85,11 @@ class clkmgr_base_vseq extends cip_base_vseq #(
     `uvm_info(`gfn, "In clkmgr_if initialize_on_start", UVM_MEDIUM)
     idle = {NUM_TRANS{MuBi4True}};
     scanmode = MuBi4False;
+  % if len(derived_clks) > 0:
     cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode), .lc_debug_en(Off));
+  % else:
+    cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode));
+  % endif
 % for clk_name in non_aon_src_names:
     ${clk_name}_ip_clk_en = 1'b1;
 % endfor
@@ -120,7 +124,11 @@ ${spc}ral.${src}_meas_ctrl_shadowed.lo};
     mubi_mode = ClkmgrMubiNone;
     `DV_GET_ENUM_PLUSARG(clkmgr_mubi_e, mubi_mode, clkmgr_mubi_mode)
     `uvm_info(`gfn, $sformatf("mubi_mode = %s", mubi_mode.name), UVM_MEDIUM)
+  % if len(derived_clks) > 0:
     cfg.clkmgr_vif.init(.idle({NUM_TRANS{MuBi4True}}), .scanmode(scanmode), .lc_debug_en(Off));
+  % else:
+    cfg.clkmgr_vif.init(.idle({NUM_TRANS{MuBi4True}}), .scanmode(scanmode));
+  % endif
 % for src in sorted(src_clks.values(), key=lambda v: v['name']):
   % if not src['aon']:
     cfg.clkmgr_vif.update_${src['name']}_ip_clk_en(1'b1);

hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv renamed to hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv.tpl

@@ -24,6 +24,7 @@ class clkmgr_regwen_vseq extends clkmgr_base_vseq;
     `uvm_info(`gfn, "Check jitter_regwen done", UVM_MEDIUM)
   endtask : check_jitter_regwen
 
+% if len(derived_clks) > 0:
   task check_extclk_regwen();
     bit enable;
     int prev_value;
@@ -37,6 +38,7 @@ class clkmgr_regwen_vseq extends clkmgr_base_vseq;
     `uvm_info(`gfn, "Check extclk_ctrl regwen done", UVM_MEDIUM)
   endtask : check_extclk_regwen
 
+% endif
   // This must be careful to turn measurements off right after checking the updates
   // to avoid measurement errors. We could set the thresholds correctly, but we
   // might as well set them randomly for good measure. Carefully masks only the
@@ -86,14 +88,18 @@ class clkmgr_regwen_vseq extends clkmgr_base_vseq;
     `uvm_info(`gfn, $sformatf("Will run %0d rounds", num_trans), UVM_MEDIUM)
     for (int i = 0; i < num_trans; ++i) begin
       check_jitter_regwen();
+    % if len(derived_clks) > 0:
       check_extclk_regwen();
+    % endif
       check_meas_ctrl_regwen();
       apply_reset("HARD");
       // This is to make sure we don't start writes immediately after reset,
       // otherwise the tl_agent could mistakenly consider the following read
       // happens during reset.
       cfg.clk_rst_vif.wait_clks(4);
+    % if len(derived_clks) > 0:
       csr_rd_check(.ptr(ral.extclk_ctrl_regwen), .compare_value(1));
+    % endif
       csr_rd_check(.ptr(ral.measure_ctrl_regwen), .compare_value(1));
     end
   endtask : body

hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv renamed to hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv.tpl

@@ -7,7 +7,9 @@
 `include "clkmgr_common_vseq.sv"
 `include "clkmgr_frequency_timeout_vseq.sv"
 `include "clkmgr_frequency_vseq.sv"
+% if len(derived_clks) > 0:
 `include "clkmgr_extclk_vseq.sv"
+% endif
 `include "clkmgr_peri_vseq.sv"
 `include "clkmgr_regwen_vseq.sv"
 `include "clkmgr_smoke_vseq.sv"

hw/ip_templates/clkmgr/dv/tb.sv.tpl

@@ -83,7 +83,11 @@ module tb;
     .clk_enables({
 % for clk in [c for c in reversed(typed_clocks['sw_clks'].values())]:
 <% sep = "})," if loop.last else "," %>\
+  % if len(typed_clocks['sw_clks']) == 1:
+        reg2hw.clk_enables.q${sep}
+  % else:
         reg2hw.clk_enables.clk_${clk['src_name']}_peri_en.q${sep}
+  % endif
 % endfor
     .clk_hints({
         reg2hw.clk_hints.clk_main_otbn_hint.q,

hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_env.core

@@ -24,7 +24,6 @@ filesets:
       - seq_lib/clkmgr_base_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_clk_status_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_common_vseq.sv: {is_include_file: true}
-      - seq_lib/clkmgr_extclk_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_frequency_timeout_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_frequency_vseq.sv: {is_include_file: true}
       - seq_lib/clkmgr_peri_vseq.sv: {is_include_file: true}

hw/top_darjeeling/ip_autogen/clkmgr/dv/env/clkmgr_if.sv

@@ -48,7 +48,7 @@ interface clkmgr_if (
   clk_enables_t clk_enables_csr;
   always_comb
     clk_enables_csr = '{
-      io_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.clk_io_peri_en.q
+      io_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.q
     };
 
   clk_hints_t clk_hints_csr;
@@ -119,6 +119,15 @@ interface clkmgr_if (
     scanmode_i = value;
   endfunction
 
+  function automatic void force_high_starting_count(clk_mesr_e clk);
+    `uvm_info("clkmgr_if", $sformatf("Forcing count of %0s to all 1.", clk.name()), UVM_MEDIUM)
+    case (clk)
+      ClkMesrIo: `CLKMGR_HIER.u_io_meas.u_meas.cnt = '1;
+      ClkMesrMain: `CLKMGR_HIER.u_main_meas.u_meas.cnt = '1;
+      default: ;
+    endcase
+  endfunction
+
   task automatic init(mubi_hintables_t idle, prim_mubi_pkg::mubi4_t scanmode,
                       prim_mubi_pkg::mubi4_t calib_rdy = prim_mubi_pkg::MuBi4True);
     `uvm_info("clkmgr_if", "In clkmgr_if init", UVM_MEDIUM)

hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv

@@ -73,7 +73,7 @@ class clkmgr_base_vseq extends cip_base_vseq #(
     `uvm_info(`gfn, "In clkmgr_if initialize_on_start", UVM_MEDIUM)
     idle = {NUM_TRANS{MuBi4True}};
     scanmode = MuBi4False;
-    cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode), .lc_debug_en(Off));
+    cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode));
     io_ip_clk_en = 1'b1;
     main_ip_clk_en = 1'b1;
     start_ip_clocks();
@@ -103,7 +103,7 @@ class clkmgr_base_vseq extends cip_base_vseq #(
     mubi_mode = ClkmgrMubiNone;
     `DV_GET_ENUM_PLUSARG(clkmgr_mubi_e, mubi_mode, clkmgr_mubi_mode)
     `uvm_info(`gfn, $sformatf("mubi_mode = %s", mubi_mode.name), UVM_MEDIUM)
-    cfg.clkmgr_vif.init(.idle({NUM_TRANS{MuBi4True}}), .scanmode(scanmode), .lc_debug_en(Off));
+    cfg.clkmgr_vif.init(.idle({NUM_TRANS{MuBi4True}}), .scanmode(scanmode));
     cfg.clkmgr_vif.update_io_ip_clk_en(1'b1);
     cfg.clkmgr_vif.update_main_ip_clk_en(1'b1);
 

hw/top_darjeeling/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv

@@ -24,19 +24,6 @@ class clkmgr_regwen_vseq extends clkmgr_base_vseq;
     `uvm_info(`gfn, "Check jitter_regwen done", UVM_MEDIUM)
   endtask : check_jitter_regwen
 
-  task check_extclk_regwen();
-    bit enable;
-    int prev_value;
-    int new_value = {extclk_ctrl_high_speed_sel, extclk_ctrl_sel};
-    `DV_CHECK_STD_RANDOMIZE_FATAL(enable)
-    `uvm_info(`gfn, $sformatf("Check extclk_ctrl regwen = %b", enable), UVM_MEDIUM)
-    csr_wr(.ptr(ral.extclk_ctrl_regwen), .value(enable));
-    csr_rd(.ptr(ral.extclk_ctrl), .value(prev_value));
-    csr_wr(.ptr(ral.extclk_ctrl), .value(new_value));
-    csr_rd_check(.ptr(ral.extclk_ctrl), .compare_value(enable ? new_value : prev_value));
-    `uvm_info(`gfn, "Check extclk_ctrl regwen done", UVM_MEDIUM)
-  endtask : check_extclk_regwen
-
   // This must be careful to turn measurements off right after checking the updates
   // to avoid measurement errors. We could set the thresholds correctly, but we
   // might as well set them randomly for good measure. Carefully masks only the
@@ -86,14 +73,12 @@ class clkmgr_regwen_vseq extends clkmgr_base_vseq;
     `uvm_info(`gfn, $sformatf("Will run %0d rounds", num_trans), UVM_MEDIUM)
     for (int i = 0; i < num_trans; ++i) begin
       check_jitter_regwen();
-      check_extclk_regwen();
       check_meas_ctrl_regwen();
       apply_reset("HARD");
       // This is to make sure we don't start writes immediately after reset,
       // otherwise the tl_agent could mistakenly consider the following read
       // happens during reset.
       cfg.clk_rst_vif.wait_clks(4);
-      csr_rd_check(.ptr(ral.extclk_ctrl_regwen), .compare_value(1));
       csr_rd_check(.ptr(ral.measure_ctrl_regwen), .compare_value(1));
     end
   endtask : body