[hw,clkmgr,rtl] Gate calibration input together with ext clock bypass

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

hw/ip_templates/clkmgr/data/clkmgr.hjson.tpl

@@ -252,7 +252,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
       package: "prim_mubi_pkg",
       width:   "${len(hint_names)}"
     },
-
+% if ext_clk_bypass:
     { struct:  "mubi4",
       desc:    "Indicates clocks are calibrated and frequencies accurate",
       type:    "uni",
@@ -261,6 +261,7 @@ rg_srcs = get_rg_srcs(typed_clocks)
       package: "prim_mubi_pkg",
       default: "prim_mubi_pkg::MuBi4True"
     },
+% endif
   ],
 
   countermeasures: [

hw/ip_templates/clkmgr/dv/env/clkmgr_if.sv.tpl

@@ -53,16 +53,13 @@ interface clkmgr_if (
   prim_mubi_pkg::mubi4_t all_clk_byp_ack;
 
   prim_mubi_pkg::mubi4_t div_step_down_req;
+  prim_mubi_pkg::mubi4_t calib_rdy;
+  prim_mubi_pkg::mubi4_t hi_speed_sel;
 
 % endif
   prim_mubi_pkg::mubi4_t jitter_en_o;
   clkmgr_pkg::clkmgr_out_t clocks_o;
 
-  prim_mubi_pkg::mubi4_t calib_rdy;
-% if ext_clk_bypass:
-  prim_mubi_pkg::mubi4_t hi_speed_sel;
-% endif
-
   // Internal DUT signals.
   // ICEBOX(lowrisc/opentitan#18379): This is a core env component (i.e. reusable entity) that
   // makes hierarchical references into the DUT. A better strategy would be to bind this interface
@@ -137,9 +134,6 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
   always_comb ${src}_timeout_err = `CLKMGR_HIER.u_${src}_meas.timeout_err_o;
 
 % endfor
-  function automatic void update_calib_rdy(prim_mubi_pkg::mubi4_t value);
-    calib_rdy = value;
-  endfunction
 
   function automatic void update_idle(mubi_hintables_t value);
     idle_i = value;
@@ -158,6 +152,10 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
   endfunction
 
 % if ext_clk_bypass:
+  function automatic void update_calib_rdy(prim_mubi_pkg::mubi4_t value);
+    calib_rdy = value;
+  endfunction
+
   function automatic void update_lc_debug_en(lc_ctrl_pkg::lc_tx_t value);
     lc_hw_debug_en_i = value;
   endfunction
@@ -200,7 +198,9 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
     % endif
                       prim_mubi_pkg::mubi4_t calib_rdy = prim_mubi_pkg::MuBi4True);
     `uvm_info("clkmgr_if", "In clkmgr_if init", UVM_MEDIUM)
+  % if ext_clk_bypass:
     update_calib_rdy(calib_rdy);
+  % endif
     update_idle(idle);
   % if ext_clk_bypass:
     update_lc_clk_byp_req(lc_clk_byp_req);
@@ -280,8 +280,8 @@ ${spc}fast: `CLKMGR_HIER.u_${src}_meas.u_meas.fast_o};
 
 % endif
   clocking clk_cb @(posedge clk);
-    input calib_rdy;
   % if ext_clk_bypass:
+    input calib_rdy;
     input extclk_ctrl_csr_sel;
     input extclk_ctrl_csr_step_down;
     input lc_hw_debug_en_i;

hw/ip_templates/clkmgr/dv/env/seq_lib/clkmgr_frequency_vseq.sv.tpl

@@ -109,6 +109,7 @@ class clkmgr_frequency_vseq extends clkmgr_base_vseq;
     // Wait for the result to propagate to the recov_err_code CSR.
     cfg.clk_rst_vif.wait_clks(CyclesForErrUpdate);
   endtask
+% if ext_clk_bypass:
 
   // If clocks become uncalibrated measure_ctrl_regwen is re-enabled.
   task check_measure_ctrl_regwen_for_calib_rdy();
@@ -118,6 +119,7 @@ class clkmgr_frequency_vseq extends clkmgr_base_vseq;
     cfg.clk_rst_vif.wait_clks(20);
     calibration_lost_checks();
   endtask
+% endif
 
   task body();
     logic [TL_DW-1:0] value;
@@ -159,6 +161,7 @@ class clkmgr_frequency_vseq extends clkmgr_base_vseq;
       logic [ClkMesrSize-1:0] expected_recov_meas_err = '0;
       bit expect_alert = 0;
       `DV_CHECK_RANDOMIZE_FATAL(this)
+% if ext_clk_bypass:
       // Update calib_rdy input: if calibration is not ready the measurements
       // don't happen, so we should not get faults.
       cfg.clkmgr_vif.update_calib_rdy(calib_rdy);
@@ -171,6 +174,7 @@ class clkmgr_frequency_vseq extends clkmgr_base_vseq;
       // Allow calib_rdy to generate side-effects.
       cfg.clk_rst_vif.wait_clks(3);
       if (calib_rdy == MuBi4False) calibration_lost_checks();
+% endif
       prior_alert_count = cfg.scoreboard.get_alert_count("recov_fault");
       if (cause_saturation) begin
         `uvm_info(`gfn, $sformatf(
@@ -254,8 +258,10 @@ class clkmgr_frequency_vseq extends clkmgr_base_vseq;
       csr_wr(.ptr(ral.recov_err_code), .value('1));
       cfg.aon_clk_rst_vif.wait_clks(12);
     end
+% if ext_clk_bypass:
     // And finally, check that unsetting calib_rdy causes measure_ctrl_regwen to be set to 1.
     check_measure_ctrl_regwen_for_calib_rdy();
+% endif
   endtask
 
 endclass

hw/ip_templates/clkmgr/dv/sva/clkmgr_bind.sv.tpl

@@ -133,6 +133,7 @@ module clkmgr_bind;
   );
 
  % endfor
+% if ext_clk_bypass:
   // Calibration assertions.
   bind clkmgr clkmgr_lost_calib_regwen_sva_if clkmgr_lost_calib_regwen_sva_if (
     .clk(clk_i),
@@ -150,7 +151,6 @@ module clkmgr_bind;
   );
 
 % endfor
-% if ext_clk_bypass:
   bind clkmgr clkmgr_sec_cm_checker_assert clkmgr_sec_cm_checker_assert (
     .clk_i,
     .rst_ni,

hw/ip_templates/clkmgr/dv/tb.sv.tpl

@@ -163,9 +163,9 @@ module tb;
     .lc_clk_byp_ack_o(clkmgr_if.lc_clk_byp_ack),
     .div_step_down_req_i(clkmgr_if.div_step_down_req),
     .hi_speed_sel_o(clkmgr_if.hi_speed_sel),
+    .calib_rdy_i(clkmgr_if.calib_rdy),
 
   % endif
-    .calib_rdy_i(clkmgr_if.calib_rdy),
     .cg_en_o(),
 
     .jitter_en_o(clkmgr_if.jitter_en_o),

hw/ip_templates/clkmgr/rtl/clkmgr.sv.tpl

@@ -94,11 +94,11 @@ rg_srcs = get_rg_srcs(typed_clocks)
   // SEC_CM: DIV.INTERSIG.MUBI
   input mubi4_t div_step_down_req_i,
 
-% endif
   // clock calibration has been done.
   // If this is signal is 0, assume clock frequencies to be
   // uncalibrated.
   input prim_mubi_pkg::mubi4_t calib_rdy_i,
+% endif
 
   // jittery enable to ast
   output mubi4_t jitter_en_o,
@@ -390,7 +390,11 @@ rg_srcs = get_rg_srcs(typed_clocks)
   ) u_calib_rdy_sync (
     .clk_i,
     .rst_ni,
+  % if ext_clk_bypass:
     .mubi_i(calib_rdy_i),
+  % else:
+    .mubi_i(MuBi4False),
+  % endif
     .mubi_o({calib_rdy})
   );
 

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -3284,21 +3284,6 @@
           top_signame: clkmgr_aon_idle
           index: -1
         }
-        {
-          name: calib_rdy
-          desc: Indicates clocks are calibrated and frequencies accurate
-          struct: mubi4
-          package: prim_mubi_pkg
-          type: uni
-          act: rcv
-          width: 1
-          default: prim_mubi_pkg::MuBi4True
-          inst_name: clkmgr_aon
-          external: true
-          top_signame: calib_rdy
-          conn_type: false
-          index: -1
-        }
         {
           name: tl
           struct: tl
@@ -11764,7 +11749,6 @@
       spi_device.ram_cfg_spi2sys: spi_device_ram_2p_cfg_spi2sys
       pwrmgr_aon.boot_status: pwrmgr_boot_status
       clkmgr_aon.jitter_en: clk_main_jitter_en
-      clkmgr_aon.calib_rdy: calib_rdy
       dma.sys: dma_sys
       entropy_src.entropy_src_rng_enable: es_rng_enable
       entropy_src.entropy_src_rng_valid: es_rng_valid
@@ -23000,21 +22984,6 @@
         top_signame: clkmgr_aon_idle
         index: -1
       }
-      {
-        name: calib_rdy
-        desc: Indicates clocks are calibrated and frequencies accurate
-        struct: mubi4
-        package: prim_mubi_pkg
-        type: uni
-        act: rcv
-        width: 1
-        default: prim_mubi_pkg::MuBi4True
-        inst_name: clkmgr_aon
-        external: true
-        top_signame: calib_rdy
-        conn_type: false
-        index: -1
-      }
       {
         name: tl
         struct: tl
@@ -29002,18 +28971,6 @@
         index: -1
         netname: clk_main_jitter_en
       }
-      {
-        package: prim_mubi_pkg
-        struct: mubi4
-        signame: calib_rdy_i
-        width: 1
-        type: uni
-        default: prim_mubi_pkg::MuBi4True
-        direction: in
-        conn_type: false
-        index: -1
-        netname: calib_rdy
-      }
       {
         package: dma_pkg
         struct: sys_req

hw/top_darjeeling/data/top_darjeeling.hjson

@@ -1410,7 +1410,6 @@
         'spi_device.ram_cfg_spi2sys'           : 'spi_device_ram_2p_cfg_spi2sys',
         'pwrmgr_aon.boot_status'               : 'pwrmgr_boot_status',
         'clkmgr_aon.jitter_en'                 : 'clk_main_jitter_en',
-        'clkmgr_aon.calib_rdy'                 : 'calib_rdy',
         'dma.sys'                              : 'dma_sys',
         'entropy_src.entropy_src_rng_enable'   : 'es_rng_enable',
         'entropy_src.entropy_src_rng_valid'    : 'es_rng_valid',

hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr.hjson

@@ -155,15 +155,6 @@
       package: "prim_mubi_pkg",
       width:   "4"
     },
-
-    { struct:  "mubi4",
-      desc:    "Indicates clocks are calibrated and frequencies accurate",
-      type:    "uni",
-      name:    "calib_rdy",
-      act:     "rcv",
-      package: "prim_mubi_pkg",
-      default: "prim_mubi_pkg::MuBi4True"
-    },
   ],
 
   countermeasures: [

hw/top_darjeeling/ip_autogen/clkmgr/doc/interfaces.md

@@ -11,15 +11,14 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
 
 ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)
 
-| Port Name   | Package::Struct          | Type    | Act   |   Width | Description                                              |
-|:------------|:-------------------------|:--------|:------|--------:|:---------------------------------------------------------|
-| clocks      | clkmgr_pkg::clkmgr_out   | uni     | req   |       1 |                                                          |
-| cg_en       | clkmgr_pkg::clkmgr_cg_en | uni     | req   |       1 |                                                          |
-| jitter_en   | prim_mubi_pkg::mubi4     | uni     | req   |       1 |                                                          |
-| pwr         | pwr_clk                  | req_rsp | rsp   |       1 |                                                          |
-| idle        | prim_mubi_pkg::mubi4     | uni     | rcv   |       4 |                                                          |
-| calib_rdy   | prim_mubi_pkg::mubi4     | uni     | rcv   |       1 | Indicates clocks are calibrated and frequencies accurate |
-| tl          | tlul_pkg::tl             | req_rsp | rsp   |       1 |                                                          |
+| Port Name   | Package::Struct          | Type    | Act   |   Width | Description   |
+|:------------|:-------------------------|:--------|:------|--------:|:--------------|
+| clocks      | clkmgr_pkg::clkmgr_out   | uni     | req   |       1 |               |
+| cg_en       | clkmgr_pkg::clkmgr_cg_en | uni     | req   |       1 |               |
+| jitter_en   | prim_mubi_pkg::mubi4     | uni     | req   |       1 |               |
+| pwr         | pwr_clk                  | req_rsp | rsp   |       1 |               |
+| idle        | prim_mubi_pkg::mubi4     | uni     | rcv   |       4 |               |
+| tl          | tlul_pkg::tl             | req_rsp | rsp   |       1 |               |
 
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