diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index b7a4233964b6b..1f2cdbb177072 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -353,12 +353,13 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     fpga = fpga_params(timeout = "moderate"),
     verilator = verilator_params(timeout = "long"),
     deps = [
         "//hw/top:alert_handler_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/base:math",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/dif:alert_handler",
@@ -695,10 +696,11 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     verilator = verilator_params(timeout = "long"),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/base:math",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/dif:alert_handler",
@@ -1123,10 +1125,11 @@ opentitan_test(
         {
             "//hw/top_earlgrey:silicon_creator": None,
         },
+        DARJEELING_TEST_ENVS,
     ),
     verilator = verilator_params(timeout = "long"),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/runtime:hart",
         "//sw/device/lib/runtime:log",
@@ -1144,9 +1147,10 @@ opentitan_test(
         {
             "//hw/top_earlgrey:silicon_creator": None,
         },
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:stdasm",
@@ -1173,6 +1177,7 @@ opentitan_test(
             "//hw/top_earlgrey:silicon_creator": None,
             "//hw/top_earlgrey:silicon_owner_sival_rom_ext": "silicon_owner",
         },
+        DARJEELING_TEST_ENVS,
     ),
     silicon_owner = silicon_params(
         tags = ["broken"],
@@ -1185,7 +1190,7 @@ opentitan_test(
     ),
     deps = [
         ":otbn_randomness_impl",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/base:memory",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/dif:aes",
@@ -1262,6 +1267,7 @@ opentitan_test(
         {
             "//hw/top_earlgrey:silicon_creator": None,
         },
+        DARJEELING_TEST_ENVS,
     ),
     verilator = verilator_params(
         timeout = "eternal",
@@ -1271,8 +1277,8 @@ opentitan_test(
     ),
     deps = [
         "//hw/ip/aes:model",
+        "//hw/top:dt",
         "//hw/top:edn_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/crypto/drivers:otbn",
         "//sw/device/lib/dif:aes",
@@ -1302,13 +1308,14 @@ opentitan_test(
         {
             "//hw/top_earlgrey:silicon_creator": None,
         },
+        DARJEELING_TEST_ENVS,
     ),
     verilator = verilator_params(
         timeout = "eternal",
     ),
     deps = [
+        "//hw/top:dt",
         "//hw/top:edn_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/dif:csrng",
         "//sw/device/lib/dif:edn",
@@ -1342,14 +1349,15 @@ opentitan_test(
         {
             "//hw/top_earlgrey:silicon_creator": None,
         },
+        DARJEELING_TEST_ENVS,
     ),
     verilator = verilator_params(
         timeout = "long",
     ),
     deps = [
         "//hw/ip/aes:model",
+        "//hw/top:dt",
         "//hw/top:edn_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/dif:aes",
         "//sw/device/lib/dif:csrng",
@@ -1374,13 +1382,14 @@ opentitan_test(
         {
             "//hw/top_earlgrey:silicon_creator": None,
         },
+        DARJEELING_TEST_ENVS,
     ),
     verilator = verilator_params(
         timeout = "long",
     ),
     deps = [
+        "//hw/top:dt",
         "//hw/top:edn_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/base:mmio",
         "//sw/device/lib/dif:csrng",
         "//sw/device/lib/dif:csrng_shared",
@@ -3240,9 +3249,10 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/base:csr",
         "//sw/device/lib/runtime:hart",
         "//sw/device/lib/runtime:irq",
@@ -3257,9 +3267,10 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/base:csr",
         "//sw/device/lib/runtime:hart",
         "//sw/device/lib/runtime:irq",
@@ -6508,7 +6519,7 @@ test_suite(
             test_harness = "//sw/host/tests/chip/rv_dm:access_after_hw_reset",
         ),
         deps = [
-            "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+            "//hw/top:dt",
             "//sw/device/lib/dif:rstmgr",
             "//sw/device/lib/runtime:hart",
             "//sw/device/lib/runtime:log",
@@ -6978,9 +6989,10 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:mmio",
@@ -6997,9 +7009,10 @@ opentitan_test(
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:mmio",
@@ -7147,14 +7160,17 @@ opentitan_binary(
         "rv_core_ibex_epmp_test.S",
         "rv_core_ibex_epmp_test.c",
     ],
-    exec_env = {
-        "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
-        "//hw/top_earlgrey:fpga_cw340_rom_with_fake_keys": None,
-    },
+    exec_env = dicts.add(
+        {
+            "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
+            "//hw/top_earlgrey:fpga_cw340_rom_with_fake_keys": None,
+        },
+        DARJEELING_TEST_ENVS,
+    ),
     kind = "ram",
     linker_script = "//sw/device/silicon_creator/manuf/lib:sram_program_linker_script",
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/runtime:log",
@@ -7280,12 +7296,14 @@ opentitan_binary(
     kind = "ram",
     linker_script = "//sw/device/silicon_creator/manuf/lib:sram_program_linker_script",
     deps = [
+        "//hw/top:dt",
         "//hw/top:pwm_c_regs",
         "//hw/top:rv_timer_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/dif:flash_ctrl",
+        "//sw/device/lib/dif:pwm",
+        "//sw/device/lib/dif:rv_timer",
         "//sw/device/lib/runtime:log",
         "//sw/device/lib/runtime:pmp",
         "//sw/device/lib/testing:flash_ctrl_testutils",
@@ -7308,14 +7326,17 @@ opentitan_test(
             ["//hw/top_earlgrey:sim_verilator"],
         ),
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
+        DARJEELING_TEST_ENVS,
     ),
     deps = [
+        "//hw/top:dt",
         "//hw/top:pwm_c_regs",
         "//hw/top:rv_timer_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/dif:flash_ctrl",
+        "//sw/device/lib/dif:pwm",
+        "//sw/device/lib/dif:rv_timer",
         "//sw/device/lib/runtime:log",
         "//sw/device/lib/runtime:pmp",
         "//sw/device/lib/testing:flash_ctrl_testutils",
@@ -7590,7 +7611,7 @@ opentitan_test(
         test_harness = "//sw/host/tests/chip/sram_ctrl:sram_ctrl_lc_escalation",
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/arch:device",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:mmio",
diff --git a/sw/device/tests/alert_handler_ping_timeout_test.c b/sw/device/tests/alert_handler_ping_timeout_test.c
index 8548c0045b967..311f73d8e5a0b 100644
--- a/sw/device/tests/alert_handler_ping_timeout_test.c
+++ b/sw/device/tests/alert_handler_ping_timeout_test.c
@@ -7,6 +7,9 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#include "hw/top/dt/dt_alert_handler.h"
+#include "hw/top/dt/dt_rv_plic.h"
+#include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/math.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_alert_handler.h"
@@ -14,52 +17,57 @@
 #include "sw/device/lib/runtime/irq.h"
 #include "sw/device/lib/runtime/log.h"
 #include "sw/device/lib/testing/alert_handler_testutils.h"
-#include "sw/device/lib/testing/rv_plic_testutils.h"
 #include "sw/device/lib/testing/test_framework/FreeRTOSConfig.h"
 #include "sw/device/lib/testing/test_framework/check.h"
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 
 #include "hw/top/alert_handler_regs.h"  // Generated.
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-#include "sw/device/lib/testing/autogen/isr_testutils.h"
 
 OTTF_DEFINE_TEST_CONFIG();
 
 static dif_rv_plic_t plic;
 static dif_alert_handler_t alert_handler;
-static const uint32_t kPlicTarget = kTopEarlgreyPlicTargetIbex0;
 
-static plic_isr_ctx_t plic_ctx = {
-    .rv_plic = &plic,
-    .hart_id = kPlicTarget,
+enum {
+  /**
+   * PLIC target for the Ibex core.
+   */
+  kDtRvPlicTargetIbex0 = 0,
 };
 
 // Depends on the clock domain, sometimes alert handler will trigger a spurious
 // alert after the alert timeout. (Issue #2321)
 // So we allow class A interrupt to fire after the real timeout interrupt is
 // triggered.
-static alert_handler_isr_ctx_t alert_handler_ctx = {
-    .alert_handler = &alert_handler,
-    .plic_alert_handler_start_irq_id = kTopEarlgreyPlicIrqIdAlertHandlerClassa,
-    .expected_irq = kDifAlertHandlerIrqClassb,
-    .is_only_irq = false,
-};
+static volatile bool irq_fired = false;
 
 /**
  * Initialize the peripherals used in this test.
  */
 static void init_peripherals(void) {
-  mmio_region_t base_addr =
-      mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR);
-  CHECK_DIF_OK(dif_rv_plic_init(base_addr, &plic));
-
-  base_addr = mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR);
-  CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler));
+  CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic));
+  CHECK_DIF_OK(dif_alert_handler_init_from_dt(kDtAlertHandler, &alert_handler));
 
   // Enable all the alert_handler interrupts used in this test.
-  rv_plic_testutils_irq_range_enable(&plic, kPlicTarget,
-                                     kTopEarlgreyPlicIrqIdAlertHandlerClassa,
-                                     kTopEarlgreyPlicIrqIdAlertHandlerClassd);
+  dt_plic_irq_id_t classa_irq = dt_alert_handler_irq_to_plic_id(
+      kDtAlertHandler, kDtAlertHandlerIrqClassa);
+  dt_plic_irq_id_t classb_irq = dt_alert_handler_irq_to_plic_id(
+      kDtAlertHandler, kDtAlertHandlerIrqClassb);
+  dt_plic_irq_id_t classc_irq = dt_alert_handler_irq_to_plic_id(
+      kDtAlertHandler, kDtAlertHandlerIrqClassc);
+  dt_plic_irq_id_t classd_irq = dt_alert_handler_irq_to_plic_id(
+      kDtAlertHandler, kDtAlertHandlerIrqClassd);
+
+  dt_plic_irq_id_t irq_ids[] = {classa_irq, classb_irq, classc_irq, classd_irq};
+  for (size_t i = 0; i < ARRAYSIZE(irq_ids); ++i) {
+    CHECK_DIF_OK(
+        dif_rv_plic_irq_set_priority(&plic, irq_ids[i], /*priority=*/1u));
+    CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+        &plic, irq_ids[i], kDtRvPlicTargetIbex0, kDifToggleEnabled));
+  }
+
+  CHECK_DIF_OK(dif_rv_plic_target_set_threshold(&plic, kDtRvPlicTargetIbex0,
+                                                /*threshold=*/0u));
 }
 
 /**
@@ -129,37 +137,48 @@ static void alert_handler_config(void) {
  * line to the CPU, which results in a call to this OTTF ISR. This ISR
  * overrides the default OTTF implementation.
  */
-void ottf_external_isr(uint32_t *exc_info) {
-  top_earlgrey_plic_peripheral_t peripheral_serviced;
-  dif_alert_handler_irq_t irq_serviced;
-  isr_testutils_alert_handler_isr(plic_ctx, alert_handler_ctx,
-                                  &peripheral_serviced, &irq_serviced);
-  CHECK(peripheral_serviced == kTopEarlgreyPlicPeripheralAlertHandler,
-        "Interrupt from unexpected peripheral: %d", peripheral_serviced);
-
-  // Only interrupts from class B alerts are expected for this test. Report the
-  // unexpected class.
-  CHECK(irq_serviced == kDifAlertHandlerIrqClassb,
-        "Interrupt from unexpected class: Class %c", 'A' + irq_serviced);
-  // Disable the interrupt after seeing a single ping timeout.
-  CHECK_DIF_OK(dif_alert_handler_irq_set_enabled(
-      &alert_handler, kDifAlertHandlerIrqClassb, kDifToggleDisabled));
+bool ottf_handle_irq(uint32_t *exc_info, dt_instance_id_t inst_id,
+                     dif_rv_plic_irq_id_t plic_irq_id) {
+  // Check if this is the alert handler peripheral
+  if (inst_id != dt_alert_handler_instance_id(kDtAlertHandler)) {
+    return false;
+  }
+
+  // Convert PLIC IRQ ID to alert handler IRQ
+  dt_alert_handler_irq_t irq =
+      dt_alert_handler_irq_from_plic_id(kDtAlertHandler, plic_irq_id);
+
+  // Acknowledge the interrupt
+  CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(&alert_handler, irq));
+
+  // We expect Class B interrupt primarily, but may see Class A due to timing
+  // (Issue #2321 - spurious alerts after timeout)
+  if (irq == kDtAlertHandlerIrqClassb) {
+    irq_fired = true;
+    // Disable the interrupt after seeing the ping timeout
+    CHECK_DIF_OK(dif_alert_handler_irq_set_enabled(
+        &alert_handler, kDifAlertHandlerIrqClassb, kDifToggleDisabled));
+  } else if (irq == kDtAlertHandlerIrqClassa) {
+    // Allow Class A as per Issue #2321
+    LOG_INFO("Received spurious Class A interrupt (expected per Issue #2321)");
+  } else {
+    CHECK(false, "Interrupt from unexpected class: %d", irq);
+  }
+
+  return true;
 }
 
 bool test_main(void) {
   init_peripherals();
 
-  // Stop Ibex from servicing interrupts just before WFI, which would lead to a
-  // long sleep if the test changes to only handle a single ping timeout.
-  irq_global_ctrl(false);
+  // Enable interrupts globally
+  irq_global_ctrl(true);
   irq_external_ctrl(true);
 
   alert_handler_config();
 
-  wait_for_interrupt();
-
-  // Enable the external IRQ at Ibex to jump to servicing it.
-  irq_global_ctrl(true);
+  // Wait for the ping timeout interrupt to fire
+  ATOMIC_WAIT_FOR_INTERRUPT(irq_fired);
 
   // Check local alert cause.
   bool is_cause;
diff --git a/sw/device/tests/aon_timer_wdog_lc_escalate_test.c b/sw/device/tests/aon_timer_wdog_lc_escalate_test.c
index 65b9b5e87bc1a..a374f2cbfa9c8 100644
--- a/sw/device/tests/aon_timer_wdog_lc_escalate_test.c
+++ b/sw/device/tests/aon_timer_wdog_lc_escalate_test.c
@@ -7,6 +7,12 @@
 #include <stdbool.h>
 #include <stdint.h>
 
+#include "hw/top/dt/dt_alert_handler.h"
+#include "hw/top/dt/dt_aon_timer.h"
+#include "hw/top/dt/dt_pwrmgr.h"
+#include "hw/top/dt/dt_rstmgr.h"
+#include "hw/top/dt/dt_rv_plic.h"
+#include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/math.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_alert_handler.h"
@@ -20,13 +26,10 @@
 #include "sw/device/lib/testing/alert_handler_testutils.h"
 #include "sw/device/lib/testing/aon_timer_testutils.h"
 #include "sw/device/lib/testing/rstmgr_testutils.h"
-#include "sw/device/lib/testing/rv_plic_testutils.h"
 #include "sw/device/lib/testing/test_framework/FreeRTOSConfig.h"
 #include "sw/device/lib/testing/test_framework/check.h"
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-
 OTTF_DEFINE_TEST_CONFIG();
 
 /**
@@ -56,7 +59,13 @@ static_assert(
 /**
  * Objects to access the peripherals used in this test via dif API.
  */
-static const uint32_t kPlicTarget = kTopEarlgreyPlicTargetIbex0;
+enum {
+  /**
+   * PLIC target for the Ibex core.
+   */
+  kDtRvPlicTargetIbex0 = 0,
+};
+
 static dif_aon_timer_t aon_timer;
 static dif_rv_plic_t plic;
 static dif_pwrmgr_t pwrmgr;
@@ -70,33 +79,32 @@ static dif_alert_handler_t alert_handler;
  * line to the CPU, which results in a call to this OTTF ISR. This ISR
  * overrides the default OTTF implementation.
  */
-void ottf_external_isr(uint32_t *exc_info) {
-  dif_rv_plic_irq_id_t irq_id;
-  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic, kPlicTarget, &irq_id));
-
-  top_earlgrey_plic_peripheral_t peripheral = (top_earlgrey_plic_peripheral_t)
-      top_earlgrey_plic_interrupt_for_peripheral[irq_id];
-
-  if (peripheral == kTopEarlgreyPlicPeripheralAonTimerAon) {
-    uint32_t irq =
-        (irq_id - (dif_rv_plic_irq_id_t)
-                      kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired);
-
+bool ottf_handle_irq(uint32_t *exc_info, dt_instance_id_t inst_id,
+                     dif_rv_plic_irq_id_t plic_irq_id) {
+  // Check if this is the AON timer peripheral
+  if (inst_id == dt_aon_timer_instance_id(kDtAonTimerAon)) {
     // We should not get aon timer interrupts since escalation suppresses them.
+    dt_aon_timer_irq_t irq =
+        dt_aon_timer_irq_from_plic_id(kDtAonTimerAon, plic_irq_id);
     LOG_ERROR("Unexpected aon timer interrupt %d", irq);
-  } else if (peripheral == kTopEarlgreyPlicPeripheralAlertHandler) {
+    return true;
+  }
+
+  // Check if this is the alert handler peripheral
+  if (inst_id == dt_alert_handler_instance_id(kDtAlertHandler)) {
+    // Convert PLIC IRQ ID to alert handler IRQ
+    dt_alert_handler_irq_t irq =
+        dt_alert_handler_irq_from_plic_id(kDtAlertHandler, plic_irq_id);
+
     // Check the class.
     dif_alert_handler_class_state_t state;
     CHECK_DIF_OK(dif_alert_handler_get_class_state(
         &alert_handler, kDifAlertHandlerClassA, &state));
     CHECK(state == kDifAlertHandlerClassStatePhase0, "Wrong phase %d", state);
 
-    uint32_t irq =
-        (irq_id -
-         (dif_rv_plic_irq_id_t)kTopEarlgreyPlicIrqIdAlertHandlerClassa);
-
     // Deals with the alert cause: we expect it to be from the pwrmgr.
-    dif_alert_handler_alert_t alert = kTopEarlgreyAlertIdPwrmgrAonFatalFault;
+    dif_alert_handler_alert_t alert =
+        dt_pwrmgr_alert_to_alert_id(kDtPwrmgrAon, kDtPwrmgrAlertFatalFault);
     bool is_cause = false;
     CHECK_DIF_OK(
         dif_alert_handler_alert_is_cause(&alert_handler, alert, &is_cause));
@@ -109,36 +117,38 @@ void ottf_external_isr(uint32_t *exc_info) {
     CHECK(!is_cause);
 
     CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(&alert_handler, irq));
+    return true;
   }
 
-  // Complete the IRQ by writing the IRQ source to the Ibex specific CC
-  // register.
-  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kPlicTarget, irq_id));
+  return false;
 }
 
 /**
  * Initialize the peripherals used in this test.
  */
 void init_peripherals(void) {
-  mmio_region_t base_addr =
-      mmio_region_from_addr(TOP_EARLGREY_PWRMGR_AON_BASE_ADDR);
-  CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr));
-
-  base_addr = mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR);
-  CHECK_DIF_OK(dif_rstmgr_init(base_addr, &rstmgr));
-
-  base_addr = mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR);
-  CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer));
-
-  base_addr = mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR);
-  CHECK_DIF_OK(dif_rv_plic_init(base_addr, &plic));
-
-  rv_plic_testutils_irq_range_enable(
-      &plic, kPlicTarget, kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired,
-      kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark);
+  CHECK_DIF_OK(dif_pwrmgr_init_from_dt(kDtPwrmgrAon, &pwrmgr));
+  CHECK_DIF_OK(dif_rstmgr_init_from_dt(kDtRstmgrAon, &rstmgr));
+  CHECK_DIF_OK(dif_aon_timer_init_from_dt(kDtAonTimerAon, &aon_timer));
+  CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic));
+  CHECK_DIF_OK(dif_alert_handler_init_from_dt(kDtAlertHandler, &alert_handler));
+
+  // Enable AON timer interrupts in PLIC
+  dt_plic_irq_id_t wkup_irq = dt_aon_timer_irq_to_plic_id(
+      kDtAonTimerAon, kDtAonTimerIrqWkupTimerExpired);
+  dt_plic_irq_id_t bark_irq =
+      dt_aon_timer_irq_to_plic_id(kDtAonTimerAon, kDtAonTimerIrqWdogTimerBark);
+
+  dt_plic_irq_id_t aon_irq_ids[] = {wkup_irq, bark_irq};
+  for (size_t i = 0; i < ARRAYSIZE(aon_irq_ids); ++i) {
+    CHECK_DIF_OK(dif_rv_plic_irq_set_priority(&plic, aon_irq_ids[i],
+                                              /*priority=*/1u));
+    CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+        &plic, aon_irq_ids[i], kDtRvPlicTargetIbex0, kDifToggleEnabled));
+  }
 
-  base_addr = mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR);
-  CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler));
+  CHECK_DIF_OK(dif_rv_plic_target_set_threshold(&plic, kDtRvPlicTargetIbex0,
+                                                /*threshold=*/0u));
 }
 
 static uint32_t udiv64_slow_into_u32(uint64_t a, uint64_t b,
@@ -154,7 +164,8 @@ static uint32_t udiv64_slow_into_u32(uint64_t a, uint64_t b,
  * wdog is programed to bark.
  */
 static void alert_handler_config(void) {
-  dif_alert_handler_alert_t alerts[] = {kTopEarlgreyAlertIdPwrmgrAonFatalFault};
+  dif_alert_handler_alert_t alerts[] = {
+      dt_pwrmgr_alert_to_alert_id(kDtPwrmgrAon, kDtPwrmgrAlertFatalFault)};
   dif_alert_handler_class_t alert_classes[] = {kDifAlertHandlerClassA};
 
   dif_alert_handler_escalation_phase_t esc_phases[] = {
@@ -236,10 +247,24 @@ bool test_main(void) {
 
   init_peripherals();
 
-  // Enable all the AON interrupts used in this test.
-  rv_plic_testutils_irq_range_enable(&plic, kPlicTarget,
-                                     kTopEarlgreyPlicIrqIdAlertHandlerClassa,
-                                     kTopEarlgreyPlicIrqIdAlertHandlerClassd);
+  // Enable all the alert handler interrupts used in this test.
+  dt_plic_irq_id_t classa_irq = dt_alert_handler_irq_to_plic_id(
+      kDtAlertHandler, kDtAlertHandlerIrqClassa);
+  dt_plic_irq_id_t classb_irq = dt_alert_handler_irq_to_plic_id(
+      kDtAlertHandler, kDtAlertHandlerIrqClassb);
+  dt_plic_irq_id_t classc_irq = dt_alert_handler_irq_to_plic_id(
+      kDtAlertHandler, kDtAlertHandlerIrqClassc);
+  dt_plic_irq_id_t classd_irq = dt_alert_handler_irq_to_plic_id(
+      kDtAlertHandler, kDtAlertHandlerIrqClassd);
+
+  dt_plic_irq_id_t alert_irq_ids[] = {classa_irq, classb_irq, classc_irq,
+                                      classd_irq};
+  for (size_t i = 0; i < ARRAYSIZE(alert_irq_ids); ++i) {
+    CHECK_DIF_OK(dif_rv_plic_irq_set_priority(&plic, alert_irq_ids[i],
+                                              /*priority=*/1u));
+    CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+        &plic, alert_irq_ids[i], kDtRvPlicTargetIbex0, kDifToggleEnabled));
+  }
 
   alert_handler_config();
 
diff --git a/sw/device/tests/crt_test.c b/sw/device/tests/crt_test.c
index 670495c02e662..fdbc7f6a50543 100644
--- a/sw/device/tests/crt_test.c
+++ b/sw/device/tests/crt_test.c
@@ -19,8 +19,6 @@
 #include "sw/device/lib/testing/test_framework/status.h"
 #include "sw/device/silicon_creator/lib/manifest_def.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-
 OTTF_DEFINE_TEST_CONFIG();
 
 // Symbols defined in `sw/device/lib/testing/test_framework/ottf.ld`,
diff --git a/sw/device/tests/csrng_edn_concurrency_test.c b/sw/device/tests/csrng_edn_concurrency_test.c
index 48648139f56c7..26dd3fad64633 100644
--- a/sw/device/tests/csrng_edn_concurrency_test.c
+++ b/sw/device/tests/csrng_edn_concurrency_test.c
@@ -2,6 +2,13 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "hw/top/dt/dt_aes.h"
+#include "hw/top/dt/dt_csrng.h"
+#include "hw/top/dt/dt_edn.h"
+#include "hw/top/dt/dt_entropy_src.h"
+#include "hw/top/dt/dt_otbn.h"
+#include "hw/top/dt/dt_rv_core_ibex.h"
+#include "hw/top/dt/dt_rv_plic.h"
 #include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_aes.h"
@@ -9,6 +16,7 @@
 #include "sw/device/lib/dif/dif_csrng_shared.h"
 #include "sw/device/lib/dif/dif_edn.h"
 #include "sw/device/lib/dif/dif_entropy_src.h"
+#include "sw/device/lib/dif/dif_rv_plic.h"
 #include "sw/device/lib/runtime/irq.h"
 #include "sw/device/lib/runtime/log.h"
 #include "sw/device/lib/testing/csrng_testutils.h"
@@ -16,15 +24,11 @@
 #include "sw/device/lib/testing/entropy_testutils.h"
 #include "sw/device/lib/testing/otbn_testutils.h"
 #include "sw/device/lib/testing/rand_testutils.h"
-#include "sw/device/lib/testing/rv_plic_testutils.h"
 #include "sw/device/lib/testing/test_framework/check.h"
 #include "sw/device/lib/testing/test_framework/ottf_macros.h"
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 #include "sw/device/tests/otbn_randomness_impl.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-#include "sw/device/lib/testing/autogen/isr_testutils.h"
-
 static dif_csrng_t csrng;
 static dif_edn_t edn0;
 static dif_edn_t edn1;
@@ -140,23 +144,14 @@ OTTF_DEFINE_TEST_CONFIG(.enable_concurrency = true);
  * Initializes the peripherals used in this test.
  */
 static void init_peripherals(void) {
-  CHECK_DIF_OK(dif_csrng_init(
-      mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR), &csrng));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR), &edn0));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR), &edn1));
-  CHECK_DIF_OK(dif_entropy_src_init(
-      mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR), &entropy_src));
-  CHECK_DIF_OK(dif_rv_plic_init(
-      mmio_region_from_addr(TOP_EARLGREY_RV_PLIC_BASE_ADDR), &plic));
-  CHECK_DIF_OK(dif_rv_core_ibex_init(
-      mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR),
-      &rv_core_ibex));
-  CHECK_DIF_OK(
-      dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn));
-  CHECK_DIF_OK(
-      dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes));
+  CHECK_DIF_OK(dif_csrng_init_from_dt(kDtCsrng, &csrng));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn0, &edn0));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1));
+  CHECK_DIF_OK(dif_entropy_src_init_from_dt(kDtEntropySrc, &entropy_src));
+  CHECK_DIF_OK(dif_rv_plic_init_from_dt(kDtRvPlic, &plic));
+  CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &rv_core_ibex));
+  CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn));
+  CHECK_DIF_OK(dif_aes_init_from_dt(kDtAes, &aes));
 }
 
 /**
diff --git a/sw/device/tests/edn_auto_mode.c b/sw/device/tests/edn_auto_mode.c
index ea20e8ea6c9e1..c7f8f47108635 100644
--- a/sw/device/tests/edn_auto_mode.c
+++ b/sw/device/tests/edn_auto_mode.c
@@ -3,6 +3,11 @@
 // SPDX-License-Identifier: Apache-2.0
 
 #include "hw/ip/aes/model/aes_modes.h"
+#include "hw/top/dt/dt_aes.h"
+#include "hw/top/dt/dt_csrng.h"
+#include "hw/top/dt/dt_edn.h"
+#include "hw/top/dt/dt_otbn.h"
+#include "hw/top/dt/dt_rv_core_ibex.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_aes.h"
 #include "sw/device/lib/dif/dif_csrng.h"
@@ -21,7 +26,6 @@
 #include "sw/device/tests/otbn_randomness_impl.h"
 
 #include "hw/top/edn_regs.h"  // Generated
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 enum {
   kTimeout = (10 * 1000 * 1000),
@@ -53,19 +57,12 @@ OTTF_DEFINE_TEST_CONFIG();
 
 // Initializes the peripherals used in this test.
 static void init_peripherals(void) {
-  CHECK_DIF_OK(dif_csrng_init(
-      mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR), &csrng));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR), &edn0));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR), &edn1));
-  CHECK_DIF_OK(
-      dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes));
-  CHECK_DIF_OK(
-      dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn));
-  CHECK_DIF_OK(dif_rv_core_ibex_init(
-      mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR),
-      &rv_core_ibex));
+  CHECK_DIF_OK(dif_csrng_init_from_dt(kDtCsrng, &csrng));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn0, &edn0));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1));
+  CHECK_DIF_OK(dif_aes_init_from_dt(kDtAes, &aes));
+  CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn));
+  CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &rv_core_ibex));
 }
 
 static void configure_otbn(void) {
diff --git a/sw/device/tests/edn_boot_mode.c b/sw/device/tests/edn_boot_mode.c
index 05858048ff965..135afd41bf5b3 100644
--- a/sw/device/tests/edn_boot_mode.c
+++ b/sw/device/tests/edn_boot_mode.c
@@ -2,6 +2,11 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "hw/top/dt/dt_csrng.h"
+#include "hw/top/dt/dt_edn.h"
+#include "hw/top/dt/dt_entropy_src.h"
+#include "hw/top/dt/dt_otbn.h"
+#include "hw/top/dt/dt_rv_core_ibex.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_csrng.h"
 #include "sw/device/lib/dif/dif_edn.h"
@@ -19,7 +24,6 @@
 #include "sw/device/tests/otbn_randomness_impl.h"
 
 #include "hw/top/edn_regs.h"  // Generated
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 enum {
   kEdnBootModeTimeout = (10 * 1000 * 1000),
@@ -48,19 +52,12 @@ OTTF_DEFINE_TEST_CONFIG();
 
 // Initializes the peripherals used in this test.
 static void init_peripherals(void) {
-  CHECK_DIF_OK(dif_entropy_src_init(
-      mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR), &entropy_src));
-  CHECK_DIF_OK(dif_csrng_init(
-      mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR), &csrng));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR), &edn0));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR), &edn1));
-  CHECK_DIF_OK(
-      dif_otbn_init(mmio_region_from_addr(TOP_EARLGREY_OTBN_BASE_ADDR), &otbn));
-  CHECK_DIF_OK(dif_rv_core_ibex_init(
-      mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR),
-      &rv_core_ibex));
+  CHECK_DIF_OK(dif_entropy_src_init_from_dt(kDtEntropySrc, &entropy_src));
+  CHECK_DIF_OK(dif_csrng_init_from_dt(kDtCsrng, &csrng));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn0, &edn0));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1));
+  CHECK_DIF_OK(dif_otbn_init_from_dt(kDtOtbn, &otbn));
+  CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &rv_core_ibex));
 }
 
 static void configure_otbn(void) {
diff --git a/sw/device/tests/edn_kat.c b/sw/device/tests/edn_kat.c
index 178f0e34b7ad8..4bcae37efcbfb 100644
--- a/sw/device/tests/edn_kat.c
+++ b/sw/device/tests/edn_kat.c
@@ -2,6 +2,9 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "hw/top/dt/dt_csrng.h"
+#include "hw/top/dt/dt_edn.h"
+#include "hw/top/dt/dt_rv_core_ibex.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_csrng.h"
 #include "sw/device/lib/dif/dif_csrng_shared.h"
@@ -16,7 +19,6 @@
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 
 #include "hw/top/edn_regs.h"  // Generated
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 enum {
   kEdnKatTimeout = (10 * 1000 * 1000),
@@ -116,15 +118,10 @@ OTTF_DEFINE_TEST_CONFIG();
 
 // Initializes the peripherals used in this test.
 static void init_peripherals(void) {
-  CHECK_DIF_OK(dif_csrng_init(
-      mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR), &csrng));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR), &edn0));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR), &edn1));
-  CHECK_DIF_OK(dif_rv_core_ibex_init(
-      mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR),
-      &rv_core_ibex));
+  CHECK_DIF_OK(dif_csrng_init_from_dt(kDtCsrng, &csrng));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn0, &edn0));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1));
+  CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(kDtRvCoreIbex, &rv_core_ibex));
 }
 
 dif_edn_auto_params_t kat_auto_params_build(bool alert_test) {
diff --git a/sw/device/tests/edn_sw_mode.c b/sw/device/tests/edn_sw_mode.c
index 56ed3caf8657a..5744423a46f09 100644
--- a/sw/device/tests/edn_sw_mode.c
+++ b/sw/device/tests/edn_sw_mode.c
@@ -3,6 +3,9 @@
 // SPDX-License-Identifier: Apache-2.0
 
 #include "hw/ip/aes/model/aes_modes.h"
+#include "hw/top/dt/dt_aes.h"
+#include "hw/top/dt/dt_csrng.h"
+#include "hw/top/dt/dt_edn.h"
 #include "sw/device/lib/base/mmio.h"
 #include "sw/device/lib/dif/dif_aes.h"
 #include "sw/device/lib/dif/dif_csrng.h"
@@ -16,7 +19,6 @@
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 
 #include "hw/top/edn_regs.h"  // Generated
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 #define TIMEOUT (10 * 1000 * 1000)
 // AES with Domain-Oriented Masking (DOM) takes 72 cycles per 16B data
@@ -34,14 +36,10 @@ OTTF_DEFINE_TEST_CONFIG();
 
 // Initializes the peripherals used in this test.
 static void init_peripherals(void) {
-  CHECK_DIF_OK(dif_csrng_init(
-      mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR), &csrng));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR), &edn0));
-  CHECK_DIF_OK(
-      dif_edn_init(mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR), &edn1));
-  CHECK_DIF_OK(
-      dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes));
+  CHECK_DIF_OK(dif_csrng_init_from_dt(kDtCsrng, &csrng));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn0, &edn0));
+  CHECK_DIF_OK(dif_edn_init_from_dt(kDtEdn1, &edn1));
+  CHECK_DIF_OK(dif_aes_init_from_dt(kDtAes, &aes));
 }
 
 // Wrapper function for the AES_TESTUTILS_WAIT_FOR_STATUS macro.
diff --git a/sw/device/tests/rv_core_ibex_epmp_test.c b/sw/device/tests/rv_core_ibex_epmp_test.c
index 132a3f7dadfef..837fd7ff6643c 100644
--- a/sw/device/tests/rv_core_ibex_epmp_test.c
+++ b/sw/device/tests/rv_core_ibex_epmp_test.c
@@ -2,6 +2,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "hw/top/dt/dt_pinmux.h"     // Generated
+#include "hw/top/dt/dt_sram_ctrl.h"  // Generated
 #include "sw/device/lib/arch/device.h"
 #include "sw/device/lib/base/csr.h"
 #include "sw/device/lib/dif/dif_uart.h"
@@ -16,8 +18,6 @@
 #include "sw/device/silicon_creator/lib/dbg_print.h"
 #include "sw/device/silicon_creator/lib/epmp_defs.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-
 OTTF_DEFINE_TEST_CONFIG();
 
 /**
@@ -196,8 +196,9 @@ static void pmp_setup_machine_area(void) {
   // but is in a lower PMP register so region 15's configuration
   // will be ignored in this area.
   const uint32_t kRodataEnd = (uint32_t)__rodata_end;
-  const uint32_t kSramEnd = TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR +
-                            TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES;
+  const uint32_t kSramEnd =
+      dt_sram_ctrl_memory_base(kDtSramCtrlMain, kDtSramCtrlMemoryRam) +
+      dt_sram_ctrl_memory_size(kDtSramCtrlMain, kDtSramCtrlMemoryRam);
 
   CSR_WRITE(CSR_REG_PMPADDR8, tor_address(kRodataEnd));
   CSR_WRITE(CSR_REG_PMPADDR9, tor_address(kSramEnd));
@@ -266,8 +267,7 @@ static void pmp_setup_test_locations(void) {
  */
 static void setup_uart(void) {
   // Initialise DIF handles
-  CHECK_DIF_OK(dif_pinmux_init(
-      mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR), &pinmux));
+  CHECK_DIF_OK(dif_pinmux_init_from_dt(kDtPinmuxAon, &pinmux));
 
   // Initialise UART console.
   pinmux_testutils_init(&pinmux);
diff --git a/sw/device/tests/rv_core_ibex_mem_test.c b/sw/device/tests/rv_core_ibex_mem_test.c
index f316db8f9cebf..8a9260cd01bf4 100644
--- a/sw/device/tests/rv_core_ibex_mem_test.c
+++ b/sw/device/tests/rv_core_ibex_mem_test.c
@@ -17,10 +17,16 @@
  * Two MMIO registers from two different devices are written to and read from.
  */
 
+#include "hw/top/dt/dt_flash_ctrl.h"  // Generated
+#include "hw/top/dt/dt_pinmux.h"      // Generated
+#include "hw/top/dt/dt_pwm.h"         // Generated
+#include "hw/top/dt/dt_rom_ctrl.h"    // Generated
+#include "hw/top/dt/dt_rv_timer.h"    // Generated
 #include "sw/device/lib/arch/boot_stage.h"
 #include "sw/device/lib/arch/device.h"
 #include "sw/device/lib/base/csr.h"
 #include "sw/device/lib/dif/dif_flash_ctrl.h"
+#include "sw/device/lib/dif/dif_pwm.h"
 #include "sw/device/lib/dif/dif_uart.h"
 #include "sw/device/lib/runtime/ibex.h"
 #include "sw/device/lib/runtime/log.h"
@@ -36,15 +42,19 @@
 #include "hw/top/flash_ctrl_regs.h"
 #include "hw/top/pwm_regs.h"
 #include "hw/top/rv_timer_regs.h"
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 OTTF_DEFINE_TEST_CONFIG();
 
+static_assert(kDtFlashCtrlCount == 1, "this test expects a flash_ctrl");
+static_assert(kDtPwmCount == 1, "this test expects a pwm");
+static_assert(kDtRvTimerCount == 1, "this test expects a rv_timer");
+static_assert(kDtRomCtrlCount == 1, "this test expects a rom_ctrl");
+
 enum {
   // Search within this ROM region to find `c.jr x1`, so execution can be
-  // tested.
-  kRomTestLocStart = TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + 0x400,
-  kRomTestLocEnd = TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + 0x500,
+  // tested. ROM base address will be computed at runtime.
+  kRomTestLocOffset = 0x400,
+  kRomTestLocSize = 0x100,
   kRomTestLocContent = 0x8082,
 
   // Number of bytes per page.
@@ -57,23 +67,12 @@ enum {
   // The start page used by this test. Points to the start of the owner
   // partition in bank 1, otherwise known as owner partition B.
   kBank1StartPageNum = 256 + kRomExtPageCount,
-
-  kFlashTestLoc = TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR +
-                  kBank1StartPageNum * kFlashBytesPerPage,
 };
 
 // The flash test location is set to the encoding of `jalr x0, 0(x1)`
 // so execution can be tested.
 const uint32_t kFlashTestLocContent = 0x00008067;
-void (*flash_test_gadget)(void) = (void (*)(void))kFlashTestLoc;
-
-volatile uint32_t *kMMIOTestLoc1 =
-    (uint32_t *)(TOP_EARLGREY_RV_TIMER_BASE_ADDR +
-                 RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET);
 const uint32_t kMMIOTestLoc1Content = 0x126d8c15;  // a random value
-
-volatile uint32_t *kMMIOTestLoc2 =
-    (uint32_t *)(TOP_EARLGREY_PWM_AON_BASE_ADDR + PWM_DUTY_CYCLE_0_REG_OFFSET);
 const uint32_t kMMIOTestLoc2Content = 0xe4210e64;  // a random value
 
 /**
@@ -84,8 +83,7 @@ static void setup_uart(void) {
   static dif_pinmux_t pinmux;
 
   // Initialise DIF handles
-  CHECK_DIF_OK(dif_pinmux_init(
-      mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR), &pinmux));
+  CHECK_DIF_OK(dif_pinmux_init_from_dt(kDtPinmuxAon, &pinmux));
 
   // Initialise UART console.
   pinmux_testutils_init(&pinmux);
@@ -113,13 +111,16 @@ static void use_icache(bool enable) {
  */
 static void setup_flash(void) {
   // Create a PMP region for the flash
+  uintptr_t flash_mem_base =
+      dt_flash_ctrl_memory_base(kDtFlashCtrl, kDtFlashCtrlMemoryMem);
+  size_t flash_mem_size =
+      dt_flash_ctrl_memory_size(kDtFlashCtrl, kDtFlashCtrlMemoryMem);
   pmp_region_config_t config = {
       .lock = kPmpRegionLockLocked,
       .permissions = kPmpRegionPermissionsReadWriteExecute,
   };
-  pmp_region_configure_napot_result_t result = pmp_region_configure_napot(
-      8, config, TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR,
-      TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES);
+  pmp_region_configure_napot_result_t result =
+      pmp_region_configure_napot(8, config, flash_mem_base, flash_mem_size);
   CHECK(result == kPmpRegionConfigureNapotOk,
         "Load configuration failed, error code = %d", result);
   // When running as ROM_EXT, ROM configures the flash memory to be readonly.
@@ -132,9 +133,7 @@ static void setup_flash(void) {
 
   // Initialise the flash controller.
   dif_flash_ctrl_state_t flash_ctrl;
-  CHECK_DIF_OK(dif_flash_ctrl_init_state(
-      &flash_ctrl,
-      mmio_region_from_addr(TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR)));
+  CHECK_DIF_OK(dif_flash_ctrl_init_state_from_dt(&flash_ctrl, kDtFlashCtrl));
 
   CHECK_STATUS_OK(flash_ctrl_testutils_wait_for_init(&flash_ctrl));
 
@@ -158,6 +157,8 @@ static void setup_flash(void) {
       dif_flash_ctrl_set_exec_enablement(&flash_ctrl, kDifToggleEnabled));
 
   // Write the wanted value to flash
+  uintptr_t kFlashTestLoc =
+      flash_mem_base + kBank1StartPageNum * kFlashBytesPerPage;
   CHECK_STATUS_OK(flash_ctrl_testutils_erase_and_write_page(
       /*flash_state=*/&flash_ctrl,
       /*byte_address=*/kFlashTestLoc,
@@ -167,16 +168,26 @@ static void setup_flash(void) {
       /*word_count=*/1));
 }
 
-/**
- * The entry point of the SRAM test.
- */
 bool test_main(void) {
   setup_uart();
 
+  volatile uint32_t *kMMIOTestLoc1 =
+      dt_rv_timer_reg_block(kDtRvTimer, kDtRvTimerRegBlockCore) +
+      RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET;
+  volatile uint32_t *kMMIOTestLoc2 =
+      dt_pwm_reg_block(kDtPwmAon, kDtPwmRegBlockCore) +
+      PWM_DUTY_CYCLE_0_REG_OFFSET;
+
   // ROM access is blocked in the silicon owner stage.
   if (kBootStage != kBootStageOwner) {
     LOG_INFO("Testing Load from ROM Location.");
 
+    // Get ROM base address
+    uintptr_t rom_base =
+        dt_rom_ctrl_memory_base(kDtRomCtrl, kDtRomCtrlMemoryRom);
+    uintptr_t kRomTestLocStart = rom_base + kRomTestLocOffset;
+    uintptr_t kRomTestLocEnd = kRomTestLocStart + kRomTestLocSize;
+
     // For the execution test we a specific `c.jr x1` (i.e. function return)
     // instruction. Since the address can vary between ROM builds, we scan a
     // small region to find it.
@@ -221,6 +232,11 @@ bool test_main(void) {
   setup_flash();
 
   LOG_INFO("Check flash load");
+  uintptr_t flash_mem_base =
+      dt_flash_ctrl_memory_base(kDtFlashCtrl, kDtFlashCtrlMemoryMem);
+  uintptr_t kFlashTestLoc =
+      flash_mem_base + kBank1StartPageNum * kFlashBytesPerPage;
+  void (*flash_test_gadget)(void) = (void (*)(void))kFlashTestLoc;
   load = *(volatile const uint32_t *)kFlashTestLoc;
   CHECK(
       load == kFlashTestLocContent,
diff --git a/sw/device/tests/rv_dm_access_after_hw_reset.c b/sw/device/tests/rv_dm_access_after_hw_reset.c
index cf403f09fe1e7..715b9a81a8c3d 100644
--- a/sw/device/tests/rv_dm_access_after_hw_reset.c
+++ b/sw/device/tests/rv_dm_access_after_hw_reset.c
@@ -2,14 +2,13 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "hw/top/dt/dt_rstmgr.h"  // Generated
 #include "sw/device/lib/runtime/log.h"
 #include "sw/device/lib/testing/rstmgr_testutils.h"
 #include "sw/device/lib/testing/test_framework/check.h"
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 #include "sw/device/lib/testing/test_framework/ottf_utils.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-
 /*
   - Wait for host to perform debugger tests
   - Once the host side confirms, do a SW reset of the chip
@@ -37,8 +36,7 @@ static void chip_sw_reset(void) {
 }
 
 bool test_main(void) {
-  CHECK_DIF_OK(dif_rstmgr_init(
-      mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr));
+  CHECK_DIF_OK(dif_rstmgr_init_from_dt(kDtRstmgrAon, &rstmgr));
 
   // Check if there was a HW reset caused by the software.
   dif_rstmgr_reset_info_bitfield_t rst_info;
diff --git a/sw/device/tests/sram_ctrl_lc_escalation_test.c b/sw/device/tests/sram_ctrl_lc_escalation_test.c
index 03d1cfe4a2651..e3e3bcf0a8a3f 100644
--- a/sw/device/tests/sram_ctrl_lc_escalation_test.c
+++ b/sw/device/tests/sram_ctrl_lc_escalation_test.c
@@ -17,6 +17,9 @@
  * through the debug module.
  */
 
+#include "hw/top/dt/dt_alert_handler.h"  // Generated
+#include "hw/top/dt/dt_lc_ctrl.h"        // Generated
+#include "hw/top/dt/dt_sram_ctrl.h"      // Generated
 #include "sw/device/lib/arch/device.h"
 #include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/mmio.h"
@@ -30,7 +33,6 @@
 #include "sw/device/silicon_creator/lib/drivers/retention_sram.h"
 
 #include "hw/top/sram_ctrl_regs.h"  // Generated.
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 static const uint32_t kStatusRegMask = kDifSramCtrlStatusBusIntegErr |
                                        kDifSramCtrlStatusInitErr |
@@ -69,11 +71,8 @@ static bool write_read_data(mmio_region_t sram_region, uint32_t data) {
 }
 
 status_t configure_srams(void) {
-  uint32_t base_addr;
-  base_addr = TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR;
-  TRY(dif_sram_ctrl_init(mmio_region_from_addr(base_addr), &sram_ctrl_main));
-  base_addr = TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR;
-  TRY(dif_sram_ctrl_init(mmio_region_from_addr(base_addr), &sram_ctrl_ret));
+  TRY(dif_sram_ctrl_init_from_dt(kDtSramCtrlMain, &sram_ctrl_main));
+  TRY(dif_sram_ctrl_init_from_dt(kDtSramCtrlRetAon, &sram_ctrl_ret));
 
   dif_sram_ctrl_status_bitfield_t status_main;
   dif_sram_ctrl_status_bitfield_t status_ret;
@@ -91,9 +90,7 @@ status_t configure_srams(void) {
 }
 
 status_t configure_alert_handler(void) {
-  TRY(dif_alert_handler_init(
-      mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR),
-      &alert_handler));
+  TRY(dif_alert_handler_init_from_dt(kDtAlertHandler, &alert_handler));
 
   dif_alert_handler_escalation_phase_t esc_phases[] = {{
       .phase = kDifAlertHandlerClassStatePhase0,
@@ -111,7 +108,9 @@ status_t configure_alert_handler(void) {
   };
 
   TRY(dif_alert_handler_configure_alert(
-      &alert_handler, kTopEarlgreyAlertIdLcCtrlFatalBusIntegError,
+      &alert_handler,
+      dt_lc_ctrl_alert_to_alert_id(kDtLcCtrlFirst,
+                                   kDtLcCtrlAlertFatalBusIntegError),
       kDifAlertHandlerClassA, kDifToggleEnabled, kDifToggleEnabled));
   TRY(dif_alert_handler_configure_class(&alert_handler, kDifAlertHandlerClassA,
                                         class_config, kDifToggleEnabled,
@@ -123,8 +122,7 @@ status_t configure_alert_handler(void) {
 OTTF_DEFINE_TEST_CONFIG(.enable_uart_flow_control = true);
 
 bool test_main(void) {
-  CHECK_DIF_OK(dif_lc_ctrl_init(
-      mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR), &lc_ctrl));
+  CHECK_DIF_OK(dif_lc_ctrl_init_from_dt(kDtLcCtrlFirst, &lc_ctrl));
 
   CHECK_STATUS_OK(configure_alert_handler());
   CHECK_STATUS_OK(configure_srams());
@@ -132,8 +130,9 @@ bool test_main(void) {
   // Read and Write to/from SRAMs. Main SRAM will use the address of the
   // buffer that has been allocated. Ret SRAM can start at the owner section.
   sram_buffer_addr_main = (uintptr_t)&sram_buffer_main;
-  sram_buffer_addr_ret = TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR +
-                         offsetof(retention_sram_t, owner);
+  sram_buffer_addr_ret =
+      dt_sram_ctrl_memory_base(kDtSramCtrlRetAon, kDtSramCtrlMemoryRam) +
+      offsetof(retention_sram_t, owner);
 
   mmio_region_t sram_region_main = mmio_region_from_addr(sram_buffer_addr_main);
   mmio_region_t sram_region_ret = mmio_region_from_addr(sram_buffer_addr_ret);
diff --git a/sw/device/tests/sram_ctrl_memset_test.c b/sw/device/tests/sram_ctrl_memset_test.c
index aed0dc5e30ce6..2e18838a96237 100644
--- a/sw/device/tests/sram_ctrl_memset_test.c
+++ b/sw/device/tests/sram_ctrl_memset_test.c
@@ -8,6 +8,7 @@
 //! The test currently only checks the retention SRAM so that it can be run out
 //! of executable main SRAM on silicon.
 
+#include "hw/top/dt/dt_sram_ctrl.h"  // Generated
 #include "sw/device/lib/arch/device.h"
 #include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/mmio.h"
@@ -18,7 +19,6 @@
 #include "sw/device/silicon_creator/lib/drivers/retention_sram.h"
 
 #include "hw/top/sram_ctrl_regs.h"  // Generated.
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 // Define some amount of data we should leave in SRAM to check it gets wiped.
 enum {
@@ -85,14 +85,12 @@ static void init_sram(dif_sram_ctrl_t sram_ctrl) {
 bool test_main(void) {
   // Initialize SRAM_CTRL hardware.
   dif_sram_ctrl_t sram_ctrl_ret;
-  CHECK_DIF_OK(dif_sram_ctrl_init(
-      mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR),
-      &sram_ctrl_ret));
+  CHECK_DIF_OK(dif_sram_ctrl_init_from_dt(kDtSramCtrlRetAon, &sram_ctrl_ret));
 
   init_sram(sram_ctrl_ret);
 
   uintptr_t sram_ret_buffer_addr =
-      TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR +
+      dt_sram_ctrl_memory_base(kDtSramCtrlRetAon, kDtSramCtrlMemoryRam) +
       offsetof(retention_sram_t, owner);
 
   mmio_region_t sram_region_ret_addr =
diff --git a/sw/device/tests/sram_ctrl_readback_test.c b/sw/device/tests/sram_ctrl_readback_test.c
index c89c9ffa88cb0..788393e41c796 100644
--- a/sw/device/tests/sram_ctrl_readback_test.c
+++ b/sw/device/tests/sram_ctrl_readback_test.c
@@ -5,6 +5,7 @@
 //! This test is identical to the sram_ctrl_memset_test except that the SRAM
 //! readack mode gets enabled.
 
+#include "hw/top/dt/dt_sram_ctrl.h"  // Generated
 #include "sw/device/lib/arch/device.h"
 #include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/mmio.h"
@@ -15,7 +16,6 @@
 #include "sw/device/silicon_creator/lib/drivers/retention_sram.h"
 
 #include "hw/top/sram_ctrl_regs.h"  // Generated.
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 
 // Define some amount of data we should leave in SRAM to check it gets wiped.
 enum {
@@ -82,14 +82,12 @@ static void init_sram(dif_sram_ctrl_t sram_ctrl) {
 bool test_main(void) {
   // Initialize SRAM_CTRL hardware.
   dif_sram_ctrl_t sram_ctrl_ret;
-  CHECK_DIF_OK(dif_sram_ctrl_init(
-      mmio_region_from_addr(TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR),
-      &sram_ctrl_ret));
+  CHECK_DIF_OK(dif_sram_ctrl_init_from_dt(kDtSramCtrlRetAon, &sram_ctrl_ret));
 
   init_sram(sram_ctrl_ret);
 
   uintptr_t sram_ret_buffer_addr =
-      TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR +
+      dt_sram_ctrl_memory_base(kDtSramCtrlRetAon, kDtSramCtrlMemoryRam) +
       offsetof(retention_sram_t, owner);
 
   mmio_region_t sram_region_ret_addr =