From 6e8bed398b4d0855e4b0f3841b8f638a4b3be62b Mon Sep 17 00:00:00 2001 From: Alice Ziuziakowska Date: Wed, 5 Nov 2025 13:52:26 +0000 Subject: [PATCH] [otlib] eeprom use constants from SpiFlash instead of redeclaring These are a common SPI Flash opcode and bitfield, so just import them from SpiFlash instead of redeclaring. Also fixes a spelling mistake. Signed-off-by: Alice Ziuziakowska --- sw/host/opentitanlib/src/io/eeprom.rs | 12 +++++------- sw/host/opentitanlib/src/transport/dediprog/spi.rs | 6 +++--- sw/host/opentitanlib/src/transport/hyperdebug/spi.rs | 7 ++++--- 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/sw/host/opentitanlib/src/io/eeprom.rs b/sw/host/opentitanlib/src/io/eeprom.rs index cc1d7804e4963..c0a98c9d4cb20 100644 --- a/sw/host/opentitanlib/src/io/eeprom.rs +++ b/sw/host/opentitanlib/src/io/eeprom.rs @@ -6,6 +6,7 @@ use anyhow::Result; use serde::{Deserialize, Serialize}; use super::spi::{SpiError, Target, Transfer}; +use crate::spiflash::SpiFlash; #[derive(Debug, Clone, Copy, Serialize, Deserialize, PartialEq, Eq)] /// Declarations of if and when to switch from single-lane SPI to a faster mode. @@ -242,15 +243,12 @@ pub enum Transaction<'rd, 'wr> { WaitForBusyClear, } -pub const READ_STATUS: u8 = 0x05; -pub const STATUS_WIP: u8 = 0x01; - pub fn default_run_eeprom_transactions( spi: &T, transactions: &mut [Transaction], ) -> Result<()> { // Default implementation translates into generic SPI read/write, which works as long as - // the transport supports generic SPI transfers of sufficint length, and that the mode is + // the transport supports generic SPI transfers of sufficient length, and that the mode is // single-data-wire. for transfer in transactions { match transfer { @@ -264,10 +262,10 @@ pub fn default_run_eeprom_transactions( spi.run_transaction(&mut [Transfer::Write(cmd.to_bytes()?), Transfer::Write(wbuf)])? } Transaction::WaitForBusyClear => { - let mut status = STATUS_WIP; - while status & STATUS_WIP != 0 { + let mut status = SpiFlash::STATUS_WIP; + while status & SpiFlash::STATUS_WIP != 0 { spi.run_transaction(&mut [ - Transfer::Write(&[READ_STATUS]), + Transfer::Write(&[SpiFlash::READ_STATUS]), Transfer::Read(std::slice::from_mut(&mut status)), ])?; } diff --git a/sw/host/opentitanlib/src/transport/dediprog/spi.rs b/sw/host/opentitanlib/src/transport/dediprog/spi.rs index 5e23ed50fc155..c2fcd9c78b7bd 100644 --- a/sw/host/opentitanlib/src/transport/dediprog/spi.rs +++ b/sw/host/opentitanlib/src/transport/dediprog/spi.rs @@ -284,10 +284,10 @@ impl DediprogSpi { } [WaitForBusyClear, rest @ ..] => { transactions = rest; - let mut status = eeprom::STATUS_WIP; - while status & eeprom::STATUS_WIP != 0 { + let mut status = SpiFlash::STATUS_WIP; + while status & SpiFlash::STATUS_WIP != 0 { self.run_transaction(&mut [ - Transfer::Write(&[eeprom::READ_STATUS]), + Transfer::Write(&[SpiFlash::READ_STATUS]), Transfer::Read(std::slice::from_mut(&mut status)), ])?; } diff --git a/sw/host/opentitanlib/src/transport/hyperdebug/spi.rs b/sw/host/opentitanlib/src/transport/hyperdebug/spi.rs index 4a5fabde83fa3..05a0b30bc6946 100644 --- a/sw/host/opentitanlib/src/transport/hyperdebug/spi.rs +++ b/sw/host/opentitanlib/src/transport/hyperdebug/spi.rs @@ -15,6 +15,7 @@ use crate::io::gpio::GpioPin; use crate::io::spi::{ AssertChipSelect, MaxSizes, SpiError, Target, TargetChipDeassert, Transfer, TransferMode, }; +use crate::spiflash::flash::SpiFlash; use crate::transport::TransportError; use crate::transport::hyperdebug::{BulkInterface, Inner}; @@ -911,10 +912,10 @@ impl Target for HyperdebugSpiTarget { } [eeprom::Transaction::WaitForBusyClear, rest @ ..] => { self.get_last_streamed_data(stream_state)?; - let mut status = eeprom::STATUS_WIP; - while status & eeprom::STATUS_WIP != 0 { + let mut status = SpiFlash::STATUS_WIP; + while status & SpiFlash::STATUS_WIP != 0 { self.run_transaction(&mut [ - Transfer::Write(&[eeprom::READ_STATUS]), + Transfer::Write(&[SpiFlash::READ_STATUS]), Transfer::Read(std::slice::from_mut(&mut status)), ])?; }