diff --git a/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson b/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson
index a508cb7bb64f9..a9ce2989d227e 100644
--- a/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson
+++ b/hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson
@@ -169,6 +169,8 @@
       si_stage: SV3
       lc_states: [
         "DEV",
+        "TEST_UNLOCKED",
+        "RMA",
       ]
       tests: [
         "chip_sw_clkmgr_external_clk_src_for_sw_fast_dev",
diff --git a/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson b/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson
index 4b7f0a4aa8647..a97383815db00 100644
--- a/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson
+++ b/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson
@@ -71,10 +71,10 @@
     {
       name: chip_rv_dm_perform_debug
       desc: '''
-            - X-ref'ed with rom_e2e_jtag_debug from rom testplan.
-
             Verify that ROM can be debugged in appropriate life cycle states.
 
+            - X-ref'ed with rom_e2e_jtag_debug from rom testplan.
+
             `CREATOR_SW_CFG_ROM_EXEC_EN` should be set to `0`.
 
             - Verify that ROM can be debugged in TEST, DEV, and RMA life cycle states.
@@ -106,7 +106,7 @@
         "//sw/device/silicon_creator/rom/e2e/jtag_inject:openocd_debug_test_otp_rma",
         "//sw/device/silicon_creator/rom/e2e/jtag_inject:openocd_debug_test_otp_test_unlocked0"
       ],
-      lc_states: ["DEV"]
+      lc_states: ["DEV", "TEST_UNLOCKED0", "RMA"]
       host_support: true
       features: [
         "RV_DM.JTAG.FSM",
@@ -219,7 +219,7 @@
       name: chip_sw_rv_dm_jtag_tap_sel
       desc: '''Verify ability to select all available TAPs.
 
-            - Put life cycle on Test or RMA state, so that TAPs can be selected between life cycle
+            - Put life cycle on DEV, TEST_UNLOCKED or RMA state, so that TAPs can be selected between life cycle
               RV_DM and DFT.
             - Verify the TAP is selected correctly.
             - X-ref'ed with chip_sw_tap_strap_sampling.