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ziuziakowskaziuziakowska
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[ot] hw/opentitan: ot_spi_device: make logging use ot_id
Signed-off-by: Alice Ziuziakowska <[email protected]>
1 parent 0eedbc8 commit 10c6611

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+35
-27
lines changed

1 file changed

+35
-27
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‎hw/opentitan/ot_spi_device.c‎

Lines changed: 35 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1559,28 +1559,31 @@ ot_spi_device_spi_regs_read(void *opaque, hwaddr addr, unsigned size)
15591559
if (!fifo8_is_empty(&f->cmd_fifo)) {
15601560
val32 = (uint32_t)fifo8_pop(&f->cmd_fifo);
15611561
} else {
1562-
qemu_log_mask(LOG_UNIMP, "%s: CMD_FIFO is empty\n", __func__);
1562+
qemu_log_mask(LOG_UNIMP, "%s: %s: CMD_FIFO is empty\n", __func__,
1563+
s->ot_id);
15631564
val32 = 0;
15641565
}
15651566
break;
15661567
case R_UPLOAD_ADDRFIFO:
15671568
if (!ot_fifo32_is_empty(&f->address_fifo)) {
15681569
val32 = ot_fifo32_pop(&f->address_fifo);
15691570
} else {
1570-
qemu_log_mask(LOG_UNIMP, "%s: ADDR_FIFO is empty\n", __func__);
1571+
qemu_log_mask(LOG_UNIMP, "%s: %s: ADDR_FIFO is empty\n", __func__,
1572+
s->ot_id);
15711573
val32 = 0;
15721574
}
15731575
break;
15741576
case R_INTR_TEST:
15751577
case R_ALERT_TEST:
15761578
qemu_log_mask(LOG_GUEST_ERROR,
1577-
"%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
1578-
addr, SPI_REG_NAME(reg));
1579+
"%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
1580+
__func__, s->ot_id, addr, SPI_REG_NAME(reg));
15791581
val32 = 0;
15801582
break;
15811583
default:
1582-
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1583-
__func__, addr);
1584+
qemu_log_mask(LOG_GUEST_ERROR,
1585+
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
1586+
s->ot_id, addr);
15841587
val32 = 0;
15851588
break;
15861589
}
@@ -1652,7 +1655,8 @@ static void ot_spi_device_spi_regs_write(void *opaque, hwaddr addr,
16521655
case CTRL_MODE_DISABLED:
16531656
case CTRL_MODE_PASSTHROUGH:
16541657
default:
1655-
qemu_log_mask(LOG_UNIMP, "%s: unsupported mode\n", __func__);
1658+
qemu_log_mask(LOG_UNIMP, "%s: %s: unsupported mode\n", __func__,
1659+
s->ot_id);
16561660
break;
16571661
}
16581662
break;
@@ -1741,12 +1745,13 @@ static void ot_spi_device_spi_regs_write(void *opaque, hwaddr addr,
17411745
case R_UPLOAD_CMDFIFO:
17421746
case R_UPLOAD_ADDRFIFO:
17431747
qemu_log_mask(LOG_GUEST_ERROR,
1744-
"%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
1745-
addr, SPI_REG_NAME(reg));
1748+
"%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
1749+
__func__, s->ot_id, addr, SPI_REG_NAME(reg));
17461750
break;
17471751
default:
1748-
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1749-
__func__, addr);
1752+
qemu_log_mask(LOG_GUEST_ERROR,
1753+
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
1754+
s->ot_id, addr);
17501755
break;
17511756
}
17521757
};
@@ -1780,19 +1785,20 @@ ot_spi_device_tpm_regs_read(void *opaque, hwaddr addr, unsigned size)
17801785
case R_TPM_INT_STATUS:
17811786
case R_TPM_DID_VID:
17821787
case R_TPM_RID:
1783-
qemu_log_mask(LOG_UNIMP, "%s: %s: not supported\n", __func__,
1784-
TPM_REG_NAME(reg));
1788+
qemu_log_mask(LOG_UNIMP, "%s: %s: %s: not supported\n", __func__,
1789+
s->ot_id, TPM_REG_NAME(reg));
17851790
val32 = s->tpm_regs[reg];
17861791
break;
17871792
case R_TPM_READ_FIFO:
17881793
qemu_log_mask(LOG_GUEST_ERROR,
1789-
"%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
1790-
addr, SPI_REG_NAME(reg));
1794+
"%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
1795+
__func__, s->ot_id, addr, SPI_REG_NAME(reg));
17911796
val32 = 0u;
17921797
break;
17931798
default:
1794-
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1795-
__func__, addr);
1799+
qemu_log_mask(LOG_GUEST_ERROR,
1800+
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
1801+
s->ot_id, addr);
17961802
val32 = 0u;
17971803
break;
17981804
}
@@ -1845,12 +1851,13 @@ static void ot_spi_device_tpm_regs_write(void *opaque, hwaddr addr,
18451851
case R_TPM_CAP:
18461852
case R_TPM_CMD_ADDR:
18471853
qemu_log_mask(LOG_GUEST_ERROR,
1848-
"%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
1849-
addr, TPM_REG_NAME(reg));
1854+
"%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
1855+
__func__, s->ot_id, addr, TPM_REG_NAME(reg));
18501856
break;
18511857
default:
1852-
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1853-
__func__, addr);
1858+
qemu_log_mask(LOG_GUEST_ERROR,
1859+
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
1860+
s->ot_id, addr);
18541861
break;
18551862
}
18561863
};
@@ -1866,8 +1873,8 @@ static MemTxResult ot_spi_device_buf_read_with_attrs(
18661873

18671874
if (addr < SPI_SRAM_INGRESS_OFFSET) {
18681875
qemu_log_mask(LOG_GUEST_ERROR,
1869-
"%s: cannot read egress buffer 0x%" HWADDR_PRIx "\n",
1870-
__func__, addr);
1876+
"%s: %s: cannot read egress buffer 0x%" HWADDR_PRIx "\n",
1877+
__func__, s->ot_id, addr);
18711878
return MEMTX_DECODE_ERROR;
18721879
}
18731880

@@ -1887,9 +1894,9 @@ static MemTxResult ot_spi_device_buf_read_with_attrs(
18871894
val32 = s->flash.address_fifo.data[addr >> 2u];
18881895
} else {
18891896
qemu_log_mask(LOG_GUEST_ERROR,
1890-
"%s: Invalid ingress buffer access to 0x%" HWADDR_PRIx
1897+
"%s: %s: Invalid ingress buffer access to 0x%" HWADDR_PRIx
18911898
"-0x%" HWADDR_PRIx "\n",
1892-
__func__, addr, last);
1899+
__func__, s->ot_id, addr, last);
18931900
val32 = 0;
18941901
}
18951902

@@ -1921,8 +1928,9 @@ static MemTxResult ot_spi_device_buf_write_with_attrs(
19211928

19221929
if (last >= SPI_SRAM_INGRESS_OFFSET) {
19231930
qemu_log_mask(LOG_GUEST_ERROR,
1924-
"%s: cannot write ingress buffer 0x%" HWADDR_PRIx "\n",
1925-
__func__, addr);
1931+
"%s: %s: cannot write ingress buffer 0x%" HWADDR_PRIx
1932+
"\n",
1933+
__func__, s->ot_id, addr);
19261934
return MEMTX_DECODE_ERROR;
19271935
}
19281936
s->sram[addr >> 2u] = val32;

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