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AlexJones0jwnrt
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[ot] hw/opentitan: ot_ibex_wrapper: Fix Fatal SW alert signal
This was using the wrong mask and so was sending all four alerts on a SW-triggered fatal alert, but should actually just be sending the 1 alert for fatal SW alerts. Also change the naming of the alert fields to more closely align with the actual alert indexes, rather than being specific to the alert test register. Signed-off-by: Alex Jones <[email protected]>
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hw/opentitan/ot_ibex_wrapper.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -71,10 +71,10 @@
7171

7272
/* clang-format off */
7373
REG32(ALERT_TEST, 0x0u)
74-
FIELD(ALERT_TEST, FATAL_SW, 0u, 1u)
75-
FIELD(ALERT_TEST, RECOV_SW, 1u, 1u)
76-
FIELD(ALERT_TEST, FATAL_HW, 2u, 1u)
77-
FIELD(ALERT_TEST, RECOV_HW, 3u, 1u)
74+
SHARED_FIELD(ALERT_FATAL_SW, 0u, 1u)
75+
SHARED_FIELD(ALERT_RECOV_SW, 1u, 1u)
76+
SHARED_FIELD(ALERT_FATAL_HW, 2u, 1u)
77+
SHARED_FIELD(ALERT_RECOV_HW, 3u, 1u)
7878
REG32(SW_RECOV_ERR, 0x4u)
7979
FIELD(SW_RECOV_ERR, VAL, 0u, 4u)
8080
REG32(SW_FATAL_ERR, 0x8u)
@@ -93,9 +93,9 @@ SHARED_FIELD(DV_SIM_STATUS_CODE, 0u, 16u)
9393
SHARED_FIELD(DV_SIM_STATUS_INFO, 16u, 16u)
9494
/* clang-format on */
9595

96-
#define ALERT_TEST_MASK \
97-
(R_ALERT_TEST_FATAL_SW_MASK | R_ALERT_TEST_RECOV_SW_MASK | \
98-
R_ALERT_TEST_FATAL_HW_MASK | R_ALERT_TEST_RECOV_HW_MASK)
96+
#define ALERT_MASK \
97+
(ALERT_FATAL_SW_MASK | ALERT_RECOV_SW_MASK | ALERT_FATAL_HW_MASK | \
98+
ALERT_RECOV_HW_MASK)
9999

100100
#define ERR_STATUS_MASK \
101101
(ERR_STATUS_REG_INTG_MASK | ERR_STATUS_FATAL_INTG_MASK | \
@@ -289,7 +289,7 @@ static void ot_ibex_wrapper_update_alerts(OtIbexWrapperState *s)
289289
uint32_t level = s->regs.alert_test;
290290

291291
if (s->regs.sw_fatal_err != OT_MULTIBITBOOL4_FALSE) {
292-
level |= R_SW_FATAL_ERR_VAL_MASK;
292+
level |= ALERT_FATAL_SW_MASK;
293293
}
294294

295295
for (unsigned ix = 0; ix < NUM_ALERTS; ix++) {
@@ -1339,7 +1339,7 @@ static void ot_ibex_wrapper_fill_tables(OtIbexWrapperState *s)
13391339
s->access_table[R32_DYN_POS(s, dv_sim_win[DV_SIM_LOG])].write =
13401340
&ot_ibex_wrapper_write_dv_sim_log;
13411341

1342-
s->access_table[R32_DYN_POS(s, alert_test)].mask = ALERT_TEST_MASK;
1342+
s->access_table[R32_DYN_POS(s, alert_test)].mask = ALERT_MASK;
13431343
s->access_table[R32_DYN_POS(s, sw_recov_err)].mask =
13441344
R_SW_RECOV_ERR_VAL_MASK;
13451345
/* this register is extended in QEMU, HW mask is applied in HW handler */

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