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6 | 6 | * |
7 | 7 | * Author(s): |
8 | 8 | * Emmanuel Blot <[email protected]> |
| 9 | + |
9 | 10 | * |
10 | 11 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
11 | 12 | * of this software and associated documentation files (the "Software"), to deal |
|
25 | 26 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
26 | 27 | * THE SOFTWARE. |
27 | 28 | * |
28 | | - * Note: for now, only a minimalist subset of Power Manager device is |
29 | | - * implemented in order to enable OpenTitan's ROM boot to progress |
| 29 | + * Known limitations: |
| 30 | + * - ECC/ICV/Scrambling functionality is not yet implemented in QEMU, |
| 31 | + * including ECC single error support. |
| 32 | + * - Alert functionality is not yet modelled (outside of test alerts). |
| 33 | + * - Program Repair / High Endurance enables are meaningless in the OpenTitan |
| 34 | + * Generic Flash Bank and so are not emulated. |
| 35 | + * - Erase Suspend is not emulated in QEMU (erases are done synchronously, so |
| 36 | + * you can suspend, but the bit will immediately be cleared). |
| 37 | + * - HW info cfg overrides are not modelled in QEMU. |
30 | 38 | */ |
31 | 39 |
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32 | 40 | #include "qemu/osdep.h" |
@@ -769,6 +777,7 @@ static void ot_flash_update_irqs(OtFlashState *s) |
769 | 777 |
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770 | 778 | static void ot_flash_update_alerts(OtFlashState *s) |
771 | 779 | { |
| 780 | + /* @todo Implement non-test alert sources and update them here as well. */ |
772 | 781 | uint32_t level = s->regs[R_ALERT_TEST]; |
773 | 782 |
|
774 | 783 | for (unsigned ix = 0u; ix < PARAM_NUM_ALERTS; ix++) { |
@@ -834,7 +843,6 @@ static void ot_flash_update_prog_watermark(OtFlashState *s) |
834 | 843 | ot_flash_update_irqs(s); |
835 | 844 | } |
836 | 845 |
|
837 | | - |
838 | 846 | static void ot_flash_op_signal(void *opaque) |
839 | 847 | { |
840 | 848 | OtFlashState *s = opaque; |
@@ -1838,8 +1846,13 @@ static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64, |
1838 | 1846 | s->regs[reg] = val32; |
1839 | 1847 | break; |
1840 | 1848 | case R_ERASE_SUSPEND: |
1841 | | - val32 &= R_ERASE_SUSPEND_REQ_MASK; |
1842 | | - s->regs[reg] = val32; |
| 1849 | + /* |
| 1850 | + * @todo We do not implement the erase suspend operation in QEMU as we |
| 1851 | + * do all erases synchronously, and so just immediately clear the erase |
| 1852 | + * suspend request. To implement this feature properly we would have to |
| 1853 | + * add delay to bank erases & check for erase suspends at each step. |
| 1854 | + */ |
| 1855 | + s->regs[reg] = 0u; |
1843 | 1856 | break; |
1844 | 1857 | case R_REGION_CFG_REGWEN_0: |
1845 | 1858 | case R_REGION_CFG_REGWEN_1: |
@@ -2498,6 +2511,8 @@ static void ot_flash_load(OtFlashState *s, Error **errp) |
2498 | 2511 | * - INFO1 bank 1 |
2499 | 2512 | * - INFO2 bank 1 |
2500 | 2513 | * - Debug info (ELF file names) |
| 2514 | + * |
| 2515 | + * @todo Add ECC section to backend for ECC/ICV support also |
2501 | 2516 | */ |
2502 | 2517 | flash->data = (uint32_t *)(base); |
2503 | 2518 | flash->info = |
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