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[ot] hw/opentitan: ot_spi_device: make logging use ot_id
Signed-off-by: Alice Ziuziakowska <[email protected]>
1 parent c32ae97 commit 5f7db5c

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+35
-27
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1 file changed

+35
-27
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‎hw/opentitan/ot_spi_device.c‎

Lines changed: 35 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1536,28 +1536,31 @@ ot_spi_device_spi_regs_read(void *opaque, hwaddr addr, unsigned size)
15361536
if (!fifo8_is_empty(&f->cmd_fifo)) {
15371537
val32 = (uint32_t)fifo8_pop(&f->cmd_fifo);
15381538
} else {
1539-
qemu_log_mask(LOG_UNIMP, "%s: CMD_FIFO is empty\n", __func__);
1539+
qemu_log_mask(LOG_UNIMP, "%s: %s: CMD_FIFO is empty\n", __func__,
1540+
s->ot_id);
15401541
val32 = 0;
15411542
}
15421543
break;
15431544
case R_UPLOAD_ADDRFIFO:
15441545
if (!ot_fifo32_is_empty(&f->address_fifo)) {
15451546
val32 = ot_fifo32_pop(&f->address_fifo);
15461547
} else {
1547-
qemu_log_mask(LOG_UNIMP, "%s: ADDR_FIFO is empty\n", __func__);
1548+
qemu_log_mask(LOG_UNIMP, "%s: %s: ADDR_FIFO is empty\n", __func__,
1549+
s->ot_id);
15481550
val32 = 0;
15491551
}
15501552
break;
15511553
case R_INTR_TEST:
15521554
case R_ALERT_TEST:
15531555
qemu_log_mask(LOG_GUEST_ERROR,
1554-
"%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
1555-
addr, SPI_REG_NAME(reg));
1556+
"%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
1557+
__func__, s->ot_id, addr, SPI_REG_NAME(reg));
15561558
val32 = 0;
15571559
break;
15581560
default:
1559-
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1560-
__func__, addr);
1561+
qemu_log_mask(LOG_GUEST_ERROR,
1562+
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
1563+
s->ot_id, addr);
15611564
val32 = 0;
15621565
break;
15631566
}
@@ -1629,7 +1632,8 @@ static void ot_spi_device_spi_regs_write(void *opaque, hwaddr addr,
16291632
case CTRL_MODE_DISABLED:
16301633
case CTRL_MODE_PASSTHROUGH:
16311634
default:
1632-
qemu_log_mask(LOG_UNIMP, "%s: unsupported mode\n", __func__);
1635+
qemu_log_mask(LOG_UNIMP, "%s: %s: unsupported mode\n", __func__,
1636+
s->ot_id);
16331637
break;
16341638
}
16351639
break;
@@ -1718,12 +1722,13 @@ static void ot_spi_device_spi_regs_write(void *opaque, hwaddr addr,
17181722
case R_UPLOAD_CMDFIFO:
17191723
case R_UPLOAD_ADDRFIFO:
17201724
qemu_log_mask(LOG_GUEST_ERROR,
1721-
"%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
1722-
addr, SPI_REG_NAME(reg));
1725+
"%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
1726+
__func__, s->ot_id, addr, SPI_REG_NAME(reg));
17231727
break;
17241728
default:
1725-
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1726-
__func__, addr);
1729+
qemu_log_mask(LOG_GUEST_ERROR,
1730+
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
1731+
s->ot_id, addr);
17271732
break;
17281733
}
17291734
};
@@ -1757,19 +1762,20 @@ ot_spi_device_tpm_regs_read(void *opaque, hwaddr addr, unsigned size)
17571762
case R_TPM_INT_STATUS:
17581763
case R_TPM_DID_VID:
17591764
case R_TPM_RID:
1760-
qemu_log_mask(LOG_UNIMP, "%s: %s: not supported\n", __func__,
1761-
TPM_REG_NAME(reg));
1765+
qemu_log_mask(LOG_UNIMP, "%s: %s: %s: not supported\n", __func__,
1766+
s->ot_id, TPM_REG_NAME(reg));
17621767
val32 = s->tpm_regs[reg];
17631768
break;
17641769
case R_TPM_READ_FIFO:
17651770
qemu_log_mask(LOG_GUEST_ERROR,
1766-
"%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
1767-
addr, SPI_REG_NAME(reg));
1771+
"%s: %s: W/O register 0x%02" HWADDR_PRIx " (%s)\n",
1772+
__func__, s->ot_id, addr, SPI_REG_NAME(reg));
17681773
val32 = 0u;
17691774
break;
17701775
default:
1771-
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1772-
__func__, addr);
1776+
qemu_log_mask(LOG_GUEST_ERROR,
1777+
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
1778+
s->ot_id, addr);
17731779
val32 = 0u;
17741780
break;
17751781
}
@@ -1822,12 +1828,13 @@ static void ot_spi_device_tpm_regs_write(void *opaque, hwaddr addr,
18221828
case R_TPM_CAP:
18231829
case R_TPM_CMD_ADDR:
18241830
qemu_log_mask(LOG_GUEST_ERROR,
1825-
"%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
1826-
addr, TPM_REG_NAME(reg));
1831+
"%s: %s: R/O register 0x%02" HWADDR_PRIx " (%s)\n",
1832+
__func__, s->ot_id, addr, TPM_REG_NAME(reg));
18271833
break;
18281834
default:
1829-
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
1830-
__func__, addr);
1835+
qemu_log_mask(LOG_GUEST_ERROR,
1836+
"%s: %s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
1837+
s->ot_id, addr);
18311838
break;
18321839
}
18331840
};
@@ -1843,8 +1850,8 @@ static MemTxResult ot_spi_device_buf_read_with_attrs(
18431850

18441851
if (addr < SPI_SRAM_INGRESS_OFFSET) {
18451852
qemu_log_mask(LOG_GUEST_ERROR,
1846-
"%s: cannot read egress buffer 0x%" HWADDR_PRIx "\n",
1847-
__func__, addr);
1853+
"%s: %s: cannot read egress buffer 0x%" HWADDR_PRIx "\n",
1854+
__func__, s->ot_id, addr);
18481855
return MEMTX_DECODE_ERROR;
18491856
}
18501857

@@ -1864,9 +1871,9 @@ static MemTxResult ot_spi_device_buf_read_with_attrs(
18641871
val32 = s->flash.address_fifo.data[addr >> 2u];
18651872
} else {
18661873
qemu_log_mask(LOG_GUEST_ERROR,
1867-
"%s: Invalid ingress buffer access to 0x%" HWADDR_PRIx
1874+
"%s: %s: Invalid ingress buffer access to 0x%" HWADDR_PRIx
18681875
"-0x%" HWADDR_PRIx "\n",
1869-
__func__, addr, last);
1876+
__func__, s->ot_id, addr, last);
18701877
val32 = 0;
18711878
}
18721879

@@ -1898,8 +1905,9 @@ static MemTxResult ot_spi_device_buf_write_with_attrs(
18981905

18991906
if (last >= SPI_SRAM_INGRESS_OFFSET) {
19001907
qemu_log_mask(LOG_GUEST_ERROR,
1901-
"%s: cannot write ingress buffer 0x%" HWADDR_PRIx "\n",
1902-
__func__, addr);
1908+
"%s: %s: cannot write ingress buffer 0x%" HWADDR_PRIx
1909+
"\n",
1910+
__func__, s->ot_id, addr);
19031911
return MEMTX_DECODE_ERROR;
19041912
}
19051913
s->sram[addr >> 2u] = val32;

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