[ot] target/riscv: Add support for Non-Maskable Interrupts

Adds support for Non-Maskable Interrupts (NMIs) to the RISC-V QEMU
CPU implementation. NMIs are defined by the RISC-V specification to be
independent to regular interrupts, used only for hardware error
conditions and causing an immediate jump to an implementation-defined
NMI vector running in M-mode, regardless of the values of e.g. MIE/MIP.

The spec states that "the values written to mcause on an NMI are
implementation-defined"; in Ibex we always use an mcause of 31 (and a
corresponding mtvec offset of 0x7C to determine the jump address for the
NMI handler). To aid a more generic implementation, this commit
introduces a generic `nmi_cause` CPU environment value that can be used
alongside the NMI functionality to allow implementations to change the
mcause as they see fit.

Signed-off-by: Alex Jones <[email protected]>

Author: AlexJones0

target/riscv/cpu.c

@@ -954,7 +954,9 @@ bool riscv_cpu_has_work(CPUState *cs)
     return riscv_cpu_all_pending(env) != 0 ||
         riscv_cpu_sirq_pending(env) != RISCV_EXCP_NONE ||
         riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE ||
-        env->debug_cs;
+        env->debug_cs ||
+        env->pending_nmi ||
+        env->processing_nmi;
 #else
     return true;
 #endif
@@ -1403,6 +1405,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
                                      BOOL_TO_MASK(level | env->software_seip));
             }
             break;
+        case IRQ_NMI:
+            /* NMIs do not need to update mip */
+            env->pending_nmi = true;
+            riscv_cpu_interrupt(env);
+            break;
         default:
             /* Handle platform / custom local interrupts */
             riscv_cpu_update_mip(env, 1ULL << irq, BOOL_TO_MASK(level));

target/riscv/cpu.h

@@ -447,6 +447,13 @@ struct CPUArchState {
     uint64_t dmhaltvec; /* Address of halt handler */
     uint64_t dmexcpvec; /* Address of exception handler */
 
+    /*
+     * NMI support
+     */
+    bool pending_nmi; /* True if an NMI is pending, and must be handled */
+    bool processing_nmi; /* True if currently in an NMI handler */
+    unsigned nmi_cause; /* Reason for entering NMI */
+
     /*
      * CSRs for PointerMasking extension
      */

target/riscv/cpu_bits.h

@@ -731,6 +731,7 @@ typedef enum RISCVException {
 #define IRQ_M_EXT                          11
 #define IRQ_S_GEXT                         12
 #define IRQ_PMU_OVF                        13
+#define IRQ_NMI                            14
 #define IRQ_LOCAL_MAX                      64
 /* -1 is due to bit zero of hgeip and hgeie being ROZ. */
 #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)

target/riscv/cpu_helper.c

@@ -504,6 +504,18 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
         if (unlikely(env->debug_dm &&
                      (env->debugger || get_field(env->dcsr, DCSR_STEP)))) {
             return false;
+        } else if (unlikely(env->pending_nmi && !env->processing_nmi)) {
+            /*
+             * NMIs are handled in the same way as machine traps, but have an
+             * implementation-defined cause, and must be signalled via
+             * additional flags, since they are implementation-specific, and
+             * not visible through the mip register.
+             */
+            cs->exception_index = RISCV_EXCP_INT_FLAG | env->nmi_cause;
+            env->pending_nmi = false;
+            env->processing_nmi = true;
+            riscv_cpu_do_interrupt(cs);
+            return true;
         }
         int interruptno = riscv_cpu_local_irq_pending(env);
         if (interruptno >= 0) {
@@ -653,7 +665,7 @@ void riscv_cpu_interrupt(CPURISCVState *env)
 
     vstip = env->vstime_irq ? MIP_VSTIP : 0;
 
-    if (env->mip | vsgein | vstip | irqf) {
+    if (env->mip | vsgein | vstip | irqf | env->pending_nmi) {
         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
     } else {
         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);

target/riscv/op_helper.c

@@ -343,6 +343,7 @@ target_ulong helper_mret(CPURISCVState *env)
         mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
     }
     env->mstatus = mstatus;
+    env->processing_nmi = false;
 
     if (riscv_has_ext(env, RVH) && prev_virt) {
         riscv_cpu_swap_hypervisor_regs(env);