[ot] hw/opentitan: ot_spi_host: passthrough mode method and IRQs

This implements a passthrough enable and chip select IRQ and a method to
interact with the downstream SPI bus, for use by upstream SPI Device.

Signed-off-by: Alice Ziuziakowska <[email protected]>

Author: ziuziakowska

hw/opentitan/ot_spi_host.c

@@ -257,6 +257,8 @@ typedef struct {
 } TraceCache;
 #endif /* DISCARD_REPEATED_STATUS_TRACES */
 
+#define SPI_DEFAULT_TX_RX_VALUE ((uint8_t)0xffu)
+
 /* ------------------------------------------------------------------------ */
 /* Types */
 /* ------------------------------------------------------------------------ */
@@ -324,12 +326,6 @@ typedef struct {
     unsigned size;
 } OtSPIHostCmd;
 
-/* this class is only required to manage on-hold reset */
-struct OtSPIHostClass {
-    SysBusDeviceClass parent_class;
-    ResettablePhases parent_phases;
-};
-
 struct OtSPIHostState {
     SysBusDevice parent_obj;
 
@@ -355,6 +351,16 @@ struct OtSPIHostState {
 
     OtSPIHostFsm fsm;
     bool on_reset;
+
+    /*
+     * Upstream SPI Device Passthrough enable and chip select. If we support
+     * passthrough mode (only one CS), The SPI Host CS is muxed with the
+     * passthrough CS, controlled by the passthrough enable signal.
+     */
+    bool passthrough_en; /* Upstream SPI Device Passthrough enable line */
+    bool passthrough_cs; /* Upstream SPI Device Chip Select */
+    bool host_cs0; /* Our Chip Select 0 */
+
     unsigned pclk; /* Current input clock */
     const char *clock_src_name; /* IRQ name once connected */
 
@@ -524,12 +530,33 @@ static bool ot_spi_host_is_ready(const OtSPIHostState *s)
     return !cmdfifo_is_full(s->cmd_fifo);
 }
 
+/* Passthrough functionality is only implemented if there is one CS */
+static bool ot_spi_host_supports_passthrough(const OtSPIHostState *s)
+{
+    return s->num_cs == 1u;
+}
+
+static void ot_spi_host_update_muxed_chip_select(OtSPIHostState *s)
+{
+    if (ot_spi_host_supports_passthrough(s)) {
+        ibex_irq_set(&s->cs_lines[0],
+                     s->passthrough_en ? s->passthrough_cs : s->host_cs0);
+    } else {
+        ibex_irq_set(&s->cs_lines[0], s->host_cs0);
+    }
+}
+
 static void ot_spi_host_chip_select(OtSPIHostState *s, unsigned csid,
                                     bool activate)
 {
     if (csid < s->num_cs) {
         trace_ot_spi_host_cs(s->ot_id, csid, activate ? "" : "de");
-        ibex_irq_set(&s->cs_lines[csid], !activate);
+        if (csid == 0u) {
+            s->host_cs0 = !activate;
+            ot_spi_host_update_muxed_chip_select(s);
+        } else {
+            ibex_irq_set(&s->cs_lines[csid], !activate);
+        }
     }
 }
 
@@ -826,13 +853,31 @@ static void ot_spi_host_step_fsm(OtSPIHostState *s, const char *cause)
 
         if (!s->fsm.transaction) {
             s->fsm.transaction = true;
+            if (ot_spi_host_supports_passthrough(s) && s->active.cmd.cs == 0u &&
+                s->passthrough_en) {
+                qemu_log_mask(
+                    LOG_GUEST_ERROR,
+                    "%s: %s: SPI Host active CS while Passthrough is enabled\n",
+                    __func__, s->ot_id);
+            }
             ot_spi_host_chip_select(s, s->active.cmd.cs, s->fsm.transaction);
         }
 
-        uint8_t tx =
-            write ? (uint8_t)txfifo_pop(s->tx_fifo, length == 1u) : 0xffu;
+        uint8_t tx = write ? (uint8_t)txfifo_pop(s->tx_fifo, length == 1u) :
+                             SPI_DEFAULT_TX_RX_VALUE;
 
-        uint8_t rx = s->fsm.output_en ? ssi_transfer(s->ssi, tx) : 0xffu;
+        uint8_t rx = SPI_DEFAULT_TX_RX_VALUE;
+
+        if (s->fsm.output_en) {
+            if (!ot_spi_host_supports_passthrough(s) || !s->passthrough_en) {
+                rx = (uint8_t)ssi_transfer(s->ssi, tx);
+            } else {
+                qemu_log_mask(
+                    LOG_GUEST_ERROR,
+                    "%s: %s: Host transfer while Passthrough is enabled\n",
+                    __func__, s->ot_id);
+            }
+        }
 
         if (multi && read && write) {
             /* invalid command, lets corrupt input data */
@@ -1293,6 +1338,73 @@ static void ot_spi_host_io_write(void *opaque, hwaddr addr, uint64_t val64,
     }
 }
 
+static uint8_t ot_spi_host_downstream_transfer(OtSPIHostState *s, uint8_t tx)
+{
+    if (!ot_spi_host_supports_passthrough(s)) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: SPI Host does not support passthrough: more than one CS\n",
+            __func__, s->ot_id);
+        return SPI_DEFAULT_TX_RX_VALUE;
+    }
+
+    if (!s->passthrough_en) {
+        trace_ot_spi_host_passthrough_disabled(s->ot_id);
+        return SPI_DEFAULT_TX_RX_VALUE;
+    }
+
+    /* Forward to downstream flash */
+    return (uint8_t)ssi_transfer(s->ssi, (uint32_t)tx);
+}
+
+static void
+ot_spi_host_device_passthrough_en_input(void *opaque, int irq, int level)
+{
+    OtSPIHostState *s = opaque;
+    g_assert(irq == 0u);
+
+    if (!ot_spi_host_supports_passthrough(s)) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: SPI Host does not support passthrough: more than one CS\n",
+            __func__, s->ot_id);
+        return;
+    }
+
+    if ((bool)level && !s->host_cs0) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: %s: Passthrough enabled while Host CS is active\n",
+                      __func__, s->ot_id);
+    }
+
+    s->passthrough_en = (bool)level;
+
+    ot_spi_host_update_muxed_chip_select(s);
+}
+
+static void
+ot_spi_host_device_passthrough_cs_input(void *opaque, int irq, int level)
+{
+    OtSPIHostState *s = opaque;
+    g_assert(irq == 0u);
+
+    if (!ot_spi_host_supports_passthrough(s)) {
+        qemu_log_mask(
+            LOG_GUEST_ERROR,
+            "%s: %s: SPI Host does not support passthrough: more than one CS\n",
+            __func__, s->ot_id);
+        return;
+    }
+
+    if (!s->passthrough_en) {
+        trace_ot_spi_host_passthrough_disabled(s->ot_id);
+    }
+
+    s->passthrough_cs = (bool)level;
+
+    ot_spi_host_update_muxed_chip_select(s);
+}
+
 /* ------------------------------------------------------------------------ */
 /* Device description/instanciation */
 /* ------------------------------------------------------------------------ */
@@ -1347,6 +1459,10 @@ static void ot_spi_host_reset_enter(Object *obj, ResetType type)
 
     s->on_reset = true;
 
+    s->passthrough_en = false;
+    s->passthrough_cs = true;
+    s->host_cs0 = true;
+
     if (!s->clock_src_name) {
         IbexClockSrcIfClass *ic = IBEX_CLOCK_SRC_IF_GET_CLASS(s->clock_src);
         IbexClockSrcIf *ii = IBEX_CLOCK_SRC_IF(s->clock_src);
@@ -1413,6 +1529,11 @@ static void ot_spi_host_instance_init(Object *obj)
                         ARRAY_SIZE(s->irqs));
     ibex_qdev_init_irq(obj, &s->alert, OT_DEVICE_ALERT);
 
+    qdev_init_gpio_in_named(DEVICE(s), &ot_spi_host_device_passthrough_en_input,
+                            OT_SPI_HOST_PASSTHROUGH_EN, 1);
+    qdev_init_gpio_in_named(DEVICE(s), &ot_spi_host_device_passthrough_cs_input,
+                            OT_SPI_HOST_PASSTHROUGH_CS, 1);
+
     s->regs = g_new0(uint32_t, REGS_COUNT);
 
     s->rx_fifo = g_new0(RxFifo, 1u);
@@ -1434,8 +1555,10 @@ static void ot_spi_host_class_init(ObjectClass *klass, void *data)
     dc->realize = ot_spi_host_realize;
     device_class_set_props(dc, ot_spi_host_properties);
 
-    ResettableClass *rc = RESETTABLE_CLASS(klass);
     OtSPIHostClass *sc = OT_SPI_HOST_CLASS(klass);
+    sc->ssi_downstream_transfer = &ot_spi_host_downstream_transfer;
+
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     resettable_class_set_parent_phases(rc, &ot_spi_host_reset_enter, NULL,
                                        &ot_spi_host_reset_exit,
                                        &sc->parent_phases);

hw/opentitan/trace-events

@@ -591,6 +591,7 @@ ot_spi_host_io_read_repeat(const char *id, const char * regname, size_t count) "
 ot_spi_host_io_write(const char *id, uint32_t addr, const char * regname, uint32_t val, uint32_t pc) "%s: addr:0x%02x (%s), val:0x%08x, pc:0x%x"
 ot_spi_host_kick_command(const char *id, unsigned cmdid, bool start) "%s: {%u} start:%u"
 ot_spi_host_new_command(const char *id, unsigned cmdid, const char *dir, const char *spd, uint32_t csid, bool active, unsigned len) "%s: {%u} d:%s s:%s cs#:%u csa:%u len:%u"
+ot_spi_host_passthrough_disabled(const char *id) "%s: passthrough enable is not asserted"
 ot_spi_host_reset(const char *id) "%s"
 ot_spi_host_retire_command(const char *id, unsigned cmdid) "%s: {%u}"
 ot_spi_host_stall(const char *id, const char *msg, uint32_t val) "%s: %s rem %u"

include/hw/opentitan/ot_spi_host.h

@@ -8,6 +8,7 @@
  * Author(s):
  *  Wilfred Mallawa <[email protected]>
  *  Emmanuel Blot <[email protected]>
+ *  Alice Ziuziakowska <[email protected]>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -32,10 +33,34 @@
 #define HW_OPENTITAN_OT_SPI_HOST_H
 
 #include "qom/object.h"
+#include "hw/resettable.h"
+#include "hw/sysbus.h"
 
 #define TYPE_OT_SPI_HOST "ot-spi_host"
 OBJECT_DECLARE_TYPE(OtSPIHostState, OtSPIHostClass, OT_SPI_HOST)
 
+/* this class is only required to manage on-hold reset */
+struct OtSPIHostClass {
+    SysBusDeviceClass parent_class;
+
+    /*
+     * Transfer a byte over this downstream SPI Host's SPI bus.
+     * If Passthrough Enable is not asserted, or the SPI Host supports more
+     * than one Chip Select, the transfer does not take place on the bus and a
+     * default value is returned.
+     *
+     * @tx byte to be transferred
+     * @return received byte from SPI bus, or a default value
+     */
+    uint8_t (*ssi_downstream_transfer)(OtSPIHostState *, uint8_t tx);
+
+    ResettablePhases parent_phases;
+};
+
+/* IRQ lines from upstream OT SPI Device */
+#define OT_SPI_HOST_PASSTHROUGH_EN (TYPE_OT_SPI_HOST "-passthrough-en")
+#define OT_SPI_HOST_PASSTHROUGH_CS (TYPE_OT_SPI_HOST "-passthrough-cs")
+
 /* Supported SPI Host versions */
 typedef enum {
     OT_SPI_HOST_VERSION_EG_1_0_0,