[ot] hw/opentitan: ot_spi_host: create GPIOs & method for Passthrough

See https://opentitan.org/book/hw/ip/spi_host/doc/theory_of_operation.html#pass-through-mode

This commit adds the `passthrough-en` and `passthrough-cs` pins for
controlling Passthrough mode behaviour.

When `passthrough_en` is asserted (i.e, the upstream OT SPI Device is in
Flash Passthrough mode), OT SPI Host is bypassed entirely and OT SPI
Device controls the transfers on the SPI bus.

This passthrough behaviour is only implemented in OT SPI Host if there
is only a single CS pin. See RTL: `spi_host.sv:100`

When in Passthrough mode, OT SPI Device can call into the new method
`downstream_transfer` to perform SPI transfers.

Signed-off-by: Alice Ziuziakowska <[email protected]>

Author: ziuziakowska

hw/opentitan/ot_spi_host.c

@@ -257,6 +257,8 @@ typedef struct {
 } TraceCache;
 #endif /* DISCARD_REPEATED_STATUS_TRACES */
 
+#define SPI_DEFAULT_TX_VALUE ((uint8_t)0xffu)
+
 /* ------------------------------------------------------------------------ */
 /* Types */
 /* ------------------------------------------------------------------------ */
@@ -324,26 +326,22 @@ typedef struct {
     unsigned size;
 } OtSPIHostCmd;
 
-/* this class is only required to manage on-hold reset */
-struct OtSPIHostClass {
-    SysBusDeviceClass parent_class;
-    ResettablePhases parent_phases;
-};
-
 struct OtSPIHostState {
     SysBusDevice parent_obj;
 
     MemoryRegion mmio;
 
     qemu_irq *cs_lines; /* CS output lines */
     SSIBus *ssi; /* SPI bus */
+    bool passthrough_en; /* Upstream SPI Device Passthrough enable line */
 
     uint32_t *regs; /* Registers (except. fifos) */
 
     RxFifo *rx_fifo;
     TxFifo *tx_fifo;
     CmdFifo *cmd_fifo;
 
+
     QEMUTimer *fsm_delay; /* Simulate delayed SPI transfer completion */
 
     IbexIRQ irqs[2u]; /* System bus IRQs */
@@ -829,10 +827,11 @@ static void ot_spi_host_step_fsm(OtSPIHostState *s, const char *cause)
             ot_spi_host_chip_select(s, s->active.cmd.cs, s->fsm.transaction);
         }
 
-        uint8_t tx =
-            write ? (uint8_t)txfifo_pop(s->tx_fifo, length == 1u) : 0xffu;
+        uint8_t tx = write ? (uint8_t)txfifo_pop(s->tx_fifo, length == 1u) :
+                             SPI_DEFAULT_TX_VALUE;
 
-        uint8_t rx = s->fsm.output_en ? ssi_transfer(s->ssi, tx) : 0xffu;
+        uint8_t rx =
+            s->fsm.output_en ? ssi_transfer(s->ssi, tx) : SPI_DEFAULT_TX_VALUE;
 
         if (multi && read && write) {
             /* invalid command, lets corrupt input data */
@@ -1293,6 +1292,61 @@ static void ot_spi_host_io_write(void *opaque, hwaddr addr, uint64_t val64,
     }
 }
 
+static uint8_t ot_spi_host_downstream_transfer(OtSPIHostState *s, uint8_t tx)
+{
+    /* Passthrough is not implemented if SPI Host has more than one CS line */
+    if (s->num_cs != 1) {
+        return SPI_DEFAULT_TX_VALUE;
+    }
+
+    if (!s->passthrough_en) {
+        return SPI_DEFAULT_TX_VALUE;
+    }
+
+    /* Forward to downstream flash */
+    return (uint8_t)ssi_transfer(s->ssi, (uint32_t)tx);
+}
+
+static void
+ot_spi_host_device_passthrough_en_input(void *opaque, int irq, int level)
+{
+    OtSPIHostState *s = opaque;
+    (void)irq;
+
+    /* Passthrough is not implemented if SPI Host has more than one CS line */
+    if (s->num_cs != 1) {
+        return;
+    }
+
+    s->passthrough_en = (bool)level;
+
+    /*
+     * Real HW muxes the CS line based on Passthrough Enable, but it doesn't
+     * make sense for a transfer to be handled by both SPI Host and SPI Device,
+     * so we just deassert CS on any change.
+     */
+    qemu_irq_raise(s->cs_lines[0]);
+}
+
+static void
+ot_spi_host_device_passthrough_cs_input(void *opaque, int irq, int level)
+{
+    OtSPIHostState *s = opaque;
+    (void)irq;
+
+    /* Passthrough is not implemented if SPI Host has more than one CS line */
+    if (s->num_cs != 1) {
+        return;
+    }
+
+    if (!s->passthrough_en) {
+        return;
+    }
+
+    /* Passthrough enabled, SPI Device is driving this CS */
+    qemu_set_irq(s->cs_lines[0], level);
+}
+
 /* ------------------------------------------------------------------------ */
 /* Device description/instanciation */
 /* ------------------------------------------------------------------------ */
@@ -1390,6 +1444,11 @@ static void ot_spi_host_realize(DeviceState *dev, Error **errp)
                              (int)s->num_cs);
     qdev_init_gpio_in_named(DEVICE(s), &ot_spi_host_clock_input, "clock-in", 1);
 
+    qdev_init_gpio_in_named(DEVICE(s), &ot_spi_host_device_passthrough_en_input,
+                            "passthrough-en", 1);
+    qdev_init_gpio_in_named(DEVICE(s), &ot_spi_host_device_passthrough_cs_input,
+                            "passthrough-cs", 1);
+
     char busname[16u];
     if (snprintf(busname, sizeof(busname), "spi%u", s->bus_num) >=
         sizeof(busname)) {

include/hw/opentitan/ot_spi_host.h

@@ -31,11 +31,23 @@
 #ifndef HW_OPENTITAN_OT_SPI_HOST_H
 #define HW_OPENTITAN_OT_SPI_HOST_H
 
+#include "qemu/osdep.h"
 #include "qom/object.h"
+#include "hw/resettable.h"
+#include "hw/sysbus.h"
 
 #define TYPE_OT_SPI_HOST "ot-spi_host"
 OBJECT_DECLARE_TYPE(OtSPIHostState, OtSPIHostClass, OT_SPI_HOST)
 
+/* this class is only required to manage on-hold reset */
+struct OtSPIHostClass {
+    SysBusDeviceClass parent_class;
+
+    uint8_t (*downstream_transfer)(OtSPIHostState *, uint8_t);
+
+    ResettablePhases parent_phases;
+};
+
 /* Supported SPI Host versions */
 typedef enum {
     OT_SPI_HOST_VERSION_EG_1_0_0,