sail_sv_backend: use packed array

In SystemVerilog, unpacked arrays are typically in the form of
`[0:LEN-1]` instead of `[LEN-1:0]` (which is the convention for packed
arrays). In fact, commonly people just use `[LEN]` and this is a
shorthand for `[0:LEN-1]`.

Currently sail_sv_backend always use `[LEN-1:0]` even for unpacked
arrays; this causes the whole array to be flipped even the user passed
in an array declared with `[LEN]`.

Author: nbdd0121

src/sail_sv_backend/jib_sv.ml

@@ -208,7 +208,7 @@ module Make (Config : CONFIG) = struct
         else ksprintf simple_type "logic [%d:0]" (width - 1)
     | CT_ref ctyp -> ksprintf simple_type "sail_reg_%s" (Util.zencode_string (string_of_ctyp ctyp))
     | CT_fvector (len, ctyp) ->
-        let outer_index = sprintf "[%d:0]" (len - 1) in
+        let outer_index = sprintf "[%d]" len in
         begin
           match sv_ctyp ~two_state ctyp with
           | ty, Some inner_index -> (ty, Some (inner_index ^ outer_index))