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HyperRAM test software
- performance test; memory-to-memory copy using bursts. - write tests; specialised implementations of `memset`-like memory initialisation code to exercise the write coalescing logic of the HyperRAM controller interface. - alignment tests; exercise all possible alignments of source and destination addresses, to check the behaviour of wrapping read bursts and coalsced linear write bursts. - buffering test, issuing pseudo-random write traffic into a destination buffer with known content.
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‎sw/cheri/checks/CMakeLists.txt‎

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@@ -51,9 +51,9 @@ add_custom_command(
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install(TARGETS ${NAME})
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set(NAME hyperram_test)
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add_executable(${NAME} hyperram_test.cc)
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add_executable(${NAME} hyperram_test.cc hyperram_memset.S)
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target_include_directories(${NAME} PRIVATE ${CHERIOT_SDK_INCLUDES} "${reisfmt_SOURCE_DIR}/include")
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target_link_libraries(${NAME} common)
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target_link_libraries(${NAME} common block_tests)
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add_custom_command(
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TARGET ${NAME} POST_BUILD

‎sw/cheri/checks/hyperram_memset.S‎

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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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// A set of memory initialisation functions using different access sizes, to check that
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// the write transactions are properly coalesced into write bursts to the HyperBus
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// Memory Controller.
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//
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// Each routine is expected to be writing a single, defined byte to each address that is
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// modified. By initialising the entirety of a target buffer to a different value first,
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// the set of modified addresses may be ascertained.
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.section .text, "ax", @progbits
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.option norvc
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// Byte-based memory writing.
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//
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// entry ca0 -> byte-aligned destination buffer
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// a1 = byte to be stored
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// a2 = number of bytes
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// exit -
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.globl hyperram_memset_b
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.p2align 5
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hyperram_memset_b:
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addi a2, a2, -8
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bltz a2, memset_b_8fix
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memset_b_8:
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csb a1, (ca0)
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csb a1, 1(ca0)
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csb a1, 2(ca0)
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csb a1, 3(ca0)
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csb a1, 4(ca0)
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csb a1, 5(ca0)
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csb a1, 6(ca0)
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csb a1, 7(ca0)
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cincoffset ca0, ca0, 8
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addi a2, a2, -8
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bgez a2, memset_b_8
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memset_b_8fix:
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addi a2, a2, 8
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bgtz a2, memset_b_tail
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cret
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// Just complete the request using byte stores; this is shared among all _ascending_ routines.
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// Performance is not very important, but it would be better to keep the byte writes temporally
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// close together to try to provoke races.
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//
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// ca0 -> byte-aligned pointer into destination buffer
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// a1 = byte to be stored
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// a2 = non-zero count of bytes remaining
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memset_b_tail:
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add a2, a0, a2
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memset_b_1:
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csb a1, (ca0)
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cincoffset ca0, ca0, 1
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bltu a0, a2, memset_b_1
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cret
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// Descending transfer, pre-decrementing address; shared among the two _descending_ routines.
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//
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// ca0 -> just beyond next address to be written, decrement before use.
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// a1 = byte to be stored
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// a2 = non-zero count of bytes remaining
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memset_b_desc_tail:
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sub a2, a0, a2
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memset_b_desc_1:
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csb a1, -1(ca0)
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cincoffset ca0, ca0, -1
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bgtu a0, a2, memset_b_desc_1
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cret
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// Byte and half word-based memory writing; each word is written using
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// 2 byte stores and a half-word store.
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//
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// entry ca0 -> word-aligned destination buffer
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// a1 = byte to be stored, replicated throughout word
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// a2 = number of bytes
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// exit -
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.globl hyperram_memset_hb
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.p2align 5
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hyperram_memset_hb:
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addi a2, a2, -4
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bltz a2, memset_hb_4fix
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memset_hb_4:
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csb a1, (ca0)
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csb a1, 1(ca0)
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csh a1, 2(ca0)
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cincoffset ca0, ca0, 4
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addi a2, a2, -4
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bgez a2, memset_hb_4
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memset_hb_4fix:
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addi a2, a2, 4
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bgtz a2, memset_b_tail
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cret
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// Half word-based memory writing.
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//
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// entry ca0 -> half-word aligned destination buffer
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// a1 = byte to be stored, replicated throughout half-word
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// a2 = number of bytes
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// exit -
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.globl hyperram_memset_h
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.p2align 5
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hyperram_memset_h:
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addi a2, a2, -16
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bltz a2, memset_h_16fix
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memset_h_16:
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csh a1, (ca0)
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csh a1, 2(ca0)
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csh a1, 4(ca0)
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csh a1, 6(ca0)
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csh a1, 8(ca0)
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csh a1, 10(ca0)
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csh a1, 12(ca0)
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csh a1, 14(ca0)
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cincoffset ca0, ca0, 16
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addi a2, a2, -16
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bgez a2, memset_h_16
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memset_h_16fix:
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addi a2, a2, 16
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bgtz a2, memset_b_tail
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cret
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// Word-based memory writing.
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//
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// entry ca0 -> word-aligned destination buffer
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// a1 = byte to be stored, replicated throughout word
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// a2 = number of bytes
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.globl hyperram_memset_w
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.p2align 5
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hyperram_memset_w:
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addi a2, a2, -32
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bltz a2, memset_w_32fix
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memset_w_32:
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csw a1, (ca0)
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csw a1, 4(ca0)
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csw a1, 8(ca0)
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csw a1, 12(ca0)
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csw a1, 16(ca0)
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csw a1, 20(ca0)
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csw a1, 24(ca0)
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csw a1, 28(ca0)
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cincoffset ca0, ca0, 32
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addi a2, a2, -32
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bgez a2, memset_w_32
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memset_w_32fix:
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addi a2, a2, 32
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bgtz a2, memset_b_tail
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cret
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// Repeated words memory writing; the performance of this code is of no consequence.
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// It is concerned purely with ensuring the correctness of the written data.
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//
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// entry ca0 -> word-aligned destination buffer
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// a1 = byte to be stored, replicated throughout word
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// a2 = number of bytes
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.globl hyperram_memset_wr
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.p2align 5
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hyperram_memset_wr:
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addi a2, a2, -4
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bltz a2, memset_wr_4fix
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xori a3, a1, -1
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memset_wr_4:
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csw a3, (ca0) // This word should be overwritten...
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csw a1, (ca0) // ...by the original value.
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cincoffset ca0, ca0, 4
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addi a2, a2, -4
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bgez a2, memset_wr_4
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memset_wr_4fix:
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addi a2, a2, 4
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bgtz a2, memset_b_tail
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cret
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// Word-based memory writing to descending addresses.
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//
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// entry ca0 -> word-aligned end of destination buffer, exclusive
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// a1 = byte to be stored, replicated throughout word
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// a2 = number of bytes
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.globl hyperram_memset_wd
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.p2align 5
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hyperram_memset_wd:
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addi a2, a2, -8
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bltz a2, memset_wd_8fix
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memset_wd_8:
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csw a1, -4(ca0)
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csw a1, -8(ca0)
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cincoffset ca0, ca0, -8
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addi a2, a2, -8
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bgez a2, memset_wd_8
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memset_wd_8fix:
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addi a2, a2, 8
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bgtz a2, memset_b_desc_tail
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cret
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// Capability stores to ascending addresses.
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//
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// These are issued as two back-to-back word writes and we're just using
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// this as a way to issue 64-bit writes rather than trying to create
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// sensible/valid capabilities.
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//
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// entry ca0 -> double-word aligned destination buffer
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// a1 = byte to be stored, replicated throughout word
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// a2 = number of bytes
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.globl hyperram_memset_c
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.p2align 5
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hyperram_memset_c:
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// Replicate the data word to yield a double word.
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cincoffset csp, csp, -8
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csw a1, (csp)
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csw a1, 4(csp)
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clc ca1,(csp)
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cincoffset csp, csp, 8
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addi a2, a2, -8
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bltz a2, memset_c_8fix
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memset_c_8:
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csc ca1, (ca0)
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cincoffset ca0, ca0, 8
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addi a2, a2, -8
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bgez a2, memset_c_8
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memset_c_8fix:
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addi a2, a2, 8
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bgtz a2, memset_b_tail
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cret
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// Capability stores to descending addresses. See above.
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//
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// entry ca0 -> double-word aligned end of destination buffer, exclusive
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// a1 = byte to be stored, replicated throughout word
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// a2 = number of bytes
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.globl hyperram_memset_cd
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.p2align 5
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hyperram_memset_cd:
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// Replicate the data word to yield a double word.
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cincoffset csp, csp, -8
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csw a1, (csp)
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csw a1, 4(csp)
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clc ca1, (csp)
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cincoffset csp, csp, 8
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addi a2, a2, -8
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bltz a2, memset_cd_8fix
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memset_cd_8:
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csc ca1, -8(ca0)
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cincoffset ca0, ca0, -8
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addi a2, a2, -8
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bgez a2, memset_cd_8
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memset_cd_8fix:
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addi a2, a2, 8
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bgtz a2, memset_b_desc_tail
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cret
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‎sw/cheri/checks/hyperram_memset.h‎

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/**
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* Copyright lowRISC contributors.
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* Licensed under the Apache License, Version 2.0, see LICENSE for details.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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enum WriteTestType {
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WriteTestType_B = 0,
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WriteTestType_H,
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WriteTestType_HB,
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WriteTestType_W,
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WriteTestType_WR,
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WriteTestType_WD,
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WriteTestType_C,
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WriteTestType_CD
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};
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// Memory-writing routines; these all mimic the ISO C function `memset` except that they have
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// a constraint of 'natural alignment' upon the buffer address and have very specific
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// implementations to ensure defined traffic for testing the write coalescing/buffering logic
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// of the HyperRAM controller interface.
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extern "C" void hyperram_memset_b(volatile uint8_t *dst, int c, size_t n);
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extern "C" void hyperram_memset_h(volatile uint16_t *dst, int c, size_t n);
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extern "C" void hyperram_memset_hb(volatile uint16_t *dst, int c, size_t n);
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extern "C" void hyperram_memset_w(volatile uint32_t *dst, int c, size_t n);
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extern "C" void hyperram_memset_wr(volatile uint32_t *dst, int c, size_t n);
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extern "C" void hyperram_memset_wd(volatile uint32_t *dst, int c, size_t n);
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extern "C" void hyperram_memset_c(volatile uint64_t *dst, int c, size_t n);
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extern "C" void hyperram_memset_cd(volatile uint64_t *dst, int c, size_t n);

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