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Reduce access latency of GPIO blocks
Rework the `gpio_core` to provide response data in the same cycle as the request to reduce the access latency. Reduce the value of the `AccessLatency` parameter of the TL-UL adapter used to connect the GPIO blocks to the system bus, to match the `gpio_core` read latency changes.
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2 files changed

+4
-6
lines changed

2 files changed

+4
-6
lines changed

rtl/ip/gpio/rtl/gpio.sv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ module gpio #(
6767
);
6868

6969
tlul_adapter_reg #(
70-
.AccessLatency ( 1 ),
70+
.AccessLatency ( 0 ),
7171
.RegAw ( RegAddrWidth )
7272
) gpio_device_adapter (
7373
.clk_i,

rtl/ip/gpio/rtl/gpio_core.sv

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -115,13 +115,11 @@ module gpio_core #(
115115
if (!rst_ni) begin
116116
gp_o <= '0;
117117
gp_o_en <= '0;
118-
device_rvalid_o <= '0;
119118
pcint_mask <= '0;
120119
pcint_enable <= '0;
121120
pcint_mode <= '0;
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pcint_i_sel <= '0;
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pcint_status <= '0;
124-
rd_reg_idx <= '0;
125123
end else begin
126124
gp_o <= (gp_o_sel && device_we_i) ? gp_o_d : gp_o;
127125
gp_o_en <= (gp_o_en_sel && device_we_i) ? gp_o_en_d : gp_o_en;
@@ -138,12 +136,12 @@ module gpio_core #(
138136
end else begin
139137
pcint_status <= pcint_status;
140138
end
141-
142-
device_rvalid_o <= device_req_i && !device_we_i;
143-
rd_reg_idx <= reg_addr[RegAddr-1:2];
144139
end
145140
end
146141

142+
assign device_rvalid_o = device_req_i && !device_we_i;
143+
assign rd_reg_idx = reg_addr[RegAddr-1:2];
144+
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logic [3:0] unused_o_device_be;
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logic [3:0] unused_i_device_be;
149147

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