PWM restructuring and resource reduction

alees24 · alees24 · commit 2dacd2ca3c50 · 2025-06-24T13:55:15.000+01:00
Migrate the tlul_adapter_reg into the pwm_wrapper itself to
clean the sonata_system top-level.
Migrate the PWM logic into an ip folder of its own.
Simplify the address decoding and the read data path
(never used).

Reduce the AccessLatency to zero because the PWM has never
required a cycle of access latency anyway; it only supports
writes. If reads are added later, the read data path should just
be expressed combinationally without a register delay, since
there is a register delay in the tlul_adapter_reg anyway.
diff --git a/rtl/ip/pwm/pwm.core b/rtl/ip/pwm/pwm.core
@@ -0,0 +1,21 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:pwm:0.1"
+description: "PWM"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:mubi
+      - lowrisc:tlul:adapter_reg
+    files:
+      - rtl/pwm.sv
+      - rtl/pwm_wrapper.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default_target
+    filesets:
+      - files_rtl
+    toplevel: pwm_wrapper
diff --git a/rtl/ip/pwm/rtl/pwm.sv b/rtl/ip/pwm/rtl/pwm.sv
diff --git a/rtl/ip/pwm/rtl/pwm_wrapper.sv b/rtl/ip/pwm/rtl/pwm_wrapper.sv
@@ -0,0 +1,109 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This wrapper instantiates a series of PWMs and distributes requests from the device bus.
+module pwm_wrapper #(
+  parameter int unsigned PwmWidth   = 12,
+  parameter int unsigned PwmCtrSize = 8,
+  parameter int unsigned DataWidth  = 32,
+  parameter int unsigned RegAddrWidth = 12
+) (
+  input  logic clk_i,
+  input  logic rst_ni,
+
+  // TileLink interface to registers.
+  input  tlul_pkg::tl_h2d_t tl_i,
+  output tlul_pkg::tl_d2h_t tl_o,
+
+  // Collected output of all PWMs.
+  output logic [PwmWidth-1:0] pwm_o
+);
+
+  localparam int unsigned PwmIdxOffset = $clog2(DataWidth / 8) + 1;
+  localparam int unsigned PwmIdxWidth = RegAddrWidth - PwmIdxOffset;
+
+  // IO for device bus.
+  logic [RegAddrWidth-1:0] device_addr;
+  logic                    device_we;
+  logic [DataWidth/8-1:0]  device_be;
+  logic [DataWidth-1:0]    device_wdata;
+  logic [DataWidth-1:0]    device_rdata;
+
+  tlul_adapter_reg #(
+    .AccessLatency ( 0            ),
+    .RegAw         ( RegAddrWidth )
+  ) pwm_device_adapter (
+    .clk_i        (clk_i),
+    .rst_ni       (rst_ni),
+
+    // TL-UL interface.
+    .tl_i         (tl_i),
+    .tl_o         (tl_o),
+
+    // Control interface.
+    .en_ifetch_i  (prim_mubi_pkg::MuBi4False),
+    .intg_error_o (),
+
+    // Register interface.
+    .re_o         (),  // Not readable.
+    .we_o         (device_we),
+    .addr_o       (device_addr),
+    .wdata_o      (device_wdata),
+    .be_o         (device_be),
+    .busy_i       ('0),
+    .rdata_i      (device_rdata),
+    .error_i      ('0)
+  );
+
+  // Generate PwmWidth number of PWMs.
+  for (genvar i = 0; i < PwmWidth; i++) begin : gen_pwm
+    logic [PwmCtrSize-1:0] data_d;
+    logic [PwmCtrSize-1:0] counter_q;
+    logic [PwmCtrSize-1:0] pulse_width_q;
+    logic counter_en;
+    logic pulse_width_en;
+    logic [PwmIdxWidth-1:0] pwm_idx;
+
+    assign pwm_idx = i;
+
+    // Byte enables are currently unsupported for PWM.
+    assign data_d         = device_wdata[PwmCtrSize-1:0]; // Only take PwmCtrSize LSBs.
+    // Each PWM has a 64-bit block. The most significant 32 bits are the counter and the least
+    // significant 32 bits are the pulse width.
+    assign counter_en     = device_we & (device_addr[RegAddrWidth-1:PwmIdxOffset] == pwm_idx)
+                                      & device_addr[PwmIdxOffset-1];
+    assign pulse_width_en = device_we & (device_addr[RegAddrWidth-1:PwmIdxOffset] == pwm_idx)
+                                      & ~device_addr[PwmIdxOffset-1];
+
+    always @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+        counter_q       <= '0;
+        pulse_width_q   <= '0;
+      end else begin
+        if (counter_en) begin
+          counter_q     <= data_d;
+        end
+        if (pulse_width_en) begin
+          pulse_width_q <= data_d;
+        end
+      end
+    end
+    pwm #(
+      .CtrSize( PwmCtrSize )
+    ) u_pwm (
+      .clk_i        (clk_i),
+      .rst_ni       (rst_ni),
+      .pulse_width_i(pulse_width_q),
+      .max_counter_i(counter_q),
+      .modulated_o  (pwm_o[i])
+    );
+  end : gen_pwm
+
+  // Generating the device bus output.
+  // TODO: Reading from PWM currently not possible.
+  assign device_rdata = '0;
+
+  logic _unused;
+  assign _unused = ^{device_be, device_wdata};
+endmodule
diff --git a/rtl/system/pwm_wrapper.sv b/rtl/system/pwm_wrapper.sv
diff --git a/rtl/system/sonata_system.sv b/rtl/system/sonata_system.sv
@@ -123,7 +123,6 @@ module sonata_system
   localparam int unsigned BusAddrWidth  = 32;
   localparam int unsigned BusByteEnable = 4;
   localparam int unsigned BusDataWidth  = 32;
-  localparam int unsigned PRegAddrWidth = 8;  // PWM uses only 8 bits of addressing.
   localparam int unsigned DRegAddrWidth = 12; // Debug module uses 12 bits of addressing.
   localparam int unsigned TRegAddrWidth = 16; // Timer uses more address bits.
   localparam int unsigned GRegAddrWidth = 9; // GPIO array uses 9 bits of addressing.
@@ -147,13 +146,12 @@ module sonata_system
   } bus_host_e;
 
   typedef enum int {
-    Pwm,
     Timer,
     RevTags,
     DbgDev
   } bus_device_e;
 
-  localparam int NrDevices = 4;
+  localparam int NrDevices = 3;
   localparam int NrHosts = 2;
 
   // Signals for hardware revoker
@@ -257,7 +255,6 @@ module sonata_system
   logic                     device_err   [NrDevices];
 
   // Generate requests from read and write enables.
-  assign device_req[Pwm]      = device_re[Pwm]      | device_we[Pwm];
   assign device_req[Timer]    = device_re[Timer]    | device_we[Timer];
   assign device_req[DbgDev]   = device_re[DbgDev]   | device_we[DbgDev];
 
@@ -284,9 +281,6 @@ module sonata_system
 
   logic debug_req;
 
-  // Tie-off unused error signals.
-  assign device_err[Pwm]      = 1'b0;
-
   //////////////////////////////////////////////
   // Instantiate TL-UL crossbar and adapters. //
   //////////////////////////////////////////////
@@ -623,34 +617,6 @@ module sonata_system
   // Set upper bits of address.
   assign device_addr[DbgDev][BusAddrWidth-1:DRegAddrWidth] = tl_ifetch_pkg::ADDR_SPACE_DBG_DEV[BusAddrWidth-1:DRegAddrWidth];
 
-  tlul_adapter_reg #(
-    .AccessLatency    ( 1 )
-  ) pwm_device_adapter (
-    .clk_i        (clk_sys_i),
-    .rst_ni       (rst_sys_ni),
-
-    // TL-UL interface.
-    .tl_i         (tl_pwm_h2d),
-    .tl_o         (tl_pwm_d2h),
-
-    // Control interface.
-    .en_ifetch_i  (prim_mubi_pkg::MuBi4False),
-    .intg_error_o (),
-
-    // Register interface.
-    .re_o         (device_re[Pwm]),
-    .we_o         (device_we[Pwm]),
-    .addr_o       (device_addr[Pwm][PRegAddrWidth-1:0]),
-    .wdata_o      (device_wdata[Pwm]),
-    .be_o         (device_be[Pwm]),
-    .busy_i       ('0),
-    .rdata_i      (device_rdata[Pwm]),
-    .error_i      (device_err[Pwm])
-  );
-
-  // Tie off upper bits of address.
-  assign device_addr[Pwm][BusAddrWidth-1:PRegAddrWidth] = '0;
-
   tlul_adapter_reg #(
     .RegAw            ( TRegAddrWidth ),
     .AccessLatency    ( 1             )
@@ -976,18 +942,13 @@ module sonata_system
     .PwmWidth   ( PWM_OUT_WIDTH ),
     .PwmCtrSize ( PwmCtrSize )
   ) u_pwm (
-    .clk_i           (clk_sys_i),
-    .rst_ni          (rst_sys_ni),
+    .clk_i  (clk_sys_i),
+    .rst_ni (rst_sys_ni),
 
-    .device_req_i    (device_req[Pwm]),
-    .device_addr_i   (device_addr[Pwm]),
-    .device_we_i     (device_we[Pwm]),
-    .device_be_i     (device_be[Pwm]),
-    .device_wdata_i  (device_wdata[Pwm]),
-    .device_rvalid_o (device_rvalid[Pwm]),
-    .device_rdata_o  (device_rdata[Pwm]),
+    .tl_i   (tl_pwm_h2d),
+    .tl_o   (tl_pwm_d2h),
 
-    .pwm_o (pwm_modulated)
+    .pwm_o  (pwm_modulated)
   );
 
   // UARTs
diff --git a/sonata_system.core b/sonata_system.core
@@ -17,6 +17,7 @@ filesets:
       - lowrisc:ip:xbar_ifetch
       - lowrisc:ip:spi
       - lowrisc:ip:gpio
+      - lowrisc:ip:pwm
       - lowrisc:ip:rev_ctl
       - lowrisc:ip:rgbled_ctrl
       - lowrisc:ip:hyperram
@@ -34,8 +35,6 @@ filesets:
       - rtl/system/dm_top.sv
       - rtl/system/debounce.sv
       - rtl/system/pinmux.sv
-      - rtl/system/pwm.sv
-      - rtl/system/pwm_wrapper.sv
       - rtl/system/pwm_fade.sv
       - rtl/system/sram.sv
       - rtl/system/rst_sync.sv
