Add Sonata One-compatible Sonata XL build target

Add Sonata XL bitstream build target that maintains
software compatibility with the Sonata One board.
Tweaks the design using `ifdef` statements and alternative XDC files.
Uses the extra block RAM of the Sonata XL FPGA to create a faux-HyperRAM
(1 MiB only) so that the memory map can be kept the same.
Does not yet make use of the extra board-to-board connectors
present only on the XL board.

Change the fusesoc target from `synth` to `synth_xl` to build.

Author: elliotb-lowrisc

data/synth_timing.xdc

@@ -0,0 +1,32 @@
+## Copyright lowRISC contributors.
+## Licensed under the Apache License, Version 2.0, see LICENSE for details.
+## SPDX-License-Identifier: Apache-2.0
+
+# Sonata XL-specific, to be sourced after synth_timing_common.xdc
+
+# This file is for timing constraints to be applied *before* synthesis.
+# i.e. timing constraints on top-level ports.
+#
+# See UG949 and UG903 for information on setting various timing constraints.
+
+#### Recommended timing constraints sequence from UG949 ####
+## Timing Assertions Section
+# Primary clocks
+# Virtual clocks
+# Generated clocks
+# Delay for external MMCM/PLL feedback loop
+# Clock Uncertainty and Jitter
+# Input and output delay constraints
+# Clock Groups and Clock False Paths
+## Timing Exceptions Section
+# False Paths
+# Max Delay / Min Delay
+# Multicycle Paths
+# Case Analysis
+# Disable Timing
+
+### Clock Groups and Clock False Paths ###
+# JTAG tck is completely asynchronous to FPGA mainClk and
+# internal clocks generated from it (and thus synchronous with it).
+# No HyperRAM on Sonata XL, so exclude HyperRAM clocks.
+set_clock_groups -asynchronous -group tck -group {mainClk clk_sys clk_usb}

data/synth_timing_common.xdc

@@ -32,3 +32,20 @@ Optionally, the bitstream can be built using a nix command:
 nix run .#bitstream-build
 ```
 Note: Vivado must be in one's path for this command to work.
+
+## Sonata XL bitstream
+
+To build a bitstream for the Sonata XL board instead of the Sonata One board, change the fusesoc target from `synth` to `synth_xl`.
+i.e. run this command:
+
+```sh
+fusesoc --cores-root=. run --target=synth_xl --setup --build lowrisc:sonata:system
+```
+
+The resulting Sonata XL bitstream should be broadly compatible with software compiled for the Sonata One board.
+Compatibility is key, given the present lack of a software target for Sonata XL.
+Excluding HyperRAM and a couple of minor details, Sonata XL is a superset of Sonata One.
+A faux-HyperRAM is instantiated using the additional block RAM of the larger FPGA to account for the lack of HyperRAM onboard.
+The faux-HyperRAM is mounted at the same memory location as the real HyperRAM would be, providing software compatibility.
+It has the added benefit of being faster, which may aid some programs.
+Currently there is no way to use the additional board-to-board connectors provided by the Sonata XL board.

data/synth_timing_xl.xdc

@@ -35,6 +35,10 @@ module top_sonata
   output logic       ethmac_cs,
 
   output logic       rgbled0,
+`ifdef TARGET_XL_BOARD
+  // Sonata XL can turn off the RGB LEDs entirely
+  output logic       rgbled_en,
+`endif
 
   // UART 0
   output logic       ser0_tx,
@@ -192,12 +196,23 @@ module top_sonata
   output logic       microsd_cmd,  // SPI mode: COPI
   input  logic       microsd_det,  // Card insertion detection
 
+  // HyperRAM interface
+`ifdef TARGET_XL_BOARD
+  // No HyperRAM on Sonata XL
+`else
   inout  wire [7:0]  hyperram_dq,
   inout  wire        hyperram_rwds,
   output wire        hyperram_ckp,
   output wire        hyperram_ckn,
   output wire        hyperram_nrst,
   output wire        hyperram_cs
+`endif
+
+`ifdef TARGET_XL_BOARD
+  // Sonata XL-only expansion headers
+  inout  logic [63:0] ex0,
+  inout  logic [63:0] ex1
+`endif
 );
   import sonata_pkg::*;
 
@@ -282,10 +297,14 @@ module top_sonata
     .rst_usb_ni     (rst_usb_n),
 
     // HyperRAM clocks and reset
+`ifdef TARGET_XL_BOARD
+    // No HyperRAM on Sonata XL
+`else
     .clk_hr_i       (clk_hr),
     .clk_hr90p_i    (clk_hr90p),
     .clk_hr3x_i     (clk_hr3x),
     .rst_hr_ni      (rst_hr_n),
+`endif
 
     // GPIO
     .gp_i           ({
@@ -354,12 +373,17 @@ module top_sonata
 
     .rgbled_dout_o(rgbled_dout),
 
+    // HyperRAM
+`ifdef TARGET_XL_BOARD
+    // No HyperRAM on Sonata XL
+`else
     .hyperram_dq,
     .hyperram_rwds,
     .hyperram_ckp,
     .hyperram_ckn,
     .hyperram_nrst,
     .hyperram_cs,
+`endif
 
     .rs485_tx_enable_o(rs485_tx_enable),
     .rs485_rx_enable_o(rs485_rx_enable),
@@ -372,6 +396,10 @@ module top_sonata
   );
 
   assign rgbled0 = ~rgbled_dout;
+`ifdef TARGET_XL_BOARD
+  // Leave RGBs always on, like Sonata One, until we can do something better
+  assign rgbled_en = 1'b1;
+`endif
 
   // Tie flash wp_n and hold_n to 1 as they're active low and we don't need either signal
   assign appspi_d2 = 1'b1;

doc/dev/fpga-development.md

@@ -23,10 +23,14 @@ module sonata_system
   input logic                      rst_usb_ni,
 
   // HyperRAM clocks and reset
+`ifdef TARGET_XL_BOARD
+  // No HyperRAM on Sonata XL
+`else
   input logic                      clk_hr_i,
   input logic                      clk_hr90p_i,
   input logic                      clk_hr3x_i,
   input logic                      rst_hr_ni,
+`endif
 
   // General purpose input and output
   input  logic [GPIO_IOS_WIDTH-1:0] gp_i,
@@ -87,12 +91,16 @@ module sonata_system
 
   output logic                     rgbled_dout_o,
 
+`ifdef TARGET_XL_BOARD
+  // No HyperRAM on Sonata XL
+`else
   inout  wire [7:0]                hyperram_dq,
   inout  wire                      hyperram_rwds,
   output wire                      hyperram_ckp,
   output wire                      hyperram_ckn,
   output wire                      hyperram_nrst,
   output wire                      hyperram_cs,
+`endif
 
   output wire                      rs485_rx_enable_o,
   output wire                      rs485_tx_enable_o,
@@ -494,6 +502,24 @@ module sonata_system
     .tl_b_o (tl_sram_b_d2h)
   );
 
+  // HyperRAM
+`ifdef TARGET_XL_BOARD
+  // No HyperRAM on Sonata XL, but we can replace it with internal block RAM
+  sram #(
+    .AddrWidth       ( $clog2(HyperRAMSize) ),
+    .DataWidth       ( BusDataWidth    ),
+    .DataBitsPerMask ( DataBitsPerMask ),
+    .InitFile        ()
+  ) u_hyperram (
+    .clk_i  (clk_sys_i),
+    .rst_ni (rst_sys_ni),
+
+    .tl_a_i (tl_hyperram_ds_h2d),
+    .tl_a_o (tl_hyperram_ds_d2h),
+    .tl_b_i (),
+    .tl_b_o ()
+  );
+`else
   hyperram #(
     .HyperRAMClkFreq ( HyperRAMClkFreq ),
     .HyperRAMSize    ( HyperRAMSize    )
@@ -516,6 +542,7 @@ module sonata_system
     .hyperram_nrst,
     .hyperram_cs
   );
+`endif
 
   // Manual M:1 socket instantiation as xbar generator cannot deal with multiple ports for one
   // device and we want to utilize the dual port SRAM. So totally separate crossbars are generated

rtl/fpga/top_sonata.sv

@@ -63,9 +63,14 @@ filesets:
   files_constraints_sonata:
     files:
       # Per AMD advice (UG949):
-      - data/pins_sonata.xdc  # 1 file for physical +
-      - data/synth_timing.xdc # 1 file for timing (synthesis) +
-      - data/impl_timing.xdc  # 1 file for timing (implementation)
+      #   1 file for physical + 1 file for timing (synthesis) + 1 file for timing (implementation)
+      # Complicated by the differences between Sonata One and Sonata XL
+      - target_synth    ? (data/pins_sonata.xdc)
+      - target_synth_xl ? (data/pins_sonata_xl.xdc)
+      -                    data/synth_timing_common.xdc
+      - target_synth    ? (data/synth_timing.xdc)
+      - target_synth_xl ? (data/synth_timing_xl.xdc)
+      -                    data/impl_timing.xdc
     file_type: xdc
 
   files_tcl:
@@ -98,6 +103,11 @@ parameters:
     paramtype: vlogdefine
     description: Use an SRAM simulation model rather than the real hyperram controller
 
+  TARGET_XL_BOARD:
+    datatype: bool
+    paramtype: vlogdefine
+    description: Targeting the Sonata XL board rather than the Sonata One board.
+
 targets:
   default: &default_target
     filesets:
@@ -118,6 +128,22 @@ targets:
       - SRAMInitFile
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
 
+  synth_xl:
+    <<: *default_target
+    default_tool: vivado
+    filesets_append:
+      - files_sonata
+      - files_constraints_sonata
+      - files_tcl
+    toplevel: top_sonata
+    tools:
+      vivado:
+        part: "xc7a200tfbg676-2" # Artix-7 200T
+    parameters:
+      - SRAMInitFile
+      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
+      - TARGET_XL_BOARD=true
+
   sim:
     <<: *default_target
     default_tool: verilator