[tool] Refactor the topgen tooling to use the rdl files

From this commit the source of truth for the registers offsets is
replaced from the data/config.toml file to the data/top.rdl file.

Signed-off-by: Douglas Reis <[email protected]>

Author: engdoreis

data/top_config.toml

@@ -1,60 +1,3 @@
-[[blocks]]
-name = "gpio"
-instances = 6 # RPi, Ard, Pmod0, Pmod1, PmodC
-ios = [
-  {
-    name = "ios",
-    type = "inout",
-    combine = "mux",
-    length = 32
-  },
-]
-memory_start = 0x80000000
-memory_size  = 0x00000040
-xbar = { pipeline = "true"}
-
-[[blocks]]
-name = "pwm"
-instances = 1
-ios = [{ name = "out", type = "output", length = 7 }]
-memory_start = 0x80001000
-memory_size  = 0x00001000
-xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
-
-[[blocks]]
-name = "uart"
-instances = 3
-ios = [
-  { name = "rx", type = "input", default = 1 },
-  { name = "tx", type = "output" },
-]
-memory_start = 0x80100000
-memory_size  = 0x00001000
-xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
-
-[[blocks]]
-name = "i2c"
-instances = 2
-ios = [
-  { name = "scl", type = "inout", combine = "and" },
-  { name = "sda", type = "inout", combine = "and" },
-]
-memory_start = 0x80200000
-memory_size  = 0x00001000
-xbar = { pipeline = "true", req_fifo_pass = "false", rsp_fifo_pass = "false" }
-
-[[blocks]]
-name = "spi"
-instances = 3
-ios = [
-  { name = "cipo", type = "input", default = 0 },
-  { name = "copi", type = "output" },
-  { name = "sclk", type = "output" },
-  { name = "cs", type = "output", length = 4 },
-]
-memory_start = 0x80302000
-memory_size  = 0x00001000
-
 # UARTS
 [[pins]]
 name = "ser0_tx"