I2C documentation discrepancy

[djlowther]

The information in https://lowrisc.github.io/sonata-system/doc/ip/i2c.html does not accurately reflect the I2C implementation used in this repository.

There is a link to the OpenTitan documentation, but the documentation linked to describes a more recent version of the OpenTitan I2C IP. The actual implementation in this repository appears to come from somewhere around commit 02e36dfabcde185bec3fbe7 in the OpenTitan repository which has a slightly different register interface, particularly in how the NACK'd writes can be detected.

Also, the documentation says that registers 0x00 - 0x10 are not accessible, which is incorrect. We have been able to read meaningful values from register 0x00 (INTR_STATE) (and in fact, it seems to be the only way to detect NACKs in this particular version, since CONTROLLER_EVENTS doesn't exist.

[marnovandermaas]

Thanks for raising this. You're right, the OpenTitan IP block has seen quite a few updates recently. It's probably worth integrating the new IP from upstream to not have to maintain the old version of the documentation here.

[HU90m]

For the time being, the old I²C is pretty well documented in https://github.com/microsoft/cheriot-rtos/blob/main/sdk/include/platform/sunburst/platform-i2c.hh