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commit 3fd91bed8c2fc78c82d5d700ecf47707e2ec2688 Author: Andrew Kay <git@ajk.me> Date: Wed Aug 20 20:10:17 2025 -0500 fix flags commit 01690730752c12c898458948f81e1bc062dd2258 Author: Andrew Kay <git@ajk.me> Date: Wed Aug 20 19:58:28 2025 -0500 x commit 59f703c8f81e4e81f405dd88aab628dd79ef3698 Author: Andrew Kay <git@ajk.me> Date: Wed Aug 20 19:23:45 2025 -0500 change it again commit dad3d3e36c916a1001ea2be07e1b6f1a05158557 Author: Andrew Kay <git@ajk.me> Date: Wed Aug 20 16:48:31 2025 -0500 cleanup commit 4726d3021865e1f63bcd22d8979d558f4b7d84bb Author: Andrew Kay <git@ajk.me> Date: Wed Aug 20 08:04:25 2025 -0500 update test_mock commit 3d71bf136136c6351dfdb9db9c8becc29e7a9681 Author: Andrew Kay <git@ajk.me> Date: Wed Aug 20 07:56:03 2025 -0500 wip commit 3b53d1b8e5e20edcd1e942f3f30e5248a45209c3 Author: Andrew Kay <git@ajk.me> Date: Tue Aug 19 08:36:09 2025 -0500 remove flags unreferenced commit 6ac1abd997679588cead576780f18e391e90eae5 Author: Andrew Kay <git@ajk.me> Date: Mon Aug 18 18:40:59 2025 -0500 wip commit 02e92420d6b7fc2173f692f5a4ec42736120e3dc Author: Andrew Kay <git@ajk.me> Date: Mon Aug 18 07:45:38 2025 -0500 x commit 8585ed9d41e2f501f5064467c8f4f3bbe686fb1c Author: Andrew Kay <git@ajk.me> Date: Mon Aug 18 07:32:32 2025 -0500 x commit 1f34e40c809e792807160e7b120af29d9718f4a9 Author: Andrew Kay <git@ajk.me> Date: Sat Aug 16 08:03:07 2025 -0500 Implement command chaining
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‎adapter1/fpga/rtl/axi_mm_channel_out.v‎

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,8 @@ module axi_mm_channel_out (
114114
reg clear_status_pending;
115115
reg status_stacked;
116116
reg [7:0] command;
117+
reg command_chained;
118+
reg command_chaining;
117119
reg [15:0] count;
118120
reg [31:0] storage_address;
119121
reg start_pending;
@@ -133,7 +135,8 @@ module axi_mm_channel_out (
133135
// D2: | SSSS SSSS | PS BA | CCCC S <- Start / Start Pending
134136
// ^^ ^^--------------- Active
135137
// ++---------------------- Pending / Stacked
136-
// D3: NNNN NNNN | NNNN NNNN | | CCCC CCCC
138+
// D3: NNNN NNNN | NNNN NNNN | DC | CCCC CCCC
139+
// ^^--------------- Command Chained / Chaining
137140
// D4: AAAA AAAA | AAAA AAAA | AAAA AAAA | AAAA AAAA <- Storage address
138141
//
139142
always @(posedge aclk)
@@ -181,7 +184,7 @@ module axi_mm_channel_out (
181184

182185
REG_DEVICE_3:
183186
begin
184-
s_axi_rdata <= { count, 8'b0, command };
187+
s_axi_rdata <= { count, 6'b0, command_chained, command_chaining, command };
185188
end
186189

187190
REG_DEVICE_4:
@@ -304,6 +307,8 @@ module axi_mm_channel_out (
304307
begin
305308
// TODO: wstrb
306309
command <= wdata[7:0];
310+
command_chaining <= wdata[8];
311+
command_chained <= wdata[9];
307312
count <= wdata[31:16];
308313
end
309314

@@ -515,7 +520,7 @@ module axi_mm_channel_out (
515520
begin
516521
// TODO: channel_burst <= no contention, probably
517522

518-
channel_in_tdata <= { 8'h11, device_address, command }; // XXX - Initial Selection
523+
channel_in_tdata <= { 3'b0, command_chained, 4'h2, device_address, command }; // XXX - Initial Selection
519524
channel_in_tvalid <= 1;
520525

521526
if (channel_in_tready && channel_in_tvalid)
@@ -730,7 +735,7 @@ module axi_mm_channel_out (
730735

731736
CHANNEL_STATE_ACCEPT_STATUS_1:
732737
begin
733-
channel_in_tdata <= 24'h020000; // XXX - Accept Status
738+
channel_in_tdata <= { 3'b0, command_chaining, 20'h30000 }; // XXX - Accept Status
734739
channel_in_tvalid <= 1;
735740

736741
if (channel_in_tready && channel_in_tvalid)
@@ -743,7 +748,7 @@ module axi_mm_channel_out (
743748

744749
CHANNEL_STATE_STACK_STATUS_1:
745750
begin
746-
channel_in_tdata <= 24'h030000; // XXX - Stack Status
751+
channel_in_tdata <= 24'h040000; // XXX - Stack Status
747752
channel_in_tvalid <= 1;
748753

749754
if (channel_in_tready && channel_in_tvalid)
@@ -774,7 +779,7 @@ module axi_mm_channel_out (
774779

775780
CHANNEL_STATE_SEND_DATA_3:
776781
begin
777-
channel_in_tdata <= { 8'h04, storage_data_read, 8'h00 }; // XXX - Send Data
782+
channel_in_tdata <= { 8'h05, storage_data_read, 8'h00 }; // XXX - Send Data
778783
channel_in_tvalid <= 1;
779784

780785
if (channel_in_tready && channel_in_tvalid)
@@ -807,7 +812,7 @@ module axi_mm_channel_out (
807812

808813
CHANNEL_STATE_RECEIVE_DATA_3:
809814
begin
810-
channel_in_tdata <= 24'h050000; // XXX - Accept Data
815+
channel_in_tdata <= 24'h060000; // XXX - Accept Data
811816
channel_in_tvalid <= 1;
812817

813818
if (channel_in_tready && channel_in_tvalid)
@@ -822,7 +827,7 @@ module axi_mm_channel_out (
822827

823828
CHANNEL_STATE_STOP:
824829
begin
825-
channel_in_tdata <= 24'h060000; // XXX - Stop
830+
channel_in_tdata <= 24'h070000; // XXX - Stop
826831
channel_in_tvalid <= 1;
827832

828833
if (channel_in_tready && channel_in_tvalid)
@@ -835,7 +840,13 @@ module axi_mm_channel_out (
835840

836841
CHANNEL_STATE_TEST_IO_1:
837842
begin
838-
channel_in_tdata <= { 8'h11, device_address, 8'h00 }; // XXX - Initial Selection
843+
// NOTE: It is not clear to me if command chained should be
844+
// indicated when executing test I/O, it may be moot if
845+
// stacking status resets command chaining.
846+
//
847+
// SPEC: The command-chaining condition [...] is reset
848+
// whenever the I/O device receives [...] stack status [...]
849+
channel_in_tdata <= { 8'h02, device_address, 8'h00 }; // XXX - Initial Selection
839850
channel_in_tvalid <= 1;
840851

841852
if (channel_in_tready && channel_in_tvalid)

‎adapter1/fpga/rtl/axi_mock_cu.v‎

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,8 @@ module axi_mock_cu (
8888
reg [15:0] mock_limit;
8989
wire [7:0] command;
9090
wire [15:0] count;
91+
wire command_chained;
92+
wire command_chaining;
9193

9294
always @(posedge aclk)
9395
begin
@@ -101,7 +103,7 @@ module axi_mock_cu (
101103
s_axi_rdata <= { mock_limit, 12'b0, mock_request, mock_short_busy, mock_busy, 1'b0 };
102104

103105
REG_STATUS:
104-
s_axi_rdata <= { count, command, 8'b0 };
106+
s_axi_rdata <= { count, command, 6'b0, command_chained, command_chaining };
105107

106108
default:
107109
s_axi_rresp <= 2'b10; // SLVERR
@@ -205,6 +207,16 @@ module axi_mock_cu (
205207
.clk(aclk),
206208
.reset(~aresetn),
207209

210+
.mock_busy(mock_busy),
211+
.mock_short_busy(mock_short_busy),
212+
.mock_request(mock_request),
213+
.mock_limit(mock_limit),
214+
215+
.command(command),
216+
.count(count),
217+
.command_chained(command_chained),
218+
.command_chaining(command_chaining),
219+
208220
.b_bus_in(b_bus_in),
209221
.b_bus_in_parity(b_bus_in_parity),
210222
.b_bus_out(b_bus_out),
@@ -239,14 +251,6 @@ module axi_mock_cu (
239251
.a_status_in(a_status_in),
240252
.a_service_in(a_service_in),
241253
.a_service_out(a_service_out),
242-
.a_suppress_out(a_suppress_out),
243-
244-
.mock_busy(mock_busy),
245-
.mock_short_busy(mock_short_busy),
246-
.mock_request(mock_request),
247-
.mock_limit(mock_limit),
248-
249-
.command(command),
250-
.count(count)
254+
.a_suppress_out(a_suppress_out)
251255
);
252256
endmodule

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