Skip to content

Commit 0fa6fdf

Browse files
authored
AMDGPU: Correct inst size for av_mov_b32_imm_pseudo (llvm#154459)
In the AGPR case this will be an 8 byte instruction, which is part of why this case is a pain to deal with in the first place.
1 parent eb2af3a commit 0fa6fdf

File tree

1 file changed

+2
-1
lines changed

1 file changed

+2
-1
lines changed

llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,8 @@ def AV_MOV_B32_IMM_PSEUDO
155155
let VOP3 = 1;
156156
let isMoveImm = 1;
157157
let SchedRW = [Write32Bit];
158-
let Size = 4;
158+
let Size = 8;
159+
let FixedSize = true;
159160
let UseNamedOperandTable = 1;
160161
}
161162

0 commit comments

Comments
 (0)