[CodeGen] Use Register::id() to avoid implicit cast. NFC

Author: topperc

llvm/include/llvm/CodeGen/RegisterPressure.h

@@ -280,7 +280,7 @@ class LiveRegSet {
     if (Reg.isVirtual())
       return Reg.virtRegIndex() + NumRegUnits;
     assert(Reg < NumRegUnits);
-    return Reg;
+    return Reg.id();
   }
 
   Register getRegFromSparseIndex(unsigned SparseIndex) const {

llvm/lib/CodeGen/BranchFolding.cpp

@@ -264,7 +264,7 @@ static unsigned HashMachineInstr(const MachineInstr &MI) {
     unsigned OperandHash = 0;
     switch (Op.getType()) {
     case MachineOperand::MO_Register:
-      OperandHash = Op.getReg();
+      OperandHash = Op.getReg().id();
       break;
     case MachineOperand::MO_Immediate:
       OperandHash = Op.getImm();

llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp

@@ -358,7 +358,9 @@ class StatepointState {
   MachineBasicBlock *getEHPad() const { return EHPad; }
 
   // Return true if register is callee saved.
-  bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; }
+  bool isCalleeSaved(Register Reg) {
+    return (Mask[Reg.id() / 32] >> (Reg.id() % 32)) & 1;
+  }
 
   // Iterates over statepoint meta args to find caller saver registers.
   // Also cache the size of found registers.

llvm/lib/CodeGen/MIRParser/MIParser.cpp

@@ -2828,7 +2828,7 @@ bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
       if (parseNamedRegister(Reg))
         return true;
       lex();
-      Mask[Reg / 32] |= 1U << (Reg % 32);
+      Mask[Reg.id() / 32] |= 1U << (Reg.id() % 32);
     }
 
     // TODO: Report an error if the same register is used more than once.
@@ -2853,7 +2853,7 @@ bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
     if (parseNamedRegister(Reg))
       return true;
     lex();
-    Mask[Reg / 32] |= 1U << (Reg % 32);
+    Mask[Reg.id() / 32] |= 1U << (Reg.id() % 32);
     // TODO: Report an error if the same register is used more than once.
     if (Token.isNot(MIToken::comma))
       break;

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

@@ -751,7 +751,7 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
       Register Reg;
       if (parseNamedRegisterReference(PFS, Reg, RegSource.Value, Error))
         return error(Error, RegSource.SourceRange);
-      CalleeSavedRegisters.push_back(Reg);
+      CalleeSavedRegisters.push_back(Reg.id());
     }
     RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
   }

llvm/lib/CodeGen/RegAllocGreedy.cpp

@@ -443,7 +443,7 @@ void RAGreedy::enqueue(PQueue &CurQueue, const LiveInterval *LI) {
 
   // The virtual register number is a tie breaker for same-sized ranges.
   // Give lower vreg numbers higher priority to assign them first.
-  CurQueue.push(std::make_pair(Ret, ~Reg));
+  CurQueue.push(std::make_pair(Ret, ~Reg.id()));
 }
 
 unsigned DefaultPriorityAdvisor::getPriority(const LiveInterval &LI) const {

llvm/lib/CodeGen/RegisterCoalescer.cpp

@@ -2311,7 +2311,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
     // We must also check for overlaps with regmask clobbers.
     BitVector RegMaskUsable;
     if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) &&
-        !RegMaskUsable.test(DstReg)) {
+        !RegMaskUsable.test(DstReg.id())) {
       LLVM_DEBUG(dbgs() << "\t\tRegMask interference\n");
       return false;
     }

llvm/lib/CodeGen/RegisterScavenging.cpp

@@ -112,7 +112,7 @@ BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
   BitVector Mask(TRI->getNumRegs());
   for (Register Reg : *RC)
     if (!isRegUsed(Reg))
-      Mask.set(Reg);
+      Mask.set(Reg.id());
   return Mask;
 }