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These VPlan debug output tests were added in llvm#108351 and llvm#110412, whenever we used to convert trivial recipes to VP intrinsics during EVL tail folding.
Nowadays we don't convert these recipes so there's nothing really to be gained from testing them. This removes the VPlan tests since an upcoming patch slightly perturbs these VPlans and removing them seems easier than manually going through and updating them all.
I've kept behind the LLVM IR/UTC counterparts, since even though they also aren't really testing anything useful at least they're easy to update.
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