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Update tests after rebasing on top of llvm#118285 
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‎llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll‎

Lines changed: 24 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -649,11 +649,10 @@ declare <vscale x 8 x half> @llvm.vp.ceil.nxv8f16(<vscale x 8 x half>, <vscale x
649649
define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
650650
; ZVFH-LABEL: vp_ceil_vv_nxv8f16:
651651
; ZVFH: # %bb.0:
652-
; ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
653-
; ZVFH-NEXT: vmv1r.v v10, v0
654-
; ZVFH-NEXT: lui a1, %hi(.LCPI18_0)
655-
; ZVFH-NEXT: flh fa5, %lo(.LCPI18_0)(a1)
656652
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
653+
; ZVFH-NEXT: vmv1r.v v10, v0
654+
; ZVFH-NEXT: lui a0, %hi(.LCPI18_0)
655+
; ZVFH-NEXT: flh fa5, %lo(.LCPI18_0)(a0)
657656
; ZVFH-NEXT: vfabs.v v12, v8, v0.t
658657
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
659658
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
@@ -736,11 +735,10 @@ declare <vscale x 16 x half> @llvm.vp.ceil.nxv16f16(<vscale x 16 x half>, <vscal
736735
define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
737736
; ZVFH-LABEL: vp_ceil_vv_nxv16f16:
738737
; ZVFH: # %bb.0:
739-
; ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
740-
; ZVFH-NEXT: vmv1r.v v12, v0
741-
; ZVFH-NEXT: lui a1, %hi(.LCPI20_0)
742-
; ZVFH-NEXT: flh fa5, %lo(.LCPI20_0)(a1)
743738
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
739+
; ZVFH-NEXT: vmv1r.v v12, v0
740+
; ZVFH-NEXT: lui a0, %hi(.LCPI20_0)
741+
; ZVFH-NEXT: flh fa5, %lo(.LCPI20_0)(a0)
744742
; ZVFH-NEXT: vfabs.v v16, v8, v0.t
745743
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
746744
; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t
@@ -823,11 +821,10 @@ declare <vscale x 32 x half> @llvm.vp.ceil.nxv32f16(<vscale x 32 x half>, <vscal
823821
define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
824822
; ZVFH-LABEL: vp_ceil_vv_nxv32f16:
825823
; ZVFH: # %bb.0:
826-
; ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
827-
; ZVFH-NEXT: vmv1r.v v16, v0
828-
; ZVFH-NEXT: lui a1, %hi(.LCPI22_0)
829-
; ZVFH-NEXT: flh fa5, %lo(.LCPI22_0)(a1)
830824
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
825+
; ZVFH-NEXT: vmv1r.v v16, v0
826+
; ZVFH-NEXT: lui a0, %hi(.LCPI22_0)
827+
; ZVFH-NEXT: flh fa5, %lo(.LCPI22_0)(a0)
831828
; ZVFH-NEXT: vfabs.v v24, v8, v0.t
832829
; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu
833830
; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t
@@ -1071,9 +1068,8 @@ declare <vscale x 4 x float> @llvm.vp.ceil.nxv4f32(<vscale x 4 x float>, <vscale
10711068
define <vscale x 4 x float> @vp_ceil_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
10721069
; CHECK-LABEL: vp_ceil_vv_nxv4f32:
10731070
; CHECK: # %bb.0:
1074-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1075-
; CHECK-NEXT: vmv1r.v v10, v0
10761071
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
1072+
; CHECK-NEXT: vmv1r.v v10, v0
10771073
; CHECK-NEXT: vfabs.v v12, v8, v0.t
10781074
; CHECK-NEXT: lui a0, 307200
10791075
; CHECK-NEXT: fmv.w.x fa5, a0
@@ -1116,9 +1112,8 @@ declare <vscale x 8 x float> @llvm.vp.ceil.nxv8f32(<vscale x 8 x float>, <vscale
11161112
define <vscale x 8 x float> @vp_ceil_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
11171113
; CHECK-LABEL: vp_ceil_vv_nxv8f32:
11181114
; CHECK: # %bb.0:
1119-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1120-
; CHECK-NEXT: vmv1r.v v12, v0
11211115
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
1116+
; CHECK-NEXT: vmv1r.v v12, v0
11221117
; CHECK-NEXT: vfabs.v v16, v8, v0.t
11231118
; CHECK-NEXT: lui a0, 307200
11241119
; CHECK-NEXT: fmv.w.x fa5, a0
@@ -1161,9 +1156,8 @@ declare <vscale x 16 x float> @llvm.vp.ceil.nxv16f32(<vscale x 16 x float>, <vsc
11611156
define <vscale x 16 x float> @vp_ceil_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
11621157
; CHECK-LABEL: vp_ceil_vv_nxv16f32:
11631158
; CHECK: # %bb.0:
1164-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1165-
; CHECK-NEXT: vmv1r.v v16, v0
11661159
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
1160+
; CHECK-NEXT: vmv1r.v v16, v0
11671161
; CHECK-NEXT: vfabs.v v24, v8, v0.t
11681162
; CHECK-NEXT: lui a0, 307200
11691163
; CHECK-NEXT: fmv.w.x fa5, a0
@@ -1248,11 +1242,10 @@ declare <vscale x 2 x double> @llvm.vp.ceil.nxv2f64(<vscale x 2 x double>, <vsca
12481242
define <vscale x 2 x double> @vp_ceil_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
12491243
; CHECK-LABEL: vp_ceil_vv_nxv2f64:
12501244
; CHECK: # %bb.0:
1251-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1252-
; CHECK-NEXT: vmv1r.v v10, v0
1253-
; CHECK-NEXT: lui a1, %hi(.LCPI36_0)
1254-
; CHECK-NEXT: fld fa5, %lo(.LCPI36_0)(a1)
12551245
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1246+
; CHECK-NEXT: vmv1r.v v10, v0
1247+
; CHECK-NEXT: lui a0, %hi(.LCPI36_0)
1248+
; CHECK-NEXT: fld fa5, %lo(.LCPI36_0)(a0)
12561249
; CHECK-NEXT: vfabs.v v12, v8, v0.t
12571250
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
12581251
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
@@ -1293,11 +1286,10 @@ declare <vscale x 4 x double> @llvm.vp.ceil.nxv4f64(<vscale x 4 x double>, <vsca
12931286
define <vscale x 4 x double> @vp_ceil_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
12941287
; CHECK-LABEL: vp_ceil_vv_nxv4f64:
12951288
; CHECK: # %bb.0:
1296-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1297-
; CHECK-NEXT: vmv1r.v v12, v0
1298-
; CHECK-NEXT: lui a1, %hi(.LCPI38_0)
1299-
; CHECK-NEXT: fld fa5, %lo(.LCPI38_0)(a1)
13001289
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1290+
; CHECK-NEXT: vmv1r.v v12, v0
1291+
; CHECK-NEXT: lui a0, %hi(.LCPI38_0)
1292+
; CHECK-NEXT: fld fa5, %lo(.LCPI38_0)(a0)
13011293
; CHECK-NEXT: vfabs.v v16, v8, v0.t
13021294
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
13031295
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
@@ -1338,11 +1330,10 @@ declare <vscale x 7 x double> @llvm.vp.ceil.nxv7f64(<vscale x 7 x double>, <vsca
13381330
define <vscale x 7 x double> @vp_ceil_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
13391331
; CHECK-LABEL: vp_ceil_vv_nxv7f64:
13401332
; CHECK: # %bb.0:
1341-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1342-
; CHECK-NEXT: vmv1r.v v16, v0
1343-
; CHECK-NEXT: lui a1, %hi(.LCPI40_0)
1344-
; CHECK-NEXT: fld fa5, %lo(.LCPI40_0)(a1)
13451333
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1334+
; CHECK-NEXT: vmv1r.v v16, v0
1335+
; CHECK-NEXT: lui a0, %hi(.LCPI40_0)
1336+
; CHECK-NEXT: fld fa5, %lo(.LCPI40_0)(a0)
13461337
; CHECK-NEXT: vfabs.v v24, v8, v0.t
13471338
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
13481339
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
@@ -1383,11 +1374,10 @@ declare <vscale x 8 x double> @llvm.vp.ceil.nxv8f64(<vscale x 8 x double>, <vsca
13831374
define <vscale x 8 x double> @vp_ceil_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
13841375
; CHECK-LABEL: vp_ceil_vv_nxv8f64:
13851376
; CHECK: # %bb.0:
1386-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1387-
; CHECK-NEXT: vmv1r.v v16, v0
1388-
; CHECK-NEXT: lui a1, %hi(.LCPI42_0)
1389-
; CHECK-NEXT: fld fa5, %lo(.LCPI42_0)(a1)
13901377
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1378+
; CHECK-NEXT: vmv1r.v v16, v0
1379+
; CHECK-NEXT: lui a0, %hi(.LCPI42_0)
1380+
; CHECK-NEXT: fld fa5, %lo(.LCPI42_0)(a0)
13911381
; CHECK-NEXT: vfabs.v v24, v8, v0.t
13921382
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
13931383
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1659,7 +1659,7 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
16591659
; RV32-NEXT: mul a1, a1, a2
16601660
; RV32-NEXT: sub sp, sp, a1
16611661
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 24 * vlenb
1662-
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1662+
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
16631663
; RV32-NEXT: vmv8r.v v24, v8
16641664
; RV32-NEXT: lui a2, 1044480
16651665
; RV32-NEXT: lui a3, 61681
@@ -1678,7 +1678,6 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
16781678
; RV32-NEXT: sw a3, 36(sp)
16791679
; RV32-NEXT: addi a3, sp, 16
16801680
; RV32-NEXT: addi a4, a5, 1365
1681-
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
16821681
; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
16831682
; RV32-NEXT: addi a5, a6, -256
16841683
; RV32-NEXT: sw a4, 24(sp)
@@ -2056,7 +2055,7 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
20562055
; RV32-NEXT: mul a1, a1, a2
20572056
; RV32-NEXT: sub sp, sp, a1
20582057
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 24 * vlenb
2059-
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
2058+
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
20602059
; RV32-NEXT: vmv8r.v v24, v8
20612060
; RV32-NEXT: lui a2, 1044480
20622061
; RV32-NEXT: lui a3, 61681
@@ -2075,7 +2074,6 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
20752074
; RV32-NEXT: sw a3, 36(sp)
20762075
; RV32-NEXT: addi a3, sp, 16
20772076
; RV32-NEXT: addi a4, a5, 1365
2078-
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
20792077
; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
20802078
; RV32-NEXT: addi a5, a6, -256
20812079
; RV32-NEXT: sw a4, 24(sp)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll‎

Lines changed: 17 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -261,11 +261,10 @@ declare <16 x half> @llvm.vp.ceil.v16f16(<16 x half>, <16 x i1>, i32)
261261
define <16 x half> @vp_ceil_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %evl) {
262262
; ZVFH-LABEL: vp_ceil_v16f16:
263263
; ZVFH: # %bb.0:
264-
; ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
265-
; ZVFH-NEXT: vmv1r.v v10, v0
266-
; ZVFH-NEXT: lui a1, %hi(.LCPI6_0)
267-
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
268264
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
265+
; ZVFH-NEXT: vmv1r.v v10, v0
266+
; ZVFH-NEXT: lui a0, %hi(.LCPI6_0)
267+
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a0)
269268
; ZVFH-NEXT: vfabs.v v12, v8, v0.t
270269
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
271270
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
@@ -432,9 +431,8 @@ declare <8 x float> @llvm.vp.ceil.v8f32(<8 x float>, <8 x i1>, i32)
432431
define <8 x float> @vp_ceil_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl) {
433432
; CHECK-LABEL: vp_ceil_v8f32:
434433
; CHECK: # %bb.0:
435-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
436-
; CHECK-NEXT: vmv1r.v v10, v0
437434
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
435+
; CHECK-NEXT: vmv1r.v v10, v0
438436
; CHECK-NEXT: vfabs.v v12, v8, v0.t
439437
; CHECK-NEXT: lui a0, 307200
440438
; CHECK-NEXT: fmv.w.x fa5, a0
@@ -477,9 +475,8 @@ declare <16 x float> @llvm.vp.ceil.v16f32(<16 x float>, <16 x i1>, i32)
477475
define <16 x float> @vp_ceil_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext %evl) {
478476
; CHECK-LABEL: vp_ceil_v16f32:
479477
; CHECK: # %bb.0:
480-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
481-
; CHECK-NEXT: vmv1r.v v12, v0
482478
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
479+
; CHECK-NEXT: vmv1r.v v12, v0
483480
; CHECK-NEXT: vfabs.v v16, v8, v0.t
484481
; CHECK-NEXT: lui a0, 307200
485482
; CHECK-NEXT: fmv.w.x fa5, a0
@@ -564,11 +561,10 @@ declare <4 x double> @llvm.vp.ceil.v4f64(<4 x double>, <4 x i1>, i32)
564561
define <4 x double> @vp_ceil_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
565562
; CHECK-LABEL: vp_ceil_v4f64:
566563
; CHECK: # %bb.0:
567-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
568-
; CHECK-NEXT: vmv1r.v v10, v0
569-
; CHECK-NEXT: lui a1, %hi(.LCPI18_0)
570-
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
571564
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
565+
; CHECK-NEXT: vmv1r.v v10, v0
566+
; CHECK-NEXT: lui a0, %hi(.LCPI18_0)
567+
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
572568
; CHECK-NEXT: vfabs.v v12, v8, v0.t
573569
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
574570
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
@@ -609,11 +605,10 @@ declare <8 x double> @llvm.vp.ceil.v8f64(<8 x double>, <8 x i1>, i32)
609605
define <8 x double> @vp_ceil_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %evl) {
610606
; CHECK-LABEL: vp_ceil_v8f64:
611607
; CHECK: # %bb.0:
612-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
613-
; CHECK-NEXT: vmv1r.v v12, v0
614-
; CHECK-NEXT: lui a1, %hi(.LCPI20_0)
615-
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
616608
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
609+
; CHECK-NEXT: vmv1r.v v12, v0
610+
; CHECK-NEXT: lui a0, %hi(.LCPI20_0)
611+
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
617612
; CHECK-NEXT: vfabs.v v16, v8, v0.t
618613
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
619614
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
@@ -654,11 +649,10 @@ declare <15 x double> @llvm.vp.ceil.v15f64(<15 x double>, <15 x i1>, i32)
654649
define <15 x double> @vp_ceil_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroext %evl) {
655650
; CHECK-LABEL: vp_ceil_v15f64:
656651
; CHECK: # %bb.0:
657-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
658-
; CHECK-NEXT: vmv1r.v v16, v0
659-
; CHECK-NEXT: lui a1, %hi(.LCPI22_0)
660-
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
661652
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
653+
; CHECK-NEXT: vmv1r.v v16, v0
654+
; CHECK-NEXT: lui a0, %hi(.LCPI22_0)
655+
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a0)
662656
; CHECK-NEXT: vfabs.v v24, v8, v0.t
663657
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
664658
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
@@ -699,11 +693,10 @@ declare <16 x double> @llvm.vp.ceil.v16f64(<16 x double>, <16 x i1>, i32)
699693
define <16 x double> @vp_ceil_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroext %evl) {
700694
; CHECK-LABEL: vp_ceil_v16f64:
701695
; CHECK: # %bb.0:
702-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
703-
; CHECK-NEXT: vmv1r.v v16, v0
704-
; CHECK-NEXT: lui a1, %hi(.LCPI24_0)
705-
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
706696
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
697+
; CHECK-NEXT: vmv1r.v v16, v0
698+
; CHECK-NEXT: lui a0, %hi(.LCPI24_0)
699+
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a0)
707700
; CHECK-NEXT: vfabs.v v24, v8, v0.t
708701
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
709702
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll‎

Lines changed: 17 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -261,11 +261,10 @@ declare <16 x half> @llvm.vp.floor.v16f16(<16 x half>, <16 x i1>, i32)
261261
define <16 x half> @vp_floor_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %evl) {
262262
; ZVFH-LABEL: vp_floor_v16f16:
263263
; ZVFH: # %bb.0:
264-
; ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
265-
; ZVFH-NEXT: vmv1r.v v10, v0
266-
; ZVFH-NEXT: lui a1, %hi(.LCPI6_0)
267-
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a1)
268264
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
265+
; ZVFH-NEXT: vmv1r.v v10, v0
266+
; ZVFH-NEXT: lui a0, %hi(.LCPI6_0)
267+
; ZVFH-NEXT: flh fa5, %lo(.LCPI6_0)(a0)
269268
; ZVFH-NEXT: vfabs.v v12, v8, v0.t
270269
; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu
271270
; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t
@@ -432,9 +431,8 @@ declare <8 x float> @llvm.vp.floor.v8f32(<8 x float>, <8 x i1>, i32)
432431
define <8 x float> @vp_floor_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl) {
433432
; CHECK-LABEL: vp_floor_v8f32:
434433
; CHECK: # %bb.0:
435-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
436-
; CHECK-NEXT: vmv1r.v v10, v0
437434
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
435+
; CHECK-NEXT: vmv1r.v v10, v0
438436
; CHECK-NEXT: vfabs.v v12, v8, v0.t
439437
; CHECK-NEXT: lui a0, 307200
440438
; CHECK-NEXT: fmv.w.x fa5, a0
@@ -477,9 +475,8 @@ declare <16 x float> @llvm.vp.floor.v16f32(<16 x float>, <16 x i1>, i32)
477475
define <16 x float> @vp_floor_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext %evl) {
478476
; CHECK-LABEL: vp_floor_v16f32:
479477
; CHECK: # %bb.0:
480-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
481-
; CHECK-NEXT: vmv1r.v v12, v0
482478
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
479+
; CHECK-NEXT: vmv1r.v v12, v0
483480
; CHECK-NEXT: vfabs.v v16, v8, v0.t
484481
; CHECK-NEXT: lui a0, 307200
485482
; CHECK-NEXT: fmv.w.x fa5, a0
@@ -564,11 +561,10 @@ declare <4 x double> @llvm.vp.floor.v4f64(<4 x double>, <4 x i1>, i32)
564561
define <4 x double> @vp_floor_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
565562
; CHECK-LABEL: vp_floor_v4f64:
566563
; CHECK: # %bb.0:
567-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
568-
; CHECK-NEXT: vmv1r.v v10, v0
569-
; CHECK-NEXT: lui a1, %hi(.LCPI18_0)
570-
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a1)
571564
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
565+
; CHECK-NEXT: vmv1r.v v10, v0
566+
; CHECK-NEXT: lui a0, %hi(.LCPI18_0)
567+
; CHECK-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
572568
; CHECK-NEXT: vfabs.v v12, v8, v0.t
573569
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
574570
; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t
@@ -609,11 +605,10 @@ declare <8 x double> @llvm.vp.floor.v8f64(<8 x double>, <8 x i1>, i32)
609605
define <8 x double> @vp_floor_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %evl) {
610606
; CHECK-LABEL: vp_floor_v8f64:
611607
; CHECK: # %bb.0:
612-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
613-
; CHECK-NEXT: vmv1r.v v12, v0
614-
; CHECK-NEXT: lui a1, %hi(.LCPI20_0)
615-
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a1)
616608
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
609+
; CHECK-NEXT: vmv1r.v v12, v0
610+
; CHECK-NEXT: lui a0, %hi(.LCPI20_0)
611+
; CHECK-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
617612
; CHECK-NEXT: vfabs.v v16, v8, v0.t
618613
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
619614
; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t
@@ -654,11 +649,10 @@ declare <15 x double> @llvm.vp.floor.v15f64(<15 x double>, <15 x i1>, i32)
654649
define <15 x double> @vp_floor_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroext %evl) {
655650
; CHECK-LABEL: vp_floor_v15f64:
656651
; CHECK: # %bb.0:
657-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
658-
; CHECK-NEXT: vmv1r.v v16, v0
659-
; CHECK-NEXT: lui a1, %hi(.LCPI22_0)
660-
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a1)
661652
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
653+
; CHECK-NEXT: vmv1r.v v16, v0
654+
; CHECK-NEXT: lui a0, %hi(.LCPI22_0)
655+
; CHECK-NEXT: fld fa5, %lo(.LCPI22_0)(a0)
662656
; CHECK-NEXT: vfabs.v v24, v8, v0.t
663657
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
664658
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t
@@ -699,11 +693,10 @@ declare <16 x double> @llvm.vp.floor.v16f64(<16 x double>, <16 x i1>, i32)
699693
define <16 x double> @vp_floor_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroext %evl) {
700694
; CHECK-LABEL: vp_floor_v16f64:
701695
; CHECK: # %bb.0:
702-
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
703-
; CHECK-NEXT: vmv1r.v v16, v0
704-
; CHECK-NEXT: lui a1, %hi(.LCPI24_0)
705-
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a1)
706696
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
697+
; CHECK-NEXT: vmv1r.v v16, v0
698+
; CHECK-NEXT: lui a0, %hi(.LCPI24_0)
699+
; CHECK-NEXT: fld fa5, %lo(.LCPI24_0)(a0)
707700
; CHECK-NEXT: vfabs.v v24, v8, v0.t
708701
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
709702
; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t

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