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Use an AVL of 1
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104 files changed

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‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1237,7 +1237,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
12371237
// Use an arbitrary but valid AVL and VTYPE so vill will be cleared. It may
12381238
// be coalesced into another vsetvli since we won't demand any fields.
12391239
VSETVLIInfo NewInfo; // Need a new VSETVLIInfo to clear SEWLMULRatioOnly
1240-
NewInfo.setAVLImm(0);
1240+
NewInfo.setAVLImm(1);
12411241
NewInfo.setVTYPE(RISCVII::VLMUL::LMUL_1, 8, true, true);
12421242
Info = NewInfo;
12431243
return;

‎llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ define <vscale x 1 x i8> @constraint_vd(<vscale x 1 x i8> %0, <vscale x 1 x i8>
4545
define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
4646
; RV32I-LABEL: constraint_vm:
4747
; RV32I: # %bb.0:
48-
; RV32I-NEXT: vsetivli zero, 0, e8, m1, ta, ma
48+
; RV32I-NEXT: vsetivli zero, 1, e8, m1, ta, ma
4949
; RV32I-NEXT: vmv1r.v v9, v0
5050
; RV32I-NEXT: vmv1r.v v0, v8
5151
; RV32I-NEXT: #APP
@@ -55,7 +55,7 @@ define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1>
5555
;
5656
; RV64I-LABEL: constraint_vm:
5757
; RV64I: # %bb.0:
58-
; RV64I-NEXT: vsetivli zero, 0, e8, m1, ta, ma
58+
; RV64I-NEXT: vsetivli zero, 1, e8, m1, ta, ma
5959
; RV64I-NEXT: vmv1r.v v9, v0
6060
; RV64I-NEXT: vmv1r.v v0, v8
6161
; RV64I-NEXT: #APP

‎llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -336,7 +336,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_i32(<vsca
336336
; RV32-NEXT: add a1, a3, a1
337337
; RV32-NEXT: li a3, 2
338338
; RV32-NEXT: vs8r.v v16, (a1)
339-
; RV32-NEXT: vsetivli zero, 0, e8, m1, ta, ma
339+
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
340340
; RV32-NEXT: vmv8r.v v8, v0
341341
; RV32-NEXT: vmv8r.v v16, v24
342342
; RV32-NEXT: call ext2
@@ -375,7 +375,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_i32(<vsca
375375
; RV64-NEXT: add a1, a3, a1
376376
; RV64-NEXT: li a3, 2
377377
; RV64-NEXT: vs8r.v v16, (a1)
378-
; RV64-NEXT: vsetivli zero, 0, e8, m1, ta, ma
378+
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
379379
; RV64-NEXT: vmv8r.v v8, v0
380380
; RV64-NEXT: vmv8r.v v16, v24
381381
; RV64-NEXT: call ext2
@@ -453,7 +453,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_
453453
; RV32-NEXT: add a1, sp, a1
454454
; RV32-NEXT: addi a1, a1, 128
455455
; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
456-
; RV32-NEXT: vsetivli zero, 0, e8, m1, ta, ma
456+
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
457457
; RV32-NEXT: vmv8r.v v16, v0
458458
; RV32-NEXT: call ext3
459459
; RV32-NEXT: addi sp, s0, -144
@@ -526,7 +526,7 @@ define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_
526526
; RV64-NEXT: add a1, sp, a1
527527
; RV64-NEXT: addi a1, a1, 128
528528
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
529-
; RV64-NEXT: vsetivli zero, 0, e8, m1, ta, ma
529+
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
530530
; RV64-NEXT: vmv8r.v v16, v0
531531
; RV64-NEXT: call ext3
532532
; RV64-NEXT: addi sp, s0, -144

‎llvm/test/CodeGen/RISCV/rvv/calling-conv.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @caller_tuple_return(
103103
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
104104
; RV32-NEXT: .cfi_offset ra, -4
105105
; RV32-NEXT: call callee_tuple_return
106-
; RV32-NEXT: vsetivli zero, 0, e8, m1, ta, ma
106+
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
107107
; RV32-NEXT: vmv2r.v v6, v8
108108
; RV32-NEXT: vmv2r.v v8, v10
109109
; RV32-NEXT: vmv2r.v v10, v6
@@ -120,7 +120,7 @@ define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @caller_tuple_return(
120120
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
121121
; RV64-NEXT: .cfi_offset ra, -8
122122
; RV64-NEXT: call callee_tuple_return
123-
; RV64-NEXT: vsetivli zero, 0, e8, m1, ta, ma
123+
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
124124
; RV64-NEXT: vmv2r.v v6, v8
125125
; RV64-NEXT: vmv2r.v v8, v10
126126
; RV64-NEXT: vmv2r.v v10, v6
@@ -146,7 +146,7 @@ define void @caller_tuple_argument(target("riscv.vector.tuple", <vscale x 16 x i
146146
; RV32-NEXT: .cfi_def_cfa_offset 16
147147
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
148148
; RV32-NEXT: .cfi_offset ra, -4
149-
; RV32-NEXT: vsetivli zero, 0, e8, m1, ta, ma
149+
; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
150150
; RV32-NEXT: vmv2r.v v6, v8
151151
; RV32-NEXT: vmv2r.v v8, v10
152152
; RV32-NEXT: vmv2r.v v10, v6
@@ -163,7 +163,7 @@ define void @caller_tuple_argument(target("riscv.vector.tuple", <vscale x 16 x i
163163
; RV64-NEXT: .cfi_def_cfa_offset 16
164164
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
165165
; RV64-NEXT: .cfi_offset ra, -8
166-
; RV64-NEXT: vsetivli zero, 0, e8, m1, ta, ma
166+
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
167167
; RV64-NEXT: vmv2r.v v6, v8
168168
; RV64-NEXT: vmv2r.v v8, v10
169169
; RV64-NEXT: vmv2r.v v10, v6

‎llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -649,7 +649,7 @@ declare <vscale x 8 x half> @llvm.vp.ceil.nxv8f16(<vscale x 8 x half>, <vscale x
649649
define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
650650
; ZVFH-LABEL: vp_ceil_vv_nxv8f16:
651651
; ZVFH: # %bb.0:
652-
; ZVFH-NEXT: vsetivli zero, 0, e8, m1, ta, ma
652+
; ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
653653
; ZVFH-NEXT: vmv1r.v v10, v0
654654
; ZVFH-NEXT: lui a1, %hi(.LCPI18_0)
655655
; ZVFH-NEXT: flh fa5, %lo(.LCPI18_0)(a1)
@@ -736,7 +736,7 @@ declare <vscale x 16 x half> @llvm.vp.ceil.nxv16f16(<vscale x 16 x half>, <vscal
736736
define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
737737
; ZVFH-LABEL: vp_ceil_vv_nxv16f16:
738738
; ZVFH: # %bb.0:
739-
; ZVFH-NEXT: vsetivli zero, 0, e8, m1, ta, ma
739+
; ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
740740
; ZVFH-NEXT: vmv1r.v v12, v0
741741
; ZVFH-NEXT: lui a1, %hi(.LCPI20_0)
742742
; ZVFH-NEXT: flh fa5, %lo(.LCPI20_0)(a1)
@@ -823,7 +823,7 @@ declare <vscale x 32 x half> @llvm.vp.ceil.nxv32f16(<vscale x 32 x half>, <vscal
823823
define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
824824
; ZVFH-LABEL: vp_ceil_vv_nxv32f16:
825825
; ZVFH: # %bb.0:
826-
; ZVFH-NEXT: vsetivli zero, 0, e8, m1, ta, ma
826+
; ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
827827
; ZVFH-NEXT: vmv1r.v v16, v0
828828
; ZVFH-NEXT: lui a1, %hi(.LCPI22_0)
829829
; ZVFH-NEXT: flh fa5, %lo(.LCPI22_0)(a1)
@@ -1071,7 +1071,7 @@ declare <vscale x 4 x float> @llvm.vp.ceil.nxv4f32(<vscale x 4 x float>, <vscale
10711071
define <vscale x 4 x float> @vp_ceil_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
10721072
; CHECK-LABEL: vp_ceil_vv_nxv4f32:
10731073
; CHECK: # %bb.0:
1074-
; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, ma
1074+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
10751075
; CHECK-NEXT: vmv1r.v v10, v0
10761076
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
10771077
; CHECK-NEXT: vfabs.v v12, v8, v0.t
@@ -1116,7 +1116,7 @@ declare <vscale x 8 x float> @llvm.vp.ceil.nxv8f32(<vscale x 8 x float>, <vscale
11161116
define <vscale x 8 x float> @vp_ceil_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
11171117
; CHECK-LABEL: vp_ceil_vv_nxv8f32:
11181118
; CHECK: # %bb.0:
1119-
; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, ma
1119+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
11201120
; CHECK-NEXT: vmv1r.v v12, v0
11211121
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
11221122
; CHECK-NEXT: vfabs.v v16, v8, v0.t
@@ -1161,7 +1161,7 @@ declare <vscale x 16 x float> @llvm.vp.ceil.nxv16f32(<vscale x 16 x float>, <vsc
11611161
define <vscale x 16 x float> @vp_ceil_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
11621162
; CHECK-LABEL: vp_ceil_vv_nxv16f32:
11631163
; CHECK: # %bb.0:
1164-
; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, ma
1164+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
11651165
; CHECK-NEXT: vmv1r.v v16, v0
11661166
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
11671167
; CHECK-NEXT: vfabs.v v24, v8, v0.t
@@ -1248,7 +1248,7 @@ declare <vscale x 2 x double> @llvm.vp.ceil.nxv2f64(<vscale x 2 x double>, <vsca
12481248
define <vscale x 2 x double> @vp_ceil_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
12491249
; CHECK-LABEL: vp_ceil_vv_nxv2f64:
12501250
; CHECK: # %bb.0:
1251-
; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, ma
1251+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
12521252
; CHECK-NEXT: vmv1r.v v10, v0
12531253
; CHECK-NEXT: lui a1, %hi(.LCPI36_0)
12541254
; CHECK-NEXT: fld fa5, %lo(.LCPI36_0)(a1)
@@ -1293,7 +1293,7 @@ declare <vscale x 4 x double> @llvm.vp.ceil.nxv4f64(<vscale x 4 x double>, <vsca
12931293
define <vscale x 4 x double> @vp_ceil_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
12941294
; CHECK-LABEL: vp_ceil_vv_nxv4f64:
12951295
; CHECK: # %bb.0:
1296-
; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, ma
1296+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
12971297
; CHECK-NEXT: vmv1r.v v12, v0
12981298
; CHECK-NEXT: lui a1, %hi(.LCPI38_0)
12991299
; CHECK-NEXT: fld fa5, %lo(.LCPI38_0)(a1)
@@ -1338,7 +1338,7 @@ declare <vscale x 7 x double> @llvm.vp.ceil.nxv7f64(<vscale x 7 x double>, <vsca
13381338
define <vscale x 7 x double> @vp_ceil_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
13391339
; CHECK-LABEL: vp_ceil_vv_nxv7f64:
13401340
; CHECK: # %bb.0:
1341-
; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, ma
1341+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
13421342
; CHECK-NEXT: vmv1r.v v16, v0
13431343
; CHECK-NEXT: lui a1, %hi(.LCPI40_0)
13441344
; CHECK-NEXT: fld fa5, %lo(.LCPI40_0)(a1)
@@ -1383,7 +1383,7 @@ declare <vscale x 8 x double> @llvm.vp.ceil.nxv8f64(<vscale x 8 x double>, <vsca
13831383
define <vscale x 8 x double> @vp_ceil_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
13841384
; CHECK-LABEL: vp_ceil_vv_nxv8f64:
13851385
; CHECK: # %bb.0:
1386-
; CHECK-NEXT: vsetivli zero, 0, e8, m1, ta, ma
1386+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
13871387
; CHECK-NEXT: vmv1r.v v16, v0
13881388
; CHECK-NEXT: lui a1, %hi(.LCPI42_0)
13891389
; CHECK-NEXT: fld fa5, %lo(.LCPI42_0)(a1)

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