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[RISCV] Remove remaining vmerge_vl mask patterns. NFC
Now that RISCVVectorPeephole can commute operands to fold vmerge into a pseudo to make it masked in llvm#156499, we can remove the remaining VPatMultiplyAccVL_VV_VX/VPatFPMulAccVL_VV_VF_RM patterns. It also looks like we can remove the vmerge_vl patterns for _TIED psuedos too. Tested on SPEC CPU 2017 and llvm-test-suite to confirm there's no codegen change. Fixes llvm#141885
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

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Original file line numberDiff line numberDiff line change
@@ -830,19 +830,6 @@ multiclass VPatTiedBinaryNoMaskVL_V<SDNode vop,
830830
result_reg_class:$rs1,
831831
op2_reg_class:$rs2,
832832
GPR:$vl, sew, TAIL_AGNOSTIC)>;
833-
// Tail undisturbed
834-
def : Pat<(riscv_vmerge_vl true_mask,
835-
(result_type (vop
836-
result_reg_class:$rs1,
837-
(op2_type op2_reg_class:$rs2),
838-
srcvalue,
839-
true_mask,
840-
VLOpFrag)),
841-
result_reg_class:$rs1, result_reg_class:$rs1, VLOpFrag),
842-
(!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_TIED")
843-
result_reg_class:$rs1,
844-
op2_reg_class:$rs2,
845-
GPR:$vl, sew, TU_MU)>;
846833
}
847834

848835
class VPatTiedBinaryMaskVL_V<SDNode vop,
@@ -892,22 +879,6 @@ multiclass VPatTiedBinaryNoMaskVL_V_RM<SDNode vop,
892879
// RISCVInsertReadWriteCSR
893880
FRM_DYN,
894881
GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
895-
// Tail undisturbed
896-
def : Pat<(riscv_vmerge_vl true_mask,
897-
(result_type (vop
898-
result_reg_class:$rs1,
899-
(op2_type op2_reg_class:$rs2),
900-
srcvalue,
901-
true_mask,
902-
VLOpFrag)),
903-
result_reg_class:$rs1, result_reg_class:$rs1, VLOpFrag),
904-
(!cast<Instruction>(name)
905-
result_reg_class:$rs1,
906-
op2_reg_class:$rs2,
907-
// Value to indicate no rounding mode change in
908-
// RISCVInsertReadWriteCSR
909-
FRM_DYN,
910-
GPR:$vl, log2sew, TU_MU)>;
911882
}
912883

913884
class VPatBinaryVL_XI<SDPatternOperator vop,
@@ -1755,50 +1726,6 @@ multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> {
17551726
}
17561727
}
17571728

1758-
multiclass VPatMultiplyAccVL_VV_VX<PatFrag op, string instruction_name> {
1759-
foreach vti = AllIntegerVectors in {
1760-
defvar suffix = vti.LMul.MX;
1761-
let Predicates = GetVTypePredicates<vti>.Predicates in {
1762-
def : Pat<(riscv_vmerge_vl (vti.Mask VMV0:$vm),
1763-
(vti.Vector (op vti.RegClass:$rd,
1764-
(riscv_mul_vl_oneuse vti.RegClass:$rs1, vti.RegClass:$rs2,
1765-
srcvalue, (vti.Mask true_mask), VLOpFrag),
1766-
srcvalue, (vti.Mask true_mask), VLOpFrag)),
1767-
vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag),
1768-
(!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
1769-
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1770-
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TU_MU)>;
1771-
def : Pat<(riscv_vmerge_vl (vti.Mask VMV0:$vm),
1772-
(vti.Vector (op vti.RegClass:$rd,
1773-
(riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), vti.RegClass:$rs2,
1774-
srcvalue, (vti.Mask true_mask), VLOpFrag),
1775-
srcvalue, (vti.Mask true_mask), VLOpFrag)),
1776-
vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag),
1777-
(!cast<Instruction>(instruction_name#"_VX_"# suffix #"_MASK")
1778-
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
1779-
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TU_MU)>;
1780-
def : Pat<(riscv_vmerge_vl (vti.Mask VMV0:$vm),
1781-
(vti.Vector (op vti.RegClass:$rd,
1782-
(riscv_mul_vl_oneuse vti.RegClass:$rs1, vti.RegClass:$rs2,
1783-
srcvalue, (vti.Mask true_mask), VLOpFrag),
1784-
srcvalue, (vti.Mask true_mask), VLOpFrag)),
1785-
vti.RegClass:$rd, undef, VLOpFrag),
1786-
(!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
1787-
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1788-
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1789-
def : Pat<(riscv_vmerge_vl (vti.Mask VMV0:$vm),
1790-
(vti.Vector (op vti.RegClass:$rd,
1791-
(riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), vti.RegClass:$rs2,
1792-
srcvalue, (vti.Mask true_mask), VLOpFrag),
1793-
srcvalue, (vti.Mask true_mask), VLOpFrag)),
1794-
vti.RegClass:$rd, undef, VLOpFrag),
1795-
(!cast<Instruction>(instruction_name#"_VX_"# suffix #"_MASK")
1796-
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
1797-
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1798-
}
1799-
}
1800-
}
1801-
18021729
multiclass VPatWidenMultiplyAddVL_VV_VX<SDNode vwmacc_op, string instr_name> {
18031730
foreach vtiTowti = AllWidenableIntVectors in {
18041731
defvar vti = vtiTowti.Vti;
@@ -1898,82 +1825,6 @@ multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_nam
18981825
}
18991826
}
19001827

1901-
multiclass VPatFPMulAccVL_VV_VF_RM<PatFrag vop, string instruction_name> {
1902-
foreach vti = AllFloatVectors in {
1903-
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
1904-
let Predicates = GetVTypePredicates<vti>.Predicates in {
1905-
def : Pat<(riscv_vmerge_vl (vti.Mask VMV0:$vm),
1906-
(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2,
1907-
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
1908-
vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag),
1909-
(!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
1910-
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1911-
(vti.Mask VMV0:$vm),
1912-
// Value to indicate no rounding mode change in
1913-
// RISCVInsertReadWriteCSR
1914-
FRM_DYN,
1915-
GPR:$vl, vti.Log2SEW, TU_MU)>;
1916-
def : Pat<(riscv_vmerge_vl (vti.Mask VMV0:$vm),
1917-
(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), vti.RegClass:$rs2,
1918-
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
1919-
vti.RegClass:$rd, vti.RegClass:$rd, VLOpFrag),
1920-
(!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
1921-
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
1922-
(vti.Mask VMV0:$vm),
1923-
// Value to indicate no rounding mode change in
1924-
// RISCVInsertReadWriteCSR
1925-
FRM_DYN,
1926-
GPR:$vl, vti.Log2SEW, TU_MU)>;
1927-
def : Pat<(riscv_vmerge_vl (vti.Mask VMV0:$vm),
1928-
(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2,
1929-
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
1930-
vti.RegClass:$rd, undef, VLOpFrag),
1931-
(!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
1932-
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1933-
(vti.Mask VMV0:$vm),
1934-
// Value to indicate no rounding mode change in
1935-
// RISCVInsertReadWriteCSR
1936-
FRM_DYN,
1937-
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1938-
def : Pat<(riscv_vmerge_vl (vti.Mask VMV0:$vm),
1939-
(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), vti.RegClass:$rs2,
1940-
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
1941-
vti.RegClass:$rd, undef, VLOpFrag),
1942-
(!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
1943-
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
1944-
(vti.Mask VMV0:$vm),
1945-
// Value to indicate no rounding mode change in
1946-
// RISCVInsertReadWriteCSR
1947-
FRM_DYN,
1948-
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
1949-
}
1950-
}
1951-
}
1952-
1953-
multiclass VPatWidenFPMulAccVL_VV_VF<SDNode vop, string instruction_name> {
1954-
foreach vtiToWti = AllWidenableFloatVectors in {
1955-
defvar vti = vtiToWti.Vti;
1956-
defvar wti = vtiToWti.Wti;
1957-
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
1958-
GetVTypePredicates<wti>.Predicates) in {
1959-
def : Pat<(vop (vti.Vector vti.RegClass:$rs1),
1960-
(vti.Vector vti.RegClass:$rs2),
1961-
(wti.Vector wti.RegClass:$rd), (vti.Mask VMV0:$vm),
1962-
VLOpFrag),
1963-
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX #"_MASK")
1964-
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
1965-
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;
1966-
def : Pat<(vop (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
1967-
(vti.Vector vti.RegClass:$rs2),
1968-
(wti.Vector wti.RegClass:$rd), (vti.Mask VMV0:$vm),
1969-
VLOpFrag),
1970-
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX #"_MASK")
1971-
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
1972-
(vti.Mask VMV0:$vm), GPR:$vl, vti.Log2SEW, TA_MA)>;
1973-
}
1974-
}
1975-
}
1976-
19771828
multiclass VPatWidenFPMulAccVL_VV_VF_RM<SDNode vop, string instruction_name,
19781829
list<VTypeInfoToWide> vtiToWtis =
19791830
AllWidenableFloatVectors> {
@@ -2331,8 +2182,6 @@ defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">;
23312182
// 11.13 Vector Single-Width Integer Multiply-Add Instructions
23322183
defm : VPatMultiplyAddVL_VV_VX<riscv_add_vl, "PseudoVMADD">;
23332184
defm : VPatMultiplyAddVL_VV_VX<riscv_sub_vl, "PseudoVNMSUB">;
2334-
defm : VPatMultiplyAccVL_VV_VX<riscv_add_vl_oneuse, "PseudoVMACC">;
2335-
defm : VPatMultiplyAccVL_VV_VX<riscv_sub_vl_oneuse, "PseudoVNMSAC">;
23362185

23372186
// 11.14. Vector Widening Integer Multiply-Add Instructions
23382187
defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmacc_vl, "PseudoVWMACC">;
@@ -2470,10 +2319,6 @@ defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfmadd_vl, "PseudoVFMADD">;
24702319
defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfmsub_vl, "PseudoVFMSUB">;
24712320
defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmadd_vl, "PseudoVFNMADD">;
24722321
defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmsub_vl, "PseudoVFNMSUB">;
2473-
defm : VPatFPMulAccVL_VV_VF_RM<riscv_vfmadd_vl_oneuse, "PseudoVFMACC">;
2474-
defm : VPatFPMulAccVL_VV_VF_RM<riscv_vfmsub_vl_oneuse, "PseudoVFMSAC">;
2475-
defm : VPatFPMulAccVL_VV_VF_RM<riscv_vfnmadd_vl_oneuse, "PseudoVFNMACC">;
2476-
defm : VPatFPMulAccVL_VV_VF_RM<riscv_vfnmsub_vl_oneuse, "PseudoVFNMSAC">;
24772322

24782323
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
24792324
defm : VPatWidenFPMulAccVL_VV_VF_RM<riscv_vfwmadd_vl, "PseudoVFWMACC">;

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