diff --git a/counter/.gitignore b/counter/.gitignore new file mode 100644 index 0000000..674cc76 --- /dev/null +++ b/counter/.gitignore @@ -0,0 +1 @@ +counter/ diff --git a/counter/counter.sby b/counter/counter.sby new file mode 100644 index 0000000..d95d8ac --- /dev/null +++ b/counter/counter.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 15 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read -formal counter.v +prep -top counter + +[files] +counter.v diff --git a/counter/counter.v b/counter/counter.v index f01efe2..f6eada2 100644 --- a/counter/counter.v +++ b/counter/counter.v @@ -1,3 +1,7 @@ +`ifdef FORMAL +`default_nettype none +`endif + module counter ( input clk, @@ -17,4 +21,50 @@ always @(posedge clk) begin end assign led = ~ledCounter; + +// +// FORMAL VERIFICATION +// +`ifdef FORMAL + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk) + f_past_valid <= 1'b1; + + // + // clockCounter + // + + // Prove that counter can't be higher than WAIT_TIME + always @(*) + assert(clockCounter <= WAIT_TIME); + + // Prove that counter counts up + always @(posedge clk) + if((f_past_valid)&&($past(f_past_valid))) begin + if(clockCounter == 0) + assert($past(clockCounter)==WAIT_TIME); + else + assert(clockCounter == ($past(clockCounter)+1)); + end + + // + // ledCounter + // + + // Prove that counter counts up + always @(posedge clk) + if((f_past_valid)&&($past(f_past_valid))) begin + if(clockCounter == 0) begin + if(ledCounter == 0) + assert($past(ledCounter) == 6'b11_1111); + else + assert(ledCounter == ($past(ledCounter)+1)); + end + end + +`endif // FORMAL + endmodule \ No newline at end of file diff --git a/counter/run_formal_verification.sh b/counter/run_formal_verification.sh new file mode 100644 index 0000000..a87664f --- /dev/null +++ b/counter/run_formal_verification.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +# Run SymbiYosis +sby -f counter.sby \ No newline at end of file diff --git a/screen/.gitignore b/screen/.gitignore new file mode 100644 index 0000000..013a8e8 --- /dev/null +++ b/screen/.gitignore @@ -0,0 +1,4 @@ +*.gprj.user +*.user +impl/ +screen/ \ No newline at end of file diff --git a/screen/screen.gprj b/screen/screen.gprj new file mode 100644 index 0000000..9153a3e --- /dev/null +++ b/screen/screen.gprj @@ -0,0 +1,11 @@ + + + + + 5 + gw1nr9c-004 + + + + + diff --git a/screen/screen.sby b/screen/screen.sby new file mode 100644 index 0000000..191ca52 --- /dev/null +++ b/screen/screen.sby @@ -0,0 +1,17 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DSCREEN -formal screen.v +prep -top screen + +[files] +screen.v +image.hex diff --git a/screen/screen.v b/screen/screen.v index 78525dd..ce18c40 100644 --- a/screen/screen.v +++ b/screen/screen.v @@ -1,141 +1,270 @@ -`default_nettype none - -module screen -#( - parameter STARTUP_WAIT = 32'd10000000 -) -( - input clk, - output io_sclk, - output io_sdin, - output io_cs, - output io_dc, - output io_reset -); - +module screen #( +`ifdef FORMAL + parameter STARTUP_WAIT = 32'd25 +`else + parameter STARTUP_WAIT = 32'd10000000 +`endif + ) + ( + input clk_i, + input reset_i, + // LEDs + output [5:0] led_o, + // OLED + output io_sclk_o, + output io_sdin_o, + output io_cs_o, + output io_dc_o, + output io_reset_o + ); localparam STATE_INIT_POWER = 8'd0; localparam STATE_LOAD_INIT_CMD = 8'd1; localparam STATE_SEND = 8'd2; localparam STATE_CHECK_FINISHED_INIT = 8'd3; localparam STATE_LOAD_DATA = 8'd4; - reg [32:0] counter = 0; - reg [2:0] state = 0; + localparam STARTUP_WAIT_2x = 2 * STARTUP_WAIT; + localparam STARTUP_WAIT_3x = 3 * STARTUP_WAIT; + localparam STARTUP_WAIT_MAX = STARTUP_WAIT_3x; + + localparam MAX_NUMBER_OF_PIXELS = 136; + + reg [32:0] counter = 0; + reg [2:0] state = STATE_INIT_POWER; + reg dc = 1; reg sclk = 1; reg sdin = 0; reg reset = 1; reg cs = 0; - + reg [7:0] dataToSend = 0; reg [3:0] bitNumber = 0; reg [9:0] pixelCounter = 0; localparam SETUP_INSTRUCTIONS = 23; reg [(SETUP_INSTRUCTIONS*8)-1:0] startupCommands = { - 8'hAE, // display off + 8'hAE, // display off + 8'h81, // contast value to 0x7F according to datasheet + 8'h7F, + 8'hA6, // normal screen mode (not inverted) + 8'h20, // horizontal addressing mode + 8'h00, + 8'hC8, // normal scan direction + 8'h40, // first line to start scanning from + 8'hA1, // address 0 is segment 0 + 8'hA8, // mux ratio + 8'h3f, // 63 (64 -1) + 8'hD3, // display offset + 8'h00, // no offset + 8'hD5, // clock divide ratio + 8'h80, // set to default ratio/osc frequency + 8'hD9, // set precharge + 8'h22, // switch precharge to 0x22 default + 8'hDB, // vcom deselect level + 8'h20, // 0x20 + 8'h8D, // charge pump config + 8'h14, // enable charge pump + 8'hA4, // resume RAM content + 8'hAF // display on + }; + reg [7:0] commandIndex = SETUP_INSTRUCTIONS * 8; - 8'h81, // contast value to 0x7F according to datasheet - 8'h7F, + reg [7:0] screenBuffer [1023:0]; + // initial $readmemh("image.hex", screenBuffer); - 8'hA6, // normal screen mode (not inverted) + assign io_sclk_o = sclk; + assign io_sdin_o = sdin; + assign io_dc_o = dc; + assign io_reset_o = reset; + assign io_cs_o = cs; - 8'h20, // horizontal addressing mode - 8'h00, + reg [5:0] debug_led = 6'b00_0000;; - 8'hC8, // normal scan direction + // State Machine + always @(posedge clk_i) begin + if(reset_i) begin + counter <= 0; + state <= STATE_INIT_POWER; + dc <= 1; + sclk <= 1; + sdin <= 0; + reset <= 1; + cs <= 0; + dataToSend <= 0; + bitNumber <= 0; + pixelCounter <= 0; + end else begin + debug_led <= 6'b00_0000; + case (state) + STATE_INIT_POWER: begin + debug_led[0] <= 1; + counter <= counter + 1; + if (counter < STARTUP_WAIT) + reset <= 1; + else if (counter < STARTUP_WAIT_2x) + reset <= 0; + else if (counter < STARTUP_WAIT_3x) + reset <= 1; + else begin + state <= STATE_LOAD_INIT_CMD; + counter <= 32'b0; + end + end + STATE_LOAD_INIT_CMD: begin + debug_led[1] <= 1; + dc <= 0; + dataToSend <= startupCommands[(commandIndex-1)-:8'd8]; + state <= STATE_SEND; + bitNumber <= 3'd7; + cs <= 0; + commandIndex <= commandIndex - 8'd8; + end + STATE_SEND: begin + debug_led[2] <= 1; + if (counter == 32'd0) begin + sclk <= 0; + sdin <= dataToSend[bitNumber]; + counter <= 32'd1; + end else begin + counter <= 32'd0; + sclk <= 1; + if (bitNumber == 0) + state <= STATE_CHECK_FINISHED_INIT; + else + bitNumber <= bitNumber - 1; + end + end + STATE_CHECK_FINISHED_INIT: begin + debug_led[3] <= 1; + cs <= 1; + if (commandIndex == 0) + state <= STATE_LOAD_DATA; + else + state <= STATE_LOAD_INIT_CMD; + end + STATE_LOAD_DATA: begin + debug_led[4] <= 1; + pixelCounter <= pixelCounter + 1; + cs <= 0; + dc <= 1; + bitNumber <= 3'd7; + state <= STATE_SEND; + if (pixelCounter < MAX_NUMBER_OF_PIXELS) + dataToSend <= 8'b01010111; + else + dataToSend <= 0; + end + endcase + end + end - 8'h40, // first line to start scanning from + assign led_o = ~debug_led; - 8'hA1, // address 0 is segment 0 - 8'hA8, // mux ratio - 8'h3f, // 63 (64 -1) +// +// FORMAL VERIFICATION +// +`ifdef FORMAL - 8'hD3, // display offset - 8'h00, // no offset + `ifdef SCREEN + `define ASSUME assume + `else + `define ASSUME assert + `endif - 8'hD5, // clock divide ratio - 8'h80, // set to default ratio/osc frequency + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; - 8'hD9, // set precharge - 8'h22, // switch precharge to 0x22 default + // Prove that state is always in a valid state + always@(*) + if((f_past_valid)&&(!reset_i)) + assert(state <= STATE_LOAD_DATA); - 8'hDB, // vcom deselect level - 8'h20, // 0x20 + // Prove that counter is always valid + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(counter <= STARTUP_WAIT_MAX); - 8'h8D, // charge pump config - 8'h14, // enable charge pump + // Prove that after a reset registers get initialized + always @(posedge clk_i) begin + if(($past(f_past_valid))&&($past(reset_i))) begin + assert(counter == 0); + assert(state == STATE_INIT_POWER); + assert(dc == 1); + assert(sclk == 1); + assert(sdin == 0); + assert(reset == 1); + assert(cs == 0); + assert(dataToSend == 0); + assert(bitNumber == 0); + assert(pixelCounter == 0); + end + end - 8'hA4, // resume RAM content + // Prove that led_o is assigned debug_led + always @(*) + assert(led_o == ~debug_led); - 8'hAF // display on - }; - reg [7:0] commandIndex = SETUP_INSTRUCTIONS * 8; + // + // Contract + // + always @(posedge clk_i) begin + if((f_past_valid)&&($past(f_past_valid))&&(!reset_i)&&(!$past(reset_i))) begin + case($past(state)) + STATE_INIT_POWER: begin + if(state == STATE_INIT_POWER) + assert(counter == ($past(counter)+1)); + // reset + if (counter <= STARTUP_WAIT) + assert(reset == 1); + else if (counter <= STARTUP_WAIT_2x) + assert(reset == 0); + else if (counter <= STARTUP_WAIT_3x) + assert(reset == 1); + end + STATE_LOAD_INIT_CMD: begin + assert(dc == 0); + assert(cs == 0); + assert(bitNumber == 3'd7); + assert(commandIndex == $past(commandIndex - 8'd8)); + assert(dataToSend == startupCommands[($past(commandIndex)-1)-:8'd8]); + end + STATE_SEND: begin + if ($past(counter) == 32'd0) begin + assert(sclk == 0); + assert(sdin == $past(dataToSend[bitNumber])); + assert(counter == 32'd1); + end else begin + assert(counter == 32'd0); + assert(sclk == 1); + if (bitNumber != 0) + assert(bitNumber == $past(bitNumber-1)); + end + end + STATE_CHECK_FINISHED_INIT: assert(cs == 1); + STATE_LOAD_DATA: begin + if(pixelCounter != 0) + assert(pixelCounter == $past(pixelCounter+1)); + assert(cs == 0); + assert(dc == 1); + assert(bitNumber == 3'd7); + if ($past(pixelCounter) < MAX_NUMBER_OF_PIXELS) + assert(dataToSend == 8'b01010111); + else + assert(dataToSend == 0); + end + default: assert(0); // We should never ever be here + endcase + end + end - assign io_sclk = sclk; - assign io_sdin = sdin; - assign io_dc = dc; - assign io_reset = reset; - assign io_cs = cs; - reg [7:0] screenBuffer [1023:0]; - initial $readmemh("image.hex", screenBuffer); - - always @(posedge clk) begin - case (state) - STATE_INIT_POWER: begin - counter <= counter + 1; - if (counter < STARTUP_WAIT) - reset <= 1; - else if (counter < STARTUP_WAIT * 2) - reset <= 0; - else if (counter < STARTUP_WAIT * 3) - reset <= 1; - else begin - state <= STATE_LOAD_INIT_CMD; - counter <= 32'b0; - end - end - STATE_LOAD_INIT_CMD: begin - dc <= 0; - dataToSend <= startupCommands[(commandIndex-1)-:8'd8]; - state <= STATE_SEND; - bitNumber <= 3'd7; - cs <= 0; - commandIndex <= commandIndex - 8'd8; - end - STATE_SEND: begin - if (counter == 32'd0) begin - sclk <= 0; - sdin <= dataToSend[bitNumber]; - counter <= 32'd1; - end - else begin - counter <= 32'd0; - sclk <= 1; - if (bitNumber == 0) - state <= STATE_CHECK_FINISHED_INIT; - else - bitNumber <= bitNumber - 1; - end - end - STATE_CHECK_FINISHED_INIT: begin - cs <= 1; - if (commandIndex == 0) - state <= STATE_LOAD_DATA; - else - state <= STATE_LOAD_INIT_CMD; - end - STATE_LOAD_DATA: begin - pixelCounter <= pixelCounter + 1; - cs <= 0; - dc <= 1; - bitNumber <= 3'd7; - state <= STATE_SEND; - dataToSend <= screenBuffer[pixelCounter]; - end - endcase - end -endmodule + +`endif // FORMAL + +endmodule \ No newline at end of file diff --git a/screen_data/.gitignore b/screen_data/.gitignore new file mode 100644 index 0000000..103a5d0 --- /dev/null +++ b/screen_data/.gitignore @@ -0,0 +1,8 @@ +*.gprj.user +*.user +impl/ +screen/ +text/ +progressRow/ +uartTextRow/ +uart/ \ No newline at end of file diff --git a/screen_data/GAO/screen.rao b/screen_data/GAO/screen.rao new file mode 100644 index 0000000..f8c9790 --- /dev/null +++ b/screen_data/GAO/screen.rao @@ -0,0 +1,15 @@ + + + 3.0 + Lite + + + ioSclk + ioSdin + ioCs + ioDc + ioReset + + + 1000010111111011 + diff --git a/screen_data/GAO/text.rao b/screen_data/GAO/text.rao new file mode 100644 index 0000000..35b2957 --- /dev/null +++ b/screen_data/GAO/text.rao @@ -0,0 +1,50 @@ + + + 3.0 + Lite + + + + pixelAddress[9] + pixelAddress[8] + pixelAddress[7] + pixelAddress[6] + pixelAddress[5] + pixelAddress[4] + pixelAddress[3] + pixelAddress[2] + pixelAddress[1] + pixelAddress[0] + + + textPixelData[7] + textPixelData[6] + textPixelData[5] + textPixelData[4] + textPixelData[3] + textPixelData[2] + textPixelData[1] + textPixelData[0] + + + charAddress[5] + charAddress[4] + charAddress[3] + charAddress[2] + charAddress[1] + charAddress[0] + + + charOutput[7] + charOutput[6] + charOutput[5] + charOutput[4] + charOutput[3] + charOutput[2] + charOutput[1] + charOutput[0] + + + + 0011011011101101 + diff --git a/screen_data/GAO/uart.rao b/screen_data/GAO/uart.rao new file mode 100644 index 0000000..6bc33f5 --- /dev/null +++ b/screen_data/GAO/uart.rao @@ -0,0 +1,22 @@ + + + 3.0 + Lite + + + + uartDataIn[7] + uartDataIn[6] + uartDataIn[5] + uartDataIn[4] + uartDataIn[3] + uartDataIn[2] + uartDataIn[1] + uartDataIn[0] + + uartRx + uartByteReady + + + 0000000010011100 + diff --git a/screen_data/hexDecRow.sby b/screen_data/hexDecRow.sby new file mode 100644 index 0000000..2713007 --- /dev/null +++ b/screen_data/hexDecRow.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DHEX_DEC_ROW -formal rows.v +prep -top hexDecRow + +[files] +rows.v diff --git a/screen_data/hexDecRow/PASS b/screen_data/hexDecRow/PASS new file mode 100644 index 0000000..953a139 --- /dev/null +++ b/screen_data/hexDecRow/PASS @@ -0,0 +1,6 @@ +Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0) +Elapsed process time [H:MM:SS (secs)]: 0:00:00 (0) +engine_0 (smtbmc) returned pass for basecase +engine_0 (smtbmc) returned pass for induction +engine_0 did not produce any traces +successful proof by k-induction. diff --git a/screen_data/hexDecRow/config.sby b/screen_data/hexDecRow/config.sby new file mode 100644 index 0000000..2713007 --- /dev/null +++ b/screen_data/hexDecRow/config.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DHEX_DEC_ROW -formal rows.v +prep -top hexDecRow + +[files] +rows.v diff --git a/screen_data/hexDecRow/engine_0/logfile_basecase.txt b/screen_data/hexDecRow/engine_0/logfile_basecase.txt new file mode 100644 index 0000000..b4f092a --- /dev/null +++ b/screen_data/hexDecRow/engine_0/logfile_basecase.txt @@ -0,0 +1,52 @@ +## 0:00:00 Solver: yices +## 0:00:00 Checking assumptions in step 0.. +## 0:00:00 Checking assertions in step 0.. +## 0:00:00 Checking assumptions in step 1.. +## 0:00:00 Checking assertions in step 1.. +## 0:00:00 Checking assumptions in step 2.. +## 0:00:00 Checking assertions in step 2.. +## 0:00:00 Checking assumptions in step 3.. +## 0:00:00 Checking assertions in step 3.. +## 0:00:00 Checking assumptions in step 4.. +## 0:00:00 Checking assertions in step 4.. +## 0:00:00 Checking assumptions in step 5.. +## 0:00:00 Checking assertions in step 5.. +## 0:00:00 Checking assumptions in step 6.. +## 0:00:00 Checking assertions in step 6.. +## 0:00:00 Checking assumptions in step 7.. +## 0:00:00 Checking assertions in step 7.. +## 0:00:00 Checking assumptions in step 8.. +## 0:00:00 Checking assertions in step 8.. +## 0:00:00 Checking assumptions in step 9.. +## 0:00:00 Checking assertions in step 9.. +## 0:00:00 Checking assumptions in step 10.. +## 0:00:00 Checking assertions in step 10.. +## 0:00:00 Checking assumptions in step 11.. +## 0:00:00 Checking assertions in step 11.. +## 0:00:00 Checking assumptions in step 12.. +## 0:00:00 Checking assertions in step 12.. +## 0:00:00 Checking assumptions in step 13.. +## 0:00:00 Checking assertions in step 13.. +## 0:00:00 Checking assumptions in step 14.. +## 0:00:00 Checking assertions in step 14.. +## 0:00:00 Checking assumptions in step 15.. +## 0:00:00 Checking assertions in step 15.. +## 0:00:00 Checking assumptions in step 16.. +## 0:00:00 Checking assertions in step 16.. +## 0:00:00 Checking assumptions in step 17.. +## 0:00:00 Checking assertions in step 17.. +## 0:00:00 Checking assumptions in step 18.. +## 0:00:00 Checking assertions in step 18.. +## 0:00:00 Checking assumptions in step 19.. +## 0:00:00 Checking assertions in step 19.. +## 0:00:00 Checking assumptions in step 20.. +## 0:00:00 Checking assertions in step 20.. +## 0:00:00 Checking assumptions in step 21.. +## 0:00:00 Checking assertions in step 21.. +## 0:00:00 Checking assumptions in step 22.. +## 0:00:00 Checking assertions in step 22.. +## 0:00:00 Checking assumptions in step 23.. +## 0:00:00 Checking assertions in step 23.. +## 0:00:00 Checking assumptions in step 24.. +## 0:00:00 Checking assertions in step 24.. +## 0:00:00 Status: passed diff --git a/screen_data/hexDecRow/engine_0/logfile_induction.txt b/screen_data/hexDecRow/engine_0/logfile_induction.txt new file mode 100644 index 0000000..8b0d178 --- /dev/null +++ b/screen_data/hexDecRow/engine_0/logfile_induction.txt @@ -0,0 +1,6 @@ +## 0:00:00 Solver: yices +## 0:00:00 Trying induction in step 25.. +## 0:00:00 Trying induction in step 24.. +## 0:00:00 Trying induction in step 23.. +## 0:00:00 Temporal induction successful. +## 0:00:00 Status: passed diff --git a/screen_data/hexDecRow/hexDecRow.xml b/screen_data/hexDecRow/hexDecRow.xml new file mode 100644 index 0000000..ab3179e --- /dev/null +++ b/screen_data/hexDecRow/hexDecRow.xml @@ -0,0 +1,107 @@ + + + + + + + + + + + + + + + + + + + + + + +SBY 11:45:22 [hexDecRow] Removing directory '/mnt/c/Workspace/NES/NESTang/tangnano9k-series-examples/screen_data/hexDecRow'. +SBY 11:45:22 [hexDecRow] Copy '/mnt/c/Workspace/NES/NESTang/tangnano9k-series-examples/screen_data/rows.v' to '/mnt/c/Workspace/NES/NESTang/tangnano9k-series-examples/screen_data/hexDecRow/src/rows.v'. +SBY 11:45:22 [hexDecRow] engine_0: smtbmc +SBY 11:45:22 [hexDecRow] base: starting process "cd hexDecRow/src; yosys -ql ../model/design.log ../model/design.ys" +SBY 11:45:22 [hexDecRow] base: finished (returncode=0) +SBY 11:45:22 [hexDecRow] prep: starting process "cd hexDecRow/model; yosys -ql design_prep.log design_prep.ys" +SBY 11:45:22 [hexDecRow] prep: finished (returncode=0) +SBY 11:45:22 [hexDecRow] smt2: starting process "cd hexDecRow/model; yosys -ql design_smt2.log design_smt2.ys" +SBY 11:45:22 [hexDecRow] smt2: finished (returncode=0) +SBY 11:45:22 [hexDecRow] engine_0.basecase: starting process "cd hexDecRow; yosys-smtbmc --presat --unroll --noprogress -t 25 --append 0 --dump-vcd engine_0/trace.vcd --dump-yw engine_0/trace.yw --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" +SBY 11:45:22 [hexDecRow] engine_0.induction: starting process "cd hexDecRow; yosys-smtbmc --presat --unroll -i --noprogress -t 25 --append 0 --dump-vcd engine_0/trace_induct.vcd --dump-yw engine_0/trace_induct.yw --dump-vlogtb engine_0/trace_induct_tb.v --dump-smtc engine_0/trace_induct.smtc model/design_smt2.smt2" +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Solver: yices +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Solver: yices +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 0.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 0.. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Trying induction in step 25.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 1.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 1.. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Trying induction in step 24.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 2.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 2.. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Trying induction in step 23.. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Temporal induction successful. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Status: passed +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 3.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 3.. +SBY 11:45:22 [hexDecRow] engine_0.induction: finished (returncode=0) +SBY 11:45:22 [hexDecRow] engine_0.induction: Status returned by engine for induction: pass +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 4.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 4.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 5.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 5.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 6.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 6.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 7.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 7.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 8.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 8.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 9.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 9.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 10.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 10.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 11.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 11.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 12.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 12.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 13.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 13.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 14.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 14.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 15.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 15.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 16.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 16.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 17.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 17.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 18.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 18.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 19.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 19.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 20.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 20.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 21.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 21.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 22.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 22.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 23.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 23.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 24.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 24.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Status: passed +SBY 11:45:22 [hexDecRow] engine_0.basecase: finished (returncode=0) +SBY 11:45:22 [hexDecRow] engine_0.basecase: Status returned by engine for basecase: pass +SBY 11:45:22 [hexDecRow] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0) +SBY 11:45:22 [hexDecRow] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:00 (0) +SBY 11:45:22 [hexDecRow] summary: engine_0 (smtbmc) returned pass for basecase +SBY 11:45:22 [hexDecRow] summary: engine_0 (smtbmc) returned pass for induction +SBY 11:45:22 [hexDecRow] summary: engine_0 did not produce any traces +SBY 11:45:22 [hexDecRow] summary: successful proof by k-induction. +SBY 11:45:22 [hexDecRow] DONE (PASS, rc=0) + + + + + diff --git a/screen_data/hexDecRow/logfile.txt b/screen_data/hexDecRow/logfile.txt new file mode 100644 index 0000000..e52291e --- /dev/null +++ b/screen_data/hexDecRow/logfile.txt @@ -0,0 +1,80 @@ +SBY 11:45:22 [hexDecRow] Removing directory '/mnt/c/Workspace/NES/NESTang/tangnano9k-series-examples/screen_data/hexDecRow'. +SBY 11:45:22 [hexDecRow] Copy '/mnt/c/Workspace/NES/NESTang/tangnano9k-series-examples/screen_data/rows.v' to '/mnt/c/Workspace/NES/NESTang/tangnano9k-series-examples/screen_data/hexDecRow/src/rows.v'. +SBY 11:45:22 [hexDecRow] engine_0: smtbmc +SBY 11:45:22 [hexDecRow] base: starting process "cd hexDecRow/src; yosys -ql ../model/design.log ../model/design.ys" +SBY 11:45:22 [hexDecRow] base: finished (returncode=0) +SBY 11:45:22 [hexDecRow] prep: starting process "cd hexDecRow/model; yosys -ql design_prep.log design_prep.ys" +SBY 11:45:22 [hexDecRow] prep: finished (returncode=0) +SBY 11:45:22 [hexDecRow] smt2: starting process "cd hexDecRow/model; yosys -ql design_smt2.log design_smt2.ys" +SBY 11:45:22 [hexDecRow] smt2: finished (returncode=0) +SBY 11:45:22 [hexDecRow] engine_0.basecase: starting process "cd hexDecRow; yosys-smtbmc --presat --unroll --noprogress -t 25 --append 0 --dump-vcd engine_0/trace.vcd --dump-yw engine_0/trace.yw --dump-vlogtb engine_0/trace_tb.v --dump-smtc engine_0/trace.smtc model/design_smt2.smt2" +SBY 11:45:22 [hexDecRow] engine_0.induction: starting process "cd hexDecRow; yosys-smtbmc --presat --unroll -i --noprogress -t 25 --append 0 --dump-vcd engine_0/trace_induct.vcd --dump-yw engine_0/trace_induct.yw --dump-vlogtb engine_0/trace_induct_tb.v --dump-smtc engine_0/trace_induct.smtc model/design_smt2.smt2" +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Solver: yices +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Solver: yices +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 0.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 0.. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Trying induction in step 25.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 1.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 1.. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Trying induction in step 24.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 2.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 2.. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Trying induction in step 23.. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Temporal induction successful. +SBY 11:45:22 [hexDecRow] engine_0.induction: ## 0:00:00 Status: passed +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 3.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 3.. +SBY 11:45:22 [hexDecRow] engine_0.induction: finished (returncode=0) +SBY 11:45:22 [hexDecRow] engine_0.induction: Status returned by engine for induction: pass +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 4.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 4.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 5.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 5.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 6.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 6.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 7.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 7.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 8.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 8.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 9.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 9.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 10.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 10.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 11.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 11.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 12.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 12.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 13.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 13.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 14.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 14.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 15.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 15.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 16.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 16.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 17.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 17.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 18.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 18.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 19.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 19.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 20.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 20.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 21.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 21.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 22.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 22.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 23.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 23.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assumptions in step 24.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Checking assertions in step 24.. +SBY 11:45:22 [hexDecRow] engine_0.basecase: ## 0:00:00 Status: passed +SBY 11:45:22 [hexDecRow] engine_0.basecase: finished (returncode=0) +SBY 11:45:22 [hexDecRow] engine_0.basecase: Status returned by engine for basecase: pass +SBY 11:45:22 [hexDecRow] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0) +SBY 11:45:22 [hexDecRow] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:00 (0) +SBY 11:45:22 [hexDecRow] summary: engine_0 (smtbmc) returned pass for basecase +SBY 11:45:22 [hexDecRow] summary: engine_0 (smtbmc) returned pass for induction +SBY 11:45:22 [hexDecRow] summary: engine_0 did not produce any traces +SBY 11:45:22 [hexDecRow] summary: successful proof by k-induction. +SBY 11:45:22 [hexDecRow] DONE (PASS, rc=0) diff --git a/screen_data/hexDecRow/model/design.il b/screen_data/hexDecRow/model/design.il new file mode 100644 index 0000000..85ba1af --- /dev/null +++ b/screen_data/hexDecRow/model/design.il @@ -0,0 +1,1260 @@ +# Generated by Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) +autoidx 535 +attribute \keep 1 +attribute \top 1 +attribute \src "rows.v:180.1-260.10" +module \hexDecRow + attribute \src "rows.v:239.9-241.49" + wire $0$formal$rows.v:240$184_CHECK[0:0]$193 + attribute \src "rows.v:239.9-241.49" + wire $0$formal$rows.v:240$184_EN[0:0]$194 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:249$185_CHECK[0:0]$203 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:249$185_EN[0:0]$204 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:250$186_CHECK[0:0]$205 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:250$186_EN[0:0]$206 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:251$187_CHECK[0:0]$207 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:251$187_EN[0:0]$208 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:252$188_CHECK[0:0]$209 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:252$188_EN[0:0]$210 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:253$189_CHECK[0:0]$211 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:253$189_EN[0:0]$212 + attribute \src "rows.v:200.5-217.8" + wire width 8 $0\outByteReg[7:0] + wire $auto$opt_reduce.cc:134:opt_pmux$522 + wire $auto$opt_reduce.cc:134:opt_pmux$524 + attribute \src "rows.v:249.31-249.65" + wire $eq$rows.v:249$213_Y + attribute \src "rows.v:250.31-250.64" + wire $eq$rows.v:250$214_Y + attribute \src "rows.v:251.32-251.61" + wire $eq$rows.v:251$215_Y + attribute \src "rows.v:252.32-252.61" + wire $eq$rows.v:252$216_Y + attribute \src "rows.v:253.32-253.61" + wire $eq$rows.v:253$217_Y + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:249$185_CHECK + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:249$185_EN + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:250$186_CHECK + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:250$186_EN + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:251$187_CHECK + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:251$187_EN + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:252$188_CHECK + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:252$188_EN + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:253$189_CHECK + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:253$189_EN + attribute \src "rows.v:0.0-0.0" + wire width 4 $past$rows.v:248$178$0 + attribute \src "rows.v:0.0-0.0" + wire width 8 $past$rows.v:249$179$0 + attribute \src "rows.v:0.0-0.0" + wire width 8 $past$rows.v:250$180$0 + attribute \src "rows.v:0.0-0.0" + wire width 8 $past$rows.v:251$181$0 + attribute \src "rows.v:0.0-0.0" + wire width 8 $past$rows.v:252$182$0 + attribute \src "rows.v:0.0-0.0" + wire width 8 $past$rows.v:253$183$0 + wire $procmux$390_Y + wire $procmux$391_CMP + wire $procmux$398_Y + wire $procmux$405_Y + wire $procmux$406_CMP + wire $procmux$412_Y + wire $procmux$418_Y + wire $procmux$419_CMP + wire $procmux$424_Y + wire $procmux$429_Y + wire $procmux$430_CMP + wire $procmux$434_Y + wire $procmux$438_Y + wire $procmux$439_CMP + wire $procmux$442_Y + wire $procmux$452_CMP + wire $procmux$453_CMP + wire $procmux$454_CMP + wire $procmux$455_CMP + wire $procmux$456_CMP + wire $procmux$457_CMP + wire $procmux$458_CMP + wire $procmux$459_CMP + wire $procmux$460_CMP + wire $procmux$461_CMP + wire $procmux$462_CMP + wire $procmux$463_CMP + wire $procmux$464_CMP + attribute \src "rows.v:181.11-181.16" + wire input 1 \clk_i + attribute \src "rows.v:197.16-197.24" + wire width 8 \decChar1 + attribute \src "rows.v:197.26-197.34" + wire width 8 \decChar2 + attribute \src "rows.v:197.36-197.44" + wire width 8 \decChar3 + attribute \init 1'0 + attribute \src "rows.v:233.13-233.25" + wire \f_past_valid + attribute \src "rows.v:188.26-188.35" + wire width 4 \hexHigher + attribute \src "rows.v:188.16-188.24" + wire width 4 \hexLower + attribute \src "rows.v:189.30-189.43" + wire width 8 \higherHexChar + attribute \src "rows.v:189.16-189.28" + wire width 8 \lowerHexChar + attribute \src "rows.v:186.15-186.25" + wire width 8 \outByteReg + attribute \src "rows.v:184.18-184.27" + wire width 8 output 4 \outByte_i + attribute \src "rows.v:183.17-183.34" + wire width 4 input 3 \outputCharIndex_i + attribute \src "rows.v:182.17-182.24" + wire width 8 input 2 \value_i + attribute \src "rows.v:240.29-241.48" + cell $assert $assert$rows.v:240$218 + connect \A $0$formal$rows.v:240$184_CHECK[0:0]$193 + connect \EN $0$formal$rows.v:240$184_EN[0:0]$194 + end + attribute \src "rows.v:249.23-249.66" + cell $assert $assert$rows.v:249$219 + connect \A $formal$rows.v:249$185_CHECK + connect \EN $formal$rows.v:249$185_EN + end + attribute \src "rows.v:250.23-250.65" + cell $assert $assert$rows.v:250$220 + connect \A $formal$rows.v:250$186_CHECK + connect \EN $formal$rows.v:250$186_EN + end + attribute \src "rows.v:251.24-251.62" + cell $assert $assert$rows.v:251$221 + connect \A $formal$rows.v:251$187_CHECK + connect \EN $formal$rows.v:251$187_EN + end + attribute \src "rows.v:252.24-252.62" + cell $assert $assert$rows.v:252$222 + connect \A $formal$rows.v:252$188_CHECK + connect \EN $formal$rows.v:252$188_EN + end + attribute \src "rows.v:253.24-253.62" + cell $assert $assert$rows.v:253$223 + connect \A $formal$rows.v:253$189_CHECK + connect \EN $formal$rows.v:253$189_EN + end + cell $reduce_or $auto$opt_reduce.cc:128:opt_pmux$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { $procmux$455_CMP $procmux$461_CMP } + connect \Y $auto$opt_reduce.cc:134:opt_pmux$522 + end + cell $reduce_or $auto$opt_reduce.cc:128:opt_pmux$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { $procmux$457_CMP $procmux$463_CMP } + connect \Y $auto$opt_reduce.cc:134:opt_pmux$524 + end + attribute \src "rows.v:249.31-249.65" + cell $eq $eq$rows.v:249$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B $past$rows.v:249$179$0 + connect \Y $eq$rows.v:249$213_Y + end + attribute \src "rows.v:250.31-250.64" + cell $eq $eq$rows.v:250$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B $past$rows.v:250$180$0 + connect \Y $eq$rows.v:250$214_Y + end + attribute \src "rows.v:251.32-251.61" + cell $eq $eq$rows.v:251$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B $past$rows.v:251$181$0 + connect \Y $eq$rows.v:251$215_Y + end + attribute \src "rows.v:252.32-252.61" + cell $eq $eq$rows.v:252$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B $past$rows.v:252$182$0 + connect \Y $eq$rows.v:252$216_Y + end + attribute \src "rows.v:253.32-253.61" + cell $eq $eq$rows.v:253$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B $past$rows.v:253$183$0 + connect \Y $eq$rows.v:253$217_Y + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$496 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 4 + connect \CLK \clk_i + connect \D \outputCharIndex_i + connect \Q $past$rows.v:248$178$0 + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$497 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D \higherHexChar + connect \Q $past$rows.v:249$179$0 + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$498 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D \lowerHexChar + connect \Q $past$rows.v:250$180$0 + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$499 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D \decChar1 + connect \Q $past$rows.v:251$181$0 + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$500 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D \decChar2 + connect \Q $past$rows.v:252$182$0 + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$501 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D \decChar3 + connect \Q $past$rows.v:253$183$0 + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$502 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:249$185_CHECK[0:0]$203 + connect \Q $formal$rows.v:249$185_CHECK + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$503 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:249$185_EN[0:0]$204 + connect \Q $formal$rows.v:249$185_EN + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$504 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:250$186_CHECK[0:0]$205 + connect \Q $formal$rows.v:250$186_CHECK + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$505 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:250$186_EN[0:0]$206 + connect \Q $formal$rows.v:250$186_EN + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$506 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:251$187_CHECK[0:0]$207 + connect \Q $formal$rows.v:251$187_CHECK + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$507 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:251$187_EN[0:0]$208 + connect \Q $formal$rows.v:251$187_EN + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$508 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:252$188_CHECK[0:0]$209 + connect \Q $formal$rows.v:252$188_CHECK + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$509 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:252$188_EN[0:0]$210 + connect \Q $formal$rows.v:252$188_EN + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$510 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:253$189_CHECK[0:0]$211 + connect \Q $formal$rows.v:253$189_CHECK + end + attribute \src "rows.v:246.9-256.12" + cell $dff $procdff$511 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D $0$formal$rows.v:253$189_EN[0:0]$212 + connect \Q $formal$rows.v:253$189_EN + end + attribute \src "rows.v:235.9-236.34" + cell $dff $procdff$512 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk_i + connect \D 1'1 + connect \Q \f_past_valid + end + attribute \src "rows.v:200.5-217.8" + cell $dff $procdff$513 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D $0\outByteReg[7:0] + connect \Q \outByteReg + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$390 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$391_CMP + connect \Y $procmux$390_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$391_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $past$rows.v:248$178$0 + connect \B 3'101 + connect \Y $procmux$391_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$392 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$390_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:249$185_EN[0:0]$204 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$398 + parameter \WIDTH 1 + connect \A 1'x + connect \B $eq$rows.v:249$213_Y + connect \S $procmux$391_CMP + connect \Y $procmux$398_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$400 + parameter \WIDTH 1 + connect \A 1'x + connect \B $procmux$398_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:249$185_CHECK[0:0]$203 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$405 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$406_CMP + connect \Y $procmux$405_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$406_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $past$rows.v:248$178$0 + connect \B 3'110 + connect \Y $procmux$406_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$407 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$405_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:250$186_EN[0:0]$206 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$412 + parameter \WIDTH 1 + connect \A 1'x + connect \B $eq$rows.v:250$214_Y + connect \S $procmux$406_CMP + connect \Y $procmux$412_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$414 + parameter \WIDTH 1 + connect \A 1'x + connect \B $procmux$412_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:250$186_CHECK[0:0]$205 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$418 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$419_CMP + connect \Y $procmux$418_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$419_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A $past$rows.v:248$178$0 + connect \B 4'1101 + connect \Y $procmux$419_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$420 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$418_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:251$187_EN[0:0]$208 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$424 + parameter \WIDTH 1 + connect \A 1'x + connect \B $eq$rows.v:251$215_Y + connect \S $procmux$419_CMP + connect \Y $procmux$424_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$426 + parameter \WIDTH 1 + connect \A 1'x + connect \B $procmux$424_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:251$187_CHECK[0:0]$207 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$429 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$430_CMP + connect \Y $procmux$429_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$430_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A $past$rows.v:248$178$0 + connect \B 4'1110 + connect \Y $procmux$430_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$431 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$429_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:252$188_EN[0:0]$210 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$434 + parameter \WIDTH 1 + connect \A 1'x + connect \B $eq$rows.v:252$216_Y + connect \S $procmux$430_CMP + connect \Y $procmux$434_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$436 + parameter \WIDTH 1 + connect \A 1'x + connect \B $procmux$434_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:252$188_CHECK[0:0]$209 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$438 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$439_CMP + connect \Y $procmux$438_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$439_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A $past$rows.v:248$178$0 + connect \B 4'1111 + connect \Y $procmux$439_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$440 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$438_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:253$189_EN[0:0]$212 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$442 + parameter \WIDTH 1 + connect \A 1'x + connect \B $eq$rows.v:253$217_Y + connect \S $procmux$439_CMP + connect \Y $procmux$442_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$444 + parameter \WIDTH 1 + connect \A 1'x + connect \B $procmux$442_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:253$189_CHECK[0:0]$211 + end + attribute \src "rows.v:240.16-240.28|rows.v:240.13-241.49" + cell $mux $procmux$446 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \f_past_valid + connect \Y $0$formal$rows.v:240$184_EN[0:0]$194 + end + attribute \src "rows.v:240.16-240.28|rows.v:240.13-241.49" + cell $mux $procmux$448 + parameter \WIDTH 1 + connect \A 1'x + connect \B 1'1 + connect \S \f_past_valid + connect \Y $0$formal$rows.v:240$184_CHECK[0:0]$193 + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $pmux $procmux$451 + parameter \S_WIDTH 11 + parameter \WIDTH 8 + connect \A 8'00100000 + connect \B { 16'0100100001111000 \higherHexChar \lowerHexChar 32'01000100011001010110001100111010 \decChar1 \decChar2 \decChar3 } + connect \S { $procmux$464_CMP $procmux$462_CMP $procmux$460_CMP $procmux$459_CMP $procmux$458_CMP $auto$opt_reduce.cc:134:opt_pmux$524 $procmux$456_CMP $auto$opt_reduce.cc:134:opt_pmux$522 $procmux$454_CMP $procmux$453_CMP $procmux$452_CMP } + connect \Y $0\outByteReg[7:0] + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$452_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1111 + connect \Y $procmux$452_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$453_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1110 + connect \Y $procmux$453_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$454_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1101 + connect \Y $procmux$454_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$455_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1011 + connect \Y $procmux$455_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$456_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1010 + connect \Y $procmux$456_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$457_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1001 + connect \Y $procmux$457_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$458_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1000 + connect \Y $procmux$458_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$459_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 3'110 + connect \Y $procmux$459_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$460_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 3'101 + connect \Y $procmux$460_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$461_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 2'11 + connect \Y $procmux$461_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$462_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 2'10 + connect \Y $procmux$462_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$463_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 1'1 + connect \Y $procmux$463_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $logic_not $procmux$464_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \Y $procmux$464_CMP + end + attribute \module_not_derived 1 + attribute \src "rows.v:198.11-198.60" + cell \toDec \dec + connect \clk_i \clk_i + connect \hundreds \decChar1 + connect \tens \decChar2 + connect \units \decChar3 + connect \value \value_i + end + attribute \module_not_derived 1 + attribute \src "rows.v:194.11-194.44" + cell \toHex \h1 + connect \clk_i \clk_i + connect \hexChar \lowerHexChar + connect \value \value_i [3:0] + end + attribute \module_not_derived 1 + attribute \src "rows.v:195.11-195.46" + cell \toHex \h2 + connect \clk_i \clk_i + connect \hexChar \higherHexChar + connect \value \value_i [7:4] + end + connect \hexHigher \value_i [7:4] + connect \hexLower \value_i [3:0] + connect \outByte_i \outByteReg +end +attribute \src "rows.v:130.1-177.10" +module \toDec + attribute \src "rows.v:147.5-176.8" + wire width 8 $0\cachedValue[7:0] + attribute \src "rows.v:147.5-176.8" + wire width 12 $0\digits[11:0] + attribute \src "rows.v:147.5-176.8" + wire width 8 $0\hundreds[7:0] + attribute \src "rows.v:147.5-176.8" + wire width 4 $0\state[3:0] + attribute \src "rows.v:147.5-176.8" + wire width 4 $0\stepCounter[3:0] + attribute \src "rows.v:147.5-176.8" + wire width 8 $0\tens[7:0] + attribute \src "rows.v:147.5-176.8" + wire width 8 $0\units[7:0] + attribute \src "rows.v:156.27-156.72" + wire width 12 $add$rows.v:156$159_Y + attribute \src "rows.v:156.27-156.112" + wire width 12 $add$rows.v:156$162_Y + attribute \src "rows.v:156.27-156.154" + wire width 12 $add$rows.v:156$165_Y + wire width 4 $add$rows.v:166$167_Y + wire width 7 $add$rows.v:170$168_Y + wire width 7 $add$rows.v:171$169_Y + wire width 7 $add$rows.v:172$170_Y + wire width 4 $auto$wreduce.cc:461:run$529 + attribute \src "rows.v:156.37-156.71" + wire width 12 $auto$wreduce.cc:461:run$530 + attribute \src "rows.v:156.76-156.111" + wire width 12 $auto$wreduce.cc:461:run$531 + attribute \src "rows.v:162.21-162.37" + wire $eq$rows.v:162$166_Y + attribute \src "rows.v:156.38-156.54" + wire $ge$rows.v:156$157_Y + attribute \src "rows.v:156.77-156.93" + wire $ge$rows.v:156$160_Y + attribute \src "rows.v:156.117-156.134" + wire $ge$rows.v:156$163_Y + wire width 4 $procmux$467_Y + wire $procmux$470_CMP + wire $procmux$471_CMP + wire $procmux$479_CMP + wire $procmux$482_CMP + attribute \src "rows.v:156.116-156.153" + wire width 12 $ternary$rows.v:156$164_Y + attribute \init 8'00000000 + attribute \src "rows.v:138.15-138.26" + wire width 8 \cachedValue + attribute \src "rows.v:131.11-131.16" + wire input 1 \clk_i + attribute \init 12'000000000000 + attribute \src "rows.v:137.16-137.22" + wire width 12 \digits + attribute \init 8'00110000 + attribute \src "rows.v:133.22-133.30" + wire width 8 output 3 \hundreds + attribute \init 4'0000 + attribute \src "rows.v:140.15-140.20" + wire width 4 \state + attribute \init 4'0000 + attribute \src "rows.v:139.15-139.26" + wire width 4 \stepCounter + attribute \init 8'00110000 + attribute \src "rows.v:134.22-134.26" + wire width 8 output 4 \tens + attribute \init 8'00110000 + attribute \src "rows.v:135.22-135.27" + wire width 8 output 5 \units + attribute \src "rows.v:132.17-132.22" + wire width 8 input 2 \value + attribute \src "rows.v:156.27-156.72" + cell $add $add$rows.v:156$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 12 + connect \A \digits + connect \B $auto$wreduce.cc:461:run$530 [1:0] + connect \Y $add$rows.v:156$159_Y + end + attribute \src "rows.v:156.27-156.112" + cell $add $add$rows.v:156$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 12 + connect \A $add$rows.v:156$159_Y + connect \B $auto$wreduce.cc:461:run$531 [5:0] + connect \Y $add$rows.v:156$162_Y + end + attribute \src "rows.v:156.27-156.154" + cell $add $add$rows.v:156$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 12 + connect \A $add$rows.v:156$162_Y + connect \B $ternary$rows.v:156$164_Y [9:0] + connect \Y $add$rows.v:156$165_Y + end + attribute \src "rows.v:166.36-166.51" + cell $add $add$rows.v:166$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \stepCounter + connect \B 1'1 + connect \Y $add$rows.v:166$167_Y + end + attribute \src "rows.v:170.29-170.49" + cell $add $add$rows.v:170$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110000 + connect \B \digits [11:8] + connect \Y $add$rows.v:170$168_Y + end + attribute \src "rows.v:171.25-171.44" + cell $add $add$rows.v:171$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110000 + connect \B \digits [7:4] + connect \Y $add$rows.v:171$169_Y + end + attribute \src "rows.v:172.26-172.45" + cell $add $add$rows.v:172$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110000 + connect \B \digits [3:0] + connect \Y $add$rows.v:172$170_Y + end + attribute \src "rows.v:162.21-162.37" + cell $eq $eq$rows.v:162$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \stepCounter + connect \B 3'111 + connect \Y $eq$rows.v:162$166_Y + end + attribute \src "rows.v:156.38-156.54" + cell $ge $ge$rows.v:156$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \digits [3:0] + connect \B 3'101 + connect \Y $ge$rows.v:156$157_Y + end + attribute \src "rows.v:156.77-156.93" + cell $ge $ge$rows.v:156$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \digits [7:4] + connect \B 3'101 + connect \Y $ge$rows.v:156$160_Y + end + attribute \src "rows.v:156.117-156.134" + cell $ge $ge$rows.v:156$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \digits [11:8] + connect \B 3'101 + connect \Y $ge$rows.v:156$163_Y + end + attribute \src "rows.v:147.5-176.8" + cell $dff $procdff$514 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 4 + connect \CLK \clk_i + connect \D $0\state[3:0] + connect \Q \state + end + attribute \src "rows.v:147.5-176.8" + cell $dff $procdff$515 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D $0\hundreds[7:0] + connect \Q \hundreds + end + attribute \src "rows.v:147.5-176.8" + cell $dff $procdff$516 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D $0\tens[7:0] + connect \Q \tens + end + attribute \src "rows.v:147.5-176.8" + cell $dff $procdff$517 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D $0\units[7:0] + connect \Q \units + end + attribute \src "rows.v:147.5-176.8" + cell $dff $procdff$518 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 12 + connect \CLK \clk_i + connect \D $0\digits[11:0] + connect \Q \digits + end + attribute \src "rows.v:147.5-176.8" + cell $dff $procdff$519 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D $0\cachedValue[7:0] + connect \Q \cachedValue + end + attribute \src "rows.v:147.5-176.8" + cell $dff $procdff$520 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 4 + connect \CLK \clk_i + connect \D $0\stepCounter[3:0] + connect \Q \stepCounter + end + attribute \full_case 1 + attribute \src "rows.v:162.21-162.37|rows.v:162.17-167.20" + cell $mux $procmux$467 + parameter \WIDTH 4 + connect \A $add$rows.v:166$167_Y + connect \B \stepCounter + connect \S $eq$rows.v:162$166_Y + connect \Y $procmux$467_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $pmux $procmux$469 + parameter \S_WIDTH 2 + parameter \WIDTH 4 + connect \A \stepCounter + connect \B { 4'0000 $procmux$467_Y } + connect \S { $procmux$471_CMP $procmux$470_CMP } + connect \Y $0\stepCounter[3:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $eq $procmux$470_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \state + connect \B 2'10 + connect \Y $procmux$470_CMP + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $logic_not $procmux$471_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \state + connect \Y $procmux$471_CMP + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $pmux $procmux$473 + parameter \S_WIDTH 2 + parameter \WIDTH 8 + connect \A \cachedValue + connect \B { \value \cachedValue [6:0] 1'0 } + connect \S { $procmux$471_CMP $procmux$470_CMP } + connect \Y $0\cachedValue[7:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $pmux $procmux$477 + parameter \S_WIDTH 3 + parameter \WIDTH 12 + connect \A \digits + connect \B { 12'000000000000 $add$rows.v:156$165_Y \digits [10:0] \cachedValue [7] } + connect \S { $procmux$471_CMP $procmux$479_CMP $procmux$470_CMP } + connect \Y $0\digits[11:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $eq $procmux$479_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \state + connect \B 1'1 + connect \Y $procmux$479_CMP + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $mux $procmux$481 + parameter \WIDTH 8 + connect \A \units + connect \B { 1'0 $add$rows.v:172$170_Y } + connect \S $procmux$482_CMP + connect \Y $0\units[7:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $eq $procmux$482_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \state + connect \B 2'11 + connect \Y $procmux$482_CMP + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $mux $procmux$483 + parameter \WIDTH 8 + connect \A \tens + connect \B { 1'0 $add$rows.v:171$169_Y } + connect \S $procmux$482_CMP + connect \Y $0\tens[7:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $mux $procmux$485 + parameter \WIDTH 8 + connect \A \hundreds + connect \B { 1'0 $add$rows.v:170$168_Y } + connect \S $procmux$482_CMP + connect \Y $0\hundreds[7:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $pmux $procmux$487 + parameter \S_WIDTH 4 + parameter \WIDTH 4 + connect \A \state + connect \B { 10'0001001000 $auto$wreduce.cc:461:run$529 [1:0] 4'0000 } + connect \S { $procmux$471_CMP $procmux$479_CMP $procmux$470_CMP $procmux$482_CMP } + connect \Y $0\state[3:0] + end + attribute \full_case 1 + attribute \src "rows.v:162.21-162.37|rows.v:162.17-167.20" + cell $mux $procmux$490 + parameter \WIDTH 2 + connect \A 2'01 + connect \B 2'11 + connect \S $eq$rows.v:162$166_Y + connect \Y $auto$wreduce.cc:461:run$529 [1:0] + end + attribute \src "rows.v:156.37-156.71" + cell $mux $ternary$rows.v:156$158 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'11 + connect \S $ge$rows.v:156$157_Y + connect \Y $auto$wreduce.cc:461:run$530 [1:0] + end + attribute \src "rows.v:156.76-156.111" + cell $mux $ternary$rows.v:156$161 + parameter \WIDTH 6 + connect \A 6'000000 + connect \B 6'110000 + connect \S $ge$rows.v:156$160_Y + connect \Y $auto$wreduce.cc:461:run$531 [5:0] + end + attribute \src "rows.v:156.116-156.153" + cell $mux $ternary$rows.v:156$164 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B 10'1100000000 + connect \S $ge$rows.v:156$163_Y + connect \Y $ternary$rows.v:156$164_Y [9:0] + end + connect $auto$wreduce.cc:461:run$529 [3:2] 2'00 + connect $auto$wreduce.cc:461:run$530 [11:2] 10'0000000000 + connect $auto$wreduce.cc:461:run$531 [11:6] 6'000000 + connect $ternary$rows.v:156$164_Y [11:10] 2'00 +end +attribute \src "rows.v:120.1-128.10" +module \toHex + wire width 7 $0\hexChar[7:0] + wire width 7 $add$rows.v:126$152_Y + wire width 7 $add$rows.v:126$153_Y + attribute \src "rows.v:126.21-126.31" + wire $le$rows.v:126$151_Y + attribute \src "rows.v:121.11-121.16" + wire input 1 \clk_i + attribute \init 8'00110000 + attribute \src "rows.v:123.22-123.29" + wire width 8 output 3 \hexChar + attribute \src "rows.v:122.17-122.22" + wire width 4 input 2 \value + attribute \src "rows.v:126.35-126.48" + cell $add $add$rows.v:126$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110000 + connect \B \value + connect \Y $add$rows.v:126$152_Y + end + attribute \src "rows.v:126.51-126.64" + cell $add $add$rows.v:126$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110111 + connect \B \value + connect \Y $add$rows.v:126$153_Y + end + attribute \src "rows.v:126.21-126.31" + cell $le $le$rows.v:126$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \value + connect \B 4'1001 + connect \Y $le$rows.v:126$151_Y + end + attribute \src "rows.v:125.5-127.8" + cell $dff $procdff$495 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 8 + connect \CLK \clk_i + connect \D { 1'0 $0\hexChar[7:0] } + connect \Q \hexChar + end + attribute \src "rows.v:126.20-126.64" + cell $mux $ternary$rows.v:126$154 + parameter \WIDTH 7 + connect \A $add$rows.v:126$153_Y + connect \B $add$rows.v:126$152_Y + connect \S $le$rows.v:126$151_Y + connect \Y $0\hexChar[7:0] + end +end diff --git a/screen_data/hexDecRow/model/design.log b/screen_data/hexDecRow/model/design.log new file mode 100644 index 0000000..6f05e03 --- /dev/null +++ b/screen_data/hexDecRow/model/design.log @@ -0,0 +1,548 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) + + +-- Executing script file `../model/design.ys' -- + +1. Executing Verilog-2005 frontend: rows.v +Parsing formal Verilog input from `rows.v' to AST representation. +Generating RTLIL representation for module `\uartTextRow'. +Generating RTLIL representation for module `\binaryRow'. +Generating RTLIL representation for module `\toHex'. +Generating RTLIL representation for module `\toDec'. +Generating RTLIL representation for module `\hexDecRow'. +Generating RTLIL representation for module `\progressRow'. +Successfully finished Verilog frontend. + +2. Executing PREP pass. + +2.1. Executing HIERARCHY pass (managing design hierarchy). + +2.1.1. Analyzing design hierarchy.. +Top module: \hexDecRow +Used module: \toDec +Used module: \toHex + +2.1.2. Analyzing design hierarchy.. +Top module: \hexDecRow +Used module: \toDec +Used module: \toHex +Removing unused module `\progressRow'. +Removing unused module `\binaryRow'. +Removing unused module `\uartTextRow'. +Removed 3 unused modules. +Module hexDecRow directly or indirectly contains formal properties -> setting "keep" attribute. +Mapping positional arguments of cell hexDecRow.dec (toDec). +Mapping positional arguments of cell hexDecRow.h2 (toHex). +Mapping positional arguments of cell hexDecRow.h1 (toHex). + +2.2. Executing PROC pass (convert processes to netlists). + +2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$rows.v:200$190 in module hexDecRow. +Marked 1 switch rules as full_case in process $proc$rows.v:147$156 in module toDec. +Removed a total of 0 dead cases. + +2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 1 redundant assignment. +Promoted 22 assignments to connections. + +2.2.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\toHex.$proc$rows.v:0$155'. + Set init value: \hexChar = 8'00110000 +Found init rule in `\hexDecRow.$proc$rows.v:0$233'. + Set init value: $formal$rows.v:253$189_EN = 1'0 +Found init rule in `\hexDecRow.$proc$rows.v:0$231'. + Set init value: $formal$rows.v:252$188_EN = 1'0 +Found init rule in `\hexDecRow.$proc$rows.v:0$229'. + Set init value: $formal$rows.v:251$187_EN = 1'0 +Found init rule in `\hexDecRow.$proc$rows.v:0$227'. + Set init value: $formal$rows.v:250$186_EN = 1'0 +Found init rule in `\hexDecRow.$proc$rows.v:0$225'. + Set init value: $formal$rows.v:249$185_EN = 1'0 +Found init rule in `\hexDecRow.$proc$rows.v:0$224'. + Set init value: \f_past_valid = 1'0 +Found init rule in `\toDec.$proc$rows.v:140$177'. + Set init value: \state = 4'0000 +Found init rule in `\toDec.$proc$rows.v:139$176'. + Set init value: \stepCounter = 4'0000 +Found init rule in `\toDec.$proc$rows.v:138$175'. + Set init value: \cachedValue = 8'00000000 +Found init rule in `\toDec.$proc$rows.v:137$174'. + Set init value: \digits = 12'000000000000 +Found init rule in `\toDec.$proc$rows.v:0$173'. + Set init value: \units = 8'00110000 +Found init rule in `\toDec.$proc$rows.v:0$172'. + Set init value: \tens = 8'00110000 +Found init rule in `\toDec.$proc$rows.v:0$171'. + Set init value: \hundreds = 8'00110000 + +2.2.5. Executing PROC_ARST pass (detect async resets in processes). + +2.2.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\toHex.$proc$rows.v:0$155'. +Creating decoders for process `\toHex.$proc$rows.v:125$150'. +Creating decoders for process `\hexDecRow.$proc$rows.v:0$233'. +Creating decoders for process `\hexDecRow.$proc$rows.v:0$231'. +Creating decoders for process `\hexDecRow.$proc$rows.v:0$229'. +Creating decoders for process `\hexDecRow.$proc$rows.v:0$227'. +Creating decoders for process `\hexDecRow.$proc$rows.v:0$225'. +Creating decoders for process `\hexDecRow.$proc$rows.v:0$224'. +Creating decoders for process `\hexDecRow.$proc$rows.v:246$196'. + 1/10: $0$formal$rows.v:249$185_EN[0:0]$204 + 2/10: $0$formal$rows.v:249$185_CHECK[0:0]$203 + 3/10: $0$formal$rows.v:250$186_EN[0:0]$206 + 4/10: $0$formal$rows.v:250$186_CHECK[0:0]$205 + 5/10: $0$formal$rows.v:251$187_EN[0:0]$208 + 6/10: $0$formal$rows.v:251$187_CHECK[0:0]$207 + 7/10: $0$formal$rows.v:252$188_EN[0:0]$210 + 8/10: $0$formal$rows.v:252$188_CHECK[0:0]$209 + 9/10: $0$formal$rows.v:253$189_EN[0:0]$212 + 10/10: $0$formal$rows.v:253$189_CHECK[0:0]$211 +Creating decoders for process `\hexDecRow.$proc$rows.v:239$192'. + 1/2: $0$formal$rows.v:240$184_EN[0:0]$194 + 2/2: $0$formal$rows.v:240$184_CHECK[0:0]$193 +Creating decoders for process `\hexDecRow.$proc$rows.v:235$191'. +Creating decoders for process `\hexDecRow.$proc$rows.v:200$190'. + 1/1: $0\outByteReg[7:0] +Creating decoders for process `\toDec.$proc$rows.v:140$177'. +Creating decoders for process `\toDec.$proc$rows.v:139$176'. +Creating decoders for process `\toDec.$proc$rows.v:138$175'. +Creating decoders for process `\toDec.$proc$rows.v:137$174'. +Creating decoders for process `\toDec.$proc$rows.v:0$173'. +Creating decoders for process `\toDec.$proc$rows.v:0$172'. +Creating decoders for process `\toDec.$proc$rows.v:0$171'. +Creating decoders for process `\toDec.$proc$rows.v:147$156'. + 1/7: $0\stepCounter[3:0] + 2/7: $0\cachedValue[7:0] + 3/7: $0\digits[11:0] + 4/7: $0\units[7:0] + 5/7: $0\tens[7:0] + 6/7: $0\hundreds[7:0] + 7/7: $0\state[3:0] + +2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). +No latch inferred for signal `\hexDecRow.$formal$rows.v:240$184_CHECK' from process `\hexDecRow.$proc$rows.v:239$192'. +No latch inferred for signal `\hexDecRow.$formal$rows.v:240$184_EN' from process `\hexDecRow.$proc$rows.v:239$192'. + +2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\toHex.\hexChar' using process `\toHex.$proc$rows.v:125$150'. + created $dff cell `$procdff$495' with positive edge clock. +Creating register for signal `\hexDecRow.$past$rows.v:248$178$0' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$496' with positive edge clock. +Creating register for signal `\hexDecRow.$past$rows.v:249$179$0' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$497' with positive edge clock. +Creating register for signal `\hexDecRow.$past$rows.v:250$180$0' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$498' with positive edge clock. +Creating register for signal `\hexDecRow.$past$rows.v:251$181$0' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$499' with positive edge clock. +Creating register for signal `\hexDecRow.$past$rows.v:252$182$0' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$500' with positive edge clock. +Creating register for signal `\hexDecRow.$past$rows.v:253$183$0' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$501' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:249$185_CHECK' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$502' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:249$185_EN' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$503' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:250$186_CHECK' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$504' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:250$186_EN' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$505' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:251$187_CHECK' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$506' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:251$187_EN' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$507' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:252$188_CHECK' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$508' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:252$188_EN' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$509' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:253$189_CHECK' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$510' with positive edge clock. +Creating register for signal `\hexDecRow.$formal$rows.v:253$189_EN' using process `\hexDecRow.$proc$rows.v:246$196'. + created $dff cell `$procdff$511' with positive edge clock. +Creating register for signal `\hexDecRow.\f_past_valid' using process `\hexDecRow.$proc$rows.v:235$191'. + created $dff cell `$procdff$512' with positive edge clock. +Creating register for signal `\hexDecRow.\outByteReg' using process `\hexDecRow.$proc$rows.v:200$190'. + created $dff cell `$procdff$513' with positive edge clock. +Creating register for signal `\toDec.\state' using process `\toDec.$proc$rows.v:147$156'. + created $dff cell `$procdff$514' with positive edge clock. +Creating register for signal `\toDec.\hundreds' using process `\toDec.$proc$rows.v:147$156'. + created $dff cell `$procdff$515' with positive edge clock. +Creating register for signal `\toDec.\tens' using process `\toDec.$proc$rows.v:147$156'. + created $dff cell `$procdff$516' with positive edge clock. +Creating register for signal `\toDec.\units' using process `\toDec.$proc$rows.v:147$156'. + created $dff cell `$procdff$517' with positive edge clock. +Creating register for signal `\toDec.\digits' using process `\toDec.$proc$rows.v:147$156'. + created $dff cell `$procdff$518' with positive edge clock. +Creating register for signal `\toDec.\cachedValue' using process `\toDec.$proc$rows.v:147$156'. + created $dff cell `$procdff$519' with positive edge clock. +Creating register for signal `\toDec.\stepCounter' using process `\toDec.$proc$rows.v:147$156'. + created $dff cell `$procdff$520' with positive edge clock. + +2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `toHex.$proc$rows.v:0$155'. +Removing empty process `toHex.$proc$rows.v:125$150'. +Removing empty process `hexDecRow.$proc$rows.v:0$233'. +Removing empty process `hexDecRow.$proc$rows.v:0$231'. +Removing empty process `hexDecRow.$proc$rows.v:0$229'. +Removing empty process `hexDecRow.$proc$rows.v:0$227'. +Removing empty process `hexDecRow.$proc$rows.v:0$225'. +Removing empty process `hexDecRow.$proc$rows.v:0$224'. +Found and cleaned up 2 empty switches in `\hexDecRow.$proc$rows.v:246$196'. +Removing empty process `hexDecRow.$proc$rows.v:246$196'. +Found and cleaned up 1 empty switch in `\hexDecRow.$proc$rows.v:239$192'. +Removing empty process `hexDecRow.$proc$rows.v:239$192'. +Removing empty process `hexDecRow.$proc$rows.v:235$191'. +Found and cleaned up 1 empty switch in `\hexDecRow.$proc$rows.v:200$190'. +Removing empty process `hexDecRow.$proc$rows.v:200$190'. +Removing empty process `toDec.$proc$rows.v:140$177'. +Removing empty process `toDec.$proc$rows.v:139$176'. +Removing empty process `toDec.$proc$rows.v:138$175'. +Removing empty process `toDec.$proc$rows.v:137$174'. +Removing empty process `toDec.$proc$rows.v:0$173'. +Removing empty process `toDec.$proc$rows.v:0$172'. +Removing empty process `toDec.$proc$rows.v:0$171'. +Found and cleaned up 2 empty switches in `\toDec.$proc$rows.v:147$156'. +Removing empty process `toDec.$proc$rows.v:147$156'. +Cleaned up 6 empty switches. + +2.2.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module toHex. +Optimizing module hexDecRow. + +Optimizing module toDec. + + +2.3. Executing FUTURE pass. + +2.4. Executing OPT_EXPR pass (perform const folding). +Optimizing module toHex. +Optimizing module hexDecRow. +Optimizing module toDec. + +2.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \toHex.. +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Removed 0 unused cells and 58 unused wires. + + +2.6. Executing CHECK pass (checking for obvious problems). +Checking module hexDecRow... +Checking module toDec... +Checking module toHex... +Found and reported 0 problems. + +2.7. Executing OPT pass (performing simple optimizations). + +2.7.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module hexDecRow. + +Optimizing module toDec. +Optimizing module toHex. + +2.7.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\hexDecRow'. + +Finding identical cells in module `\toDec'. + +Finding identical cells in module `\toHex'. +Removed a total of 15 cells. + +2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \hexDecRow.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \toDec.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \toHex.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \hexDecRow. + New ctrl vector for $pmux cell $procmux$451: { $procmux$464_CMP $procmux$462_CMP $procmux$460_CMP $procmux$459_CMP $procmux$458_CMP $auto$opt_reduce.cc:134:opt_pmux$524 $procmux$456_CMP $auto$opt_reduce.cc:134:opt_pmux$522 $procmux$454_CMP $procmux$453_CMP $procmux$452_CMP } + Optimizing cells in module \hexDecRow. + Optimizing cells in module \toDec. + Optimizing cells in module \toHex. +Performed a total of 1 changes. + +2.7.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\hexDecRow'. +Finding identical cells in module `\toDec'. +Finding identical cells in module `\toHex'. +Removed a total of 0 cells. + +2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \toHex.. +Removed 0 unused cells and 16 unused wires. + + +2.7.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module hexDecRow. +Optimizing module toDec. +Optimizing module toHex. + +2.7.8. Rerunning OPT passes. (Maybe there is more to do..) + +2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \hexDecRow.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \toDec.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \toHex.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \hexDecRow. + Optimizing cells in module \toDec. + Optimizing cells in module \toHex. +Performed a total of 0 changes. + +2.7.11. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\hexDecRow'. +Finding identical cells in module `\toDec'. +Finding identical cells in module `\toHex'. +Removed a total of 0 cells. + +2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \toHex.. + +2.7.13. Executing OPT_EXPR pass (perform const folding). +Optimizing module hexDecRow. +Optimizing module toDec. +Optimizing module toHex. + +2.7.14. Finished OPT passes. (There is nothing left to do.) + +2.8. Executing WREDUCE pass (reducing word size of cells). +Removed top 3 bits (of 4) from port B of cell hexDecRow.$procmux$463_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell hexDecRow.$procmux$462_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell hexDecRow.$procmux$461_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell hexDecRow.$procmux$460_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell hexDecRow.$procmux$459_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell hexDecRow.$procmux$406_CMP0 ($eq). +Removed top 1 bits (of 4) from port B of cell hexDecRow.$procmux$391_CMP0 ($eq). +Removed top 2 bits (of 4) from mux cell toDec.$procmux$490 ($mux). +Removed top 2 bits (of 4) from port B of cell toDec.$procmux$482_CMP0 ($eq). +Removed top 3 bits (of 4) from port B of cell toDec.$procmux$479_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell toDec.$procmux$470_CMP0 ($eq). +Removed top 29 bits (of 32) from port B of cell toDec.$ge$rows.v:156$157 ($ge). +Removed top 10 bits (of 12) from mux cell toDec.$ternary$rows.v:156$158 ($mux). +Removed top 10 bits (of 12) from port B of cell toDec.$add$rows.v:156$159 ($add). +Removed top 29 bits (of 32) from port B of cell toDec.$ge$rows.v:156$160 ($ge). +Removed top 6 bits (of 12) from mux cell toDec.$ternary$rows.v:156$161 ($mux). +Removed top 6 bits (of 12) from port B of cell toDec.$add$rows.v:156$162 ($add). +Removed top 29 bits (of 32) from port B of cell toDec.$ge$rows.v:156$163 ($ge). +Removed top 2 bits (of 12) from mux cell toDec.$ternary$rows.v:156$164 ($mux). +Removed top 2 bits (of 12) from port B of cell toDec.$add$rows.v:156$165 ($add). +Removed top 1 bits (of 4) from port B of cell toDec.$eq$rows.v:162$166 ($eq). +Removed top 31 bits (of 32) from port B of cell toDec.$add$rows.v:166$167 ($add). +Removed top 28 bits (of 32) from port Y of cell toDec.$add$rows.v:166$167 ($add). +Removed top 2 bits (of 8) from port A of cell toDec.$add$rows.v:170$168 ($add). +Removed top 1 bits (of 8) from port Y of cell toDec.$add$rows.v:170$168 ($add). +Removed top 2 bits (of 8) from port A of cell toDec.$add$rows.v:171$169 ($add). +Removed top 1 bits (of 8) from port Y of cell toDec.$add$rows.v:171$169 ($add). +Removed top 2 bits (of 8) from port A of cell toDec.$add$rows.v:172$170 ($add). +Removed top 1 bits (of 8) from port Y of cell toDec.$add$rows.v:172$170 ($add). +Removed top 28 bits (of 32) from wire toDec.$add$rows.v:166$167_Y. +Removed top 1 bits (of 8) from wire toDec.$add$rows.v:170$168_Y. +Removed top 1 bits (of 8) from wire toDec.$add$rows.v:171$169_Y. +Removed top 1 bits (of 8) from wire toDec.$add$rows.v:172$170_Y. +Removed top 2 bits (of 4) from wire toDec.$procmux$490_Y. +Removed top 10 bits (of 12) from wire toDec.$ternary$rows.v:156$158_Y. +Removed top 9 bits (of 12) from wire toDec.$ternary$rows.v:156$161_Y. +Removed top 28 bits (of 32) from port B of cell toHex.$le$rows.v:126$151 ($le). +Removed top 2 bits (of 8) from port A of cell toHex.$add$rows.v:126$152 ($add). +Removed top 1 bits (of 8) from port Y of cell toHex.$add$rows.v:126$152 ($add). +Removed top 2 bits (of 8) from port A of cell toHex.$add$rows.v:126$153 ($add). +Removed top 1 bits (of 8) from port Y of cell toHex.$add$rows.v:126$153 ($add). +Removed top 1 bits (of 8) from mux cell toHex.$ternary$rows.v:126$154 ($mux). +Removed top 1 bits (of 8) from wire toHex.$0\hexChar[7:0]. +Removed top 1 bits (of 8) from wire toHex.$add$rows.v:126$152_Y. +Removed top 1 bits (of 8) from wire toHex.$add$rows.v:126$153_Y. + +2.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \toHex.. +Removed 0 unused cells and 10 unused wires. + + +2.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.11. Executing OPT pass (performing simple optimizations). + +2.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module hexDecRow. +Optimizing module toDec. +Optimizing module toHex. + +2.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\hexDecRow'. +Finding identical cells in module `\toDec'. +Finding identical cells in module `\toHex'. +Removed a total of 0 cells. + +2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \toHex.. + +2.11.4. Finished fast OPT passes. + +2.12. Printing statistics. + +=== hexDecRow === + + Number of wires: 77 + Number of wire bits: 187 + Number of public wires: 13 + Number of public wire bits: 78 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 75 + $assert 6 + $dff 18 + $eq 22 + $logic_not 1 + $mux 22 + $pmux 1 + $reduce_or 2 + toDec 1 + toHex 2 + +=== toDec === + + Number of wires: 36 + Number of wire bits: 226 + Number of public wires: 9 + Number of public wire bits: 61 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 34 + $add 7 + $dff 7 + $eq 4 + $ge 3 + $logic_not 1 + $mux 8 + $pmux 4 + +=== toHex === + + Number of wires: 7 + Number of wire bits: 35 + Number of public wires: 3 + Number of public wire bits: 13 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $add 2 + $dff 1 + $le 1 + $mux 1 + +=== design hierarchy === + + hexDecRow 1 + toDec 1 + toHex 2 + + Number of wires: 127 + Number of wire bits: 483 + Number of public wires: 28 + Number of public wire bits: 165 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 116 + $add 11 + $assert 6 + $dff 27 + $eq 26 + $ge 3 + $le 2 + $logic_not 2 + $mux 32 + $pmux 5 + $reduce_or 2 + +2.13. Executing CHECK pass (checking for obvious problems). +Checking module hexDecRow... +Checking module toDec... +Checking module toHex... +Found and reported 0 problems. + +3. Executing HIERARCHY pass (managing design hierarchy). + +3.1. Analyzing design hierarchy.. +Top module: \hexDecRow +Used module: \toDec +Used module: \toHex + +3.2. Analyzing design hierarchy.. +Top module: \hexDecRow +Used module: \toDec +Used module: \toHex +Removed 0 unused modules. +Module hexDecRow directly or indirectly contains formal properties -> setting "keep" attribute. + +4. Executing jny backend. + +5. Executing RTLIL backend. +Output filename: ../model/design.il + +End of script. Logfile hash: de9271d43d, CPU: user 0.07s system 0.00s, MEM: 13.31 MB peak +Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) +Time spent: 26% 2x read_verilog (0 sec), 18% 6x opt_expr (0 sec), ... diff --git a/screen_data/hexDecRow/model/design.ys b/screen_data/hexDecRow/model/design.ys new file mode 100644 index 0000000..a5b4b45 --- /dev/null +++ b/screen_data/hexDecRow/model/design.ys @@ -0,0 +1,7 @@ +# running in hexDecRow/src/ +read_verilog -DHEX_DEC_ROW -formal rows.v +prep -top hexDecRow + +hierarchy -smtcheck +write_jny -no-connections ../model/design.json +write_rtlil ../model/design.il diff --git a/screen_data/hexDecRow/model/design_prep.il b/screen_data/hexDecRow/model/design_prep.il new file mode 100644 index 0000000..6a76711 --- /dev/null +++ b/screen_data/hexDecRow/model/design_prep.il @@ -0,0 +1,1281 @@ +# Generated by Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) +autoidx 564 +attribute \src "rows.v:180.1-260.10" +attribute \top 1 +attribute \keep 1 +module \hexDecRow + attribute \src "rows.v:239.9-241.49" + wire $0$formal$rows.v:240$184_CHECK[0:0]$193 + attribute \src "rows.v:239.9-241.49" + wire $0$formal$rows.v:240$184_EN[0:0]$194 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:249$185_CHECK[0:0]$203 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:249$185_EN[0:0]$204 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:250$186_CHECK[0:0]$205 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:250$186_EN[0:0]$206 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:251$187_CHECK[0:0]$207 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:251$187_EN[0:0]$208 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:252$188_CHECK[0:0]$209 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:252$188_EN[0:0]$210 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:253$189_CHECK[0:0]$211 + attribute \src "rows.v:246.9-256.12" + wire $0$formal$rows.v:253$189_EN[0:0]$212 + attribute \src "rows.v:200.5-217.8" + wire width 8 $0\outByteReg[7:0] + wire $auto$opt_reduce.cc:134:opt_pmux$522 + wire $auto$opt_reduce.cc:134:opt_pmux$524 + attribute \src "rows.v:249.31-249.65" + wire $eq$rows.v:249$213_Y + attribute \src "rows.v:250.31-250.64" + wire $eq$rows.v:250$214_Y + attribute \src "rows.v:251.32-251.61" + wire $eq$rows.v:251$215_Y + attribute \src "rows.v:252.32-252.61" + wire $eq$rows.v:252$216_Y + attribute \src "rows.v:253.32-253.61" + wire $eq$rows.v:253$217_Y + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:249$185_EN + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:250$186_EN + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:251$187_EN + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:252$188_EN + attribute \init 1'0 + attribute \src "rows.v:0.0-0.0" + wire $formal$rows.v:253$189_EN + wire $procmux$390_Y + wire $procmux$391_CMP + wire $procmux$398_Y + wire $procmux$405_Y + wire $procmux$406_CMP + wire $procmux$412_Y + wire $procmux$418_Y + wire $procmux$419_CMP + wire $procmux$424_Y + wire $procmux$429_Y + wire $procmux$430_CMP + wire $procmux$434_Y + wire $procmux$438_Y + wire $procmux$439_CMP + wire $procmux$442_Y + wire $procmux$452_CMP + wire $procmux$453_CMP + wire $procmux$454_CMP + wire $procmux$455_CMP + wire $procmux$456_CMP + wire $procmux$457_CMP + wire $procmux$458_CMP + wire $procmux$459_CMP + wire $procmux$460_CMP + wire $procmux$461_CMP + wire $procmux$462_CMP + wire $procmux$463_CMP + wire $procmux$464_CMP + attribute \hdlname "_witness_ anyinit_procdff_496" + wire width 4 \_witness_.anyinit_procdff_496 + attribute \hdlname "_witness_ anyinit_procdff_497" + wire width 8 \_witness_.anyinit_procdff_497 + attribute \hdlname "_witness_ anyinit_procdff_498" + wire width 8 \_witness_.anyinit_procdff_498 + attribute \hdlname "_witness_ anyinit_procdff_499" + wire width 8 \_witness_.anyinit_procdff_499 + attribute \hdlname "_witness_ anyinit_procdff_500" + wire width 8 \_witness_.anyinit_procdff_500 + attribute \hdlname "_witness_ anyinit_procdff_501" + wire width 8 \_witness_.anyinit_procdff_501 + attribute \hdlname "_witness_ anyinit_procdff_502" + wire \_witness_.anyinit_procdff_502 + attribute \hdlname "_witness_ anyinit_procdff_504" + wire \_witness_.anyinit_procdff_504 + attribute \hdlname "_witness_ anyinit_procdff_506" + wire \_witness_.anyinit_procdff_506 + attribute \hdlname "_witness_ anyinit_procdff_508" + wire \_witness_.anyinit_procdff_508 + attribute \hdlname "_witness_ anyinit_procdff_510" + wire \_witness_.anyinit_procdff_510 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_541" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_541 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_543" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_543 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_545" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_545 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_547" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_547 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_549" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_549 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_551" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_551 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_553" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_553 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_555" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_555 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_557" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_557 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_559" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_559 + attribute \hdlname "_witness_ anyseq_auto_setundef_cc_533_execute_561" + wire \_witness_.anyseq_auto_setundef_cc_533_execute_561 + attribute \keep 1 + attribute \replaced_by_gclk 1'1 + attribute \src "rows.v:181.11-181.16" + wire input 1 \clk_i + attribute \src "rows.v:197.16-197.24" + wire width 8 \decChar1 + attribute \src "rows.v:197.26-197.34" + wire width 8 \decChar2 + attribute \src "rows.v:197.36-197.44" + wire width 8 \decChar3 + attribute \init 1'0 + attribute \src "rows.v:233.13-233.25" + wire \f_past_valid + attribute \src "rows.v:188.26-188.35" + wire width 4 \hexHigher + attribute \src "rows.v:188.16-188.24" + wire width 4 \hexLower + attribute \src "rows.v:189.30-189.43" + wire width 8 \higherHexChar + attribute \src "rows.v:189.16-189.28" + wire width 8 \lowerHexChar + attribute \src "rows.v:186.15-186.25" + wire width 8 \outByteReg + attribute \src "rows.v:184.18-184.27" + wire width 8 output 4 \outByte_i + attribute \src "rows.v:183.17-183.34" + wire width 4 input 3 \outputCharIndex_i + attribute \src "rows.v:182.17-182.24" + wire width 8 input 2 \value_i + attribute \src "rows.v:240.29-241.48" + cell $assert $assert$rows.v:240$218 + connect \A $0$formal$rows.v:240$184_CHECK[0:0]$193 + connect \EN $0$formal$rows.v:240$184_EN[0:0]$194 + end + attribute \src "rows.v:249.23-249.66" + cell $assert $assert$rows.v:249$219 + connect \A \_witness_.anyinit_procdff_502 + connect \EN $formal$rows.v:249$185_EN + end + attribute \src "rows.v:250.23-250.65" + cell $assert $assert$rows.v:250$220 + connect \A \_witness_.anyinit_procdff_504 + connect \EN $formal$rows.v:250$186_EN + end + attribute \src "rows.v:251.24-251.62" + cell $assert $assert$rows.v:251$221 + connect \A \_witness_.anyinit_procdff_506 + connect \EN $formal$rows.v:251$187_EN + end + attribute \src "rows.v:252.24-252.62" + cell $assert $assert$rows.v:252$222 + connect \A \_witness_.anyinit_procdff_508 + connect \EN $formal$rows.v:252$188_EN + end + attribute \src "rows.v:253.24-253.62" + cell $assert $assert$rows.v:253$223 + connect \A \_witness_.anyinit_procdff_510 + connect \EN $formal$rows.v:253$189_EN + end + cell $reduce_or $auto$opt_reduce.cc:128:opt_pmux$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { $procmux$455_CMP $procmux$461_CMP } + connect \Y $auto$opt_reduce.cc:134:opt_pmux$522 + end + cell $reduce_or $auto$opt_reduce.cc:128:opt_pmux$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { $procmux$457_CMP $procmux$463_CMP } + connect \Y $auto$opt_reduce.cc:134:opt_pmux$524 + end + cell $anyseq $auto$setundef.cc:533:execute$541 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_541 + end + cell $anyseq $auto$setundef.cc:533:execute$543 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_543 + end + cell $anyseq $auto$setundef.cc:533:execute$545 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_545 + end + cell $anyseq $auto$setundef.cc:533:execute$547 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_547 + end + cell $anyseq $auto$setundef.cc:533:execute$549 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_549 + end + cell $anyseq $auto$setundef.cc:533:execute$551 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_551 + end + cell $anyseq $auto$setundef.cc:533:execute$553 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_553 + end + cell $anyseq $auto$setundef.cc:533:execute$555 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_555 + end + cell $anyseq $auto$setundef.cc:533:execute$557 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_557 + end + cell $anyseq $auto$setundef.cc:533:execute$559 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_559 + end + cell $anyseq $auto$setundef.cc:533:execute$561 + parameter \WIDTH 1 + connect \Y \_witness_.anyseq_auto_setundef_cc_533_execute_561 + end + attribute \src "rows.v:249.31-249.65" + cell $eq $eq$rows.v:249$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B \_witness_.anyinit_procdff_497 + connect \Y $eq$rows.v:249$213_Y + end + attribute \src "rows.v:250.31-250.64" + cell $eq $eq$rows.v:250$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B \_witness_.anyinit_procdff_498 + connect \Y $eq$rows.v:250$214_Y + end + attribute \src "rows.v:251.32-251.61" + cell $eq $eq$rows.v:251$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B \_witness_.anyinit_procdff_499 + connect \Y $eq$rows.v:251$215_Y + end + attribute \src "rows.v:252.32-252.61" + cell $eq $eq$rows.v:252$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B \_witness_.anyinit_procdff_500 + connect \Y $eq$rows.v:252$216_Y + end + attribute \src "rows.v:253.32-253.61" + cell $eq $eq$rows.v:253$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \outByteReg + connect \B \_witness_.anyinit_procdff_501 + connect \Y $eq$rows.v:253$217_Y + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$496 + parameter \WIDTH 4 + connect \D \outputCharIndex_i + connect \Q \_witness_.anyinit_procdff_496 + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$497 + parameter \WIDTH 8 + connect \D \higherHexChar + connect \Q \_witness_.anyinit_procdff_497 + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$498 + parameter \WIDTH 8 + connect \D \lowerHexChar + connect \Q \_witness_.anyinit_procdff_498 + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$499 + parameter \WIDTH 8 + connect \D \decChar1 + connect \Q \_witness_.anyinit_procdff_499 + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$500 + parameter \WIDTH 8 + connect \D \decChar2 + connect \Q \_witness_.anyinit_procdff_500 + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$501 + parameter \WIDTH 8 + connect \D \decChar3 + connect \Q \_witness_.anyinit_procdff_501 + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$502 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:249$185_CHECK[0:0]$203 + connect \Q \_witness_.anyinit_procdff_502 + end + attribute \src "rows.v:246.9-256.12" + cell $ff $procdff$503 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:249$185_EN[0:0]$204 + connect \Q $formal$rows.v:249$185_EN + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$504 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:250$186_CHECK[0:0]$205 + connect \Q \_witness_.anyinit_procdff_504 + end + attribute \src "rows.v:246.9-256.12" + cell $ff $procdff$505 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:250$186_EN[0:0]$206 + connect \Q $formal$rows.v:250$186_EN + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$506 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:251$187_CHECK[0:0]$207 + connect \Q \_witness_.anyinit_procdff_506 + end + attribute \src "rows.v:246.9-256.12" + cell $ff $procdff$507 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:251$187_EN[0:0]$208 + connect \Q $formal$rows.v:251$187_EN + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$508 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:252$188_CHECK[0:0]$209 + connect \Q \_witness_.anyinit_procdff_508 + end + attribute \src "rows.v:246.9-256.12" + cell $ff $procdff$509 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:252$188_EN[0:0]$210 + connect \Q $formal$rows.v:252$188_EN + end + attribute \src "rows.v:246.9-256.12" + cell $anyinit $procdff$510 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:253$189_CHECK[0:0]$211 + connect \Q \_witness_.anyinit_procdff_510 + end + attribute \src "rows.v:246.9-256.12" + cell $ff $procdff$511 + parameter \WIDTH 1 + connect \D $0$formal$rows.v:253$189_EN[0:0]$212 + connect \Q $formal$rows.v:253$189_EN + end + attribute \src "rows.v:235.9-236.34" + cell $ff $procdff$512 + parameter \WIDTH 1 + connect \D 1'1 + connect \Q \f_past_valid + end + attribute \src "rows.v:200.5-217.8" + cell $anyinit $procdff$513 + parameter \WIDTH 8 + connect \D $0\outByteReg[7:0] + connect \Q \outByteReg + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$390 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$391_CMP + connect \Y $procmux$390_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$391_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_witness_.anyinit_procdff_496 + connect \B 3'101 + connect \Y $procmux$391_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$392 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$390_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:249$185_EN[0:0]$204 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$398 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_541 + connect \B $eq$rows.v:249$213_Y + connect \S $procmux$391_CMP + connect \Y $procmux$398_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$400 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_543 + connect \B $procmux$398_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:249$185_CHECK[0:0]$203 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$405 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$406_CMP + connect \Y $procmux$405_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$406_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_witness_.anyinit_procdff_496 + connect \B 3'110 + connect \Y $procmux$406_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$407 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$405_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:250$186_EN[0:0]$206 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$412 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_545 + connect \B $eq$rows.v:250$214_Y + connect \S $procmux$406_CMP + connect \Y $procmux$412_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$414 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_547 + connect \B $procmux$412_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:250$186_CHECK[0:0]$205 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$418 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$419_CMP + connect \Y $procmux$418_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$419_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_witness_.anyinit_procdff_496 + connect \B 4'1101 + connect \Y $procmux$419_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$420 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$418_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:251$187_EN[0:0]$208 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$424 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_549 + connect \B $eq$rows.v:251$215_Y + connect \S $procmux$419_CMP + connect \Y $procmux$424_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$426 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_551 + connect \B $procmux$424_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:251$187_CHECK[0:0]$207 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$429 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$430_CMP + connect \Y $procmux$429_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$430_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_witness_.anyinit_procdff_496 + connect \B 4'1110 + connect \Y $procmux$430_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$431 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$429_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:252$188_EN[0:0]$210 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$434 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_553 + connect \B $eq$rows.v:252$216_Y + connect \S $procmux$430_CMP + connect \Y $procmux$434_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$436 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_555 + connect \B $procmux$434_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:252$188_CHECK[0:0]$209 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$438 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S $procmux$439_CMP + connect \Y $procmux$438_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $eq $procmux$439_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_witness_.anyinit_procdff_496 + connect \B 4'1111 + connect \Y $procmux$439_CMP + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$440 + parameter \WIDTH 1 + connect \A 1'0 + connect \B $procmux$438_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:253$189_EN[0:0]$212 + end + attribute \src "rows.v:0.0-0.0|rows.v:248.17-254.24" + cell $mux $procmux$442 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_557 + connect \B $eq$rows.v:253$217_Y + connect \S $procmux$439_CMP + connect \Y $procmux$442_Y + end + attribute \src "rows.v:247.16-247.28|rows.v:247.13-255.16" + cell $mux $procmux$444 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_559 + connect \B $procmux$442_Y + connect \S \f_past_valid + connect \Y $0$formal$rows.v:253$189_CHECK[0:0]$211 + end + attribute \src "rows.v:240.16-240.28|rows.v:240.13-241.49" + cell $mux $procmux$446 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \f_past_valid + connect \Y $0$formal$rows.v:240$184_EN[0:0]$194 + end + attribute \src "rows.v:240.16-240.28|rows.v:240.13-241.49" + cell $mux $procmux$448 + parameter \WIDTH 1 + connect \A \_witness_.anyseq_auto_setundef_cc_533_execute_561 + connect \B 1'1 + connect \S \f_past_valid + connect \Y $0$formal$rows.v:240$184_CHECK[0:0]$193 + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $pmux $procmux$451 + parameter \S_WIDTH 11 + parameter \WIDTH 8 + connect \A 8'00100000 + connect \B { 16'0100100001111000 \higherHexChar \lowerHexChar 32'01000100011001010110001100111010 \decChar1 \decChar2 \decChar3 } + connect \S { $procmux$464_CMP $procmux$462_CMP $procmux$460_CMP $procmux$459_CMP $procmux$458_CMP $auto$opt_reduce.cc:134:opt_pmux$524 $procmux$456_CMP $auto$opt_reduce.cc:134:opt_pmux$522 $procmux$454_CMP $procmux$453_CMP $procmux$452_CMP } + connect \Y $0\outByteReg[7:0] + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$452_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1111 + connect \Y $procmux$452_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$453_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1110 + connect \Y $procmux$453_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$454_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1101 + connect \Y $procmux$454_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$455_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1011 + connect \Y $procmux$455_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$456_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1010 + connect \Y $procmux$456_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$457_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1001 + connect \Y $procmux$457_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$458_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 4'1000 + connect \Y $procmux$458_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$459_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 3'110 + connect \Y $procmux$459_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$460_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 3'101 + connect \Y $procmux$460_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$461_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 2'11 + connect \Y $procmux$461_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$462_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 2'10 + connect \Y $procmux$462_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $eq $procmux$463_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \B 1'1 + connect \Y $procmux$463_CMP + end + attribute \full_case 1 + attribute \src "rows.v:0.0-0.0|rows.v:201.9-216.16" + cell $logic_not $procmux$464_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \outputCharIndex_i + connect \Y $procmux$464_CMP + end + attribute \module_not_derived 1 + attribute \src "rows.v:198.11-198.60" + cell \toDec \dec + connect \clk_i \clk_i + connect \hundreds \decChar1 + connect \tens \decChar2 + connect \units \decChar3 + connect \value \value_i + end + attribute \module_not_derived 1 + attribute \src "rows.v:194.11-194.44" + cell \toHex \h1 + connect \clk_i \clk_i + connect \hexChar \lowerHexChar + connect \value \value_i [3:0] + end + attribute \module_not_derived 1 + attribute \src "rows.v:195.11-195.46" + cell \toHex \h2 + connect \clk_i \clk_i + connect \hexChar \higherHexChar + connect \value \value_i [7:4] + end + connect \hexHigher \value_i [7:4] + connect \hexLower \value_i [3:0] + connect \outByte_i \outByteReg +end +attribute \src "rows.v:130.1-177.10" +module \toDec + attribute \src "rows.v:147.5-176.8" + wire width 8 $0\cachedValue[7:0] + attribute \src "rows.v:147.5-176.8" + wire width 12 $0\digits[11:0] + attribute \src "rows.v:147.5-176.8" + wire width 8 $0\hundreds[7:0] + attribute \src "rows.v:147.5-176.8" + wire width 4 $0\state[3:0] + attribute \src "rows.v:147.5-176.8" + wire width 4 $0\stepCounter[3:0] + attribute \src "rows.v:147.5-176.8" + wire width 8 $0\tens[7:0] + attribute \src "rows.v:147.5-176.8" + wire width 8 $0\units[7:0] + attribute \src "rows.v:156.27-156.72" + wire width 12 $add$rows.v:156$159_Y + attribute \src "rows.v:156.27-156.112" + wire width 12 $add$rows.v:156$162_Y + attribute \src "rows.v:156.27-156.154" + wire width 12 $add$rows.v:156$165_Y + wire width 4 $add$rows.v:166$167_Y + wire width 7 $add$rows.v:170$168_Y + wire width 7 $add$rows.v:171$169_Y + wire width 7 $add$rows.v:172$170_Y + wire width 4 $auto$wreduce.cc:461:run$529 + attribute \src "rows.v:156.37-156.71" + wire width 12 $auto$wreduce.cc:461:run$530 + attribute \src "rows.v:156.76-156.111" + wire width 12 $auto$wreduce.cc:461:run$531 + attribute \src "rows.v:162.21-162.37" + wire $eq$rows.v:162$166_Y + attribute \src "rows.v:156.38-156.54" + wire $ge$rows.v:156$157_Y + attribute \src "rows.v:156.77-156.93" + wire $ge$rows.v:156$160_Y + attribute \src "rows.v:156.117-156.134" + wire $ge$rows.v:156$163_Y + wire width 4 $procmux$467_Y + wire $procmux$470_CMP + wire $procmux$471_CMP + wire $procmux$479_CMP + wire $procmux$482_CMP + attribute \src "rows.v:156.116-156.153" + wire width 12 $ternary$rows.v:156$164_Y + attribute \init 8'00000000 + attribute \src "rows.v:138.15-138.26" + wire width 8 \cachedValue + attribute \keep 1 + attribute \replaced_by_gclk 1'1 + attribute \src "rows.v:131.11-131.16" + wire input 1 \clk_i + attribute \init 12'000000000000 + attribute \src "rows.v:137.16-137.22" + wire width 12 \digits + attribute \init 8'00110000 + attribute \src "rows.v:133.22-133.30" + wire width 8 output 3 \hundreds + attribute \init 4'0000 + attribute \src "rows.v:140.15-140.20" + wire width 4 \state + attribute \init 4'0000 + attribute \src "rows.v:139.15-139.26" + wire width 4 \stepCounter + attribute \init 8'00110000 + attribute \src "rows.v:134.22-134.26" + wire width 8 output 4 \tens + attribute \init 8'00110000 + attribute \src "rows.v:135.22-135.27" + wire width 8 output 5 \units + attribute \src "rows.v:132.17-132.22" + wire width 8 input 2 \value + attribute \src "rows.v:156.27-156.72" + cell $add $add$rows.v:156$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 12 + connect \A \digits + connect \B $auto$wreduce.cc:461:run$530 [1:0] + connect \Y $add$rows.v:156$159_Y + end + attribute \src "rows.v:156.27-156.112" + cell $add $add$rows.v:156$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 12 + connect \A $add$rows.v:156$159_Y + connect \B $auto$wreduce.cc:461:run$531 [5:0] + connect \Y $add$rows.v:156$162_Y + end + attribute \src "rows.v:156.27-156.154" + cell $add $add$rows.v:156$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 12 + connect \A $add$rows.v:156$162_Y + connect \B $ternary$rows.v:156$164_Y [9:0] + connect \Y $add$rows.v:156$165_Y + end + attribute \src "rows.v:166.36-166.51" + cell $add $add$rows.v:166$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \stepCounter + connect \B 1'1 + connect \Y $add$rows.v:166$167_Y + end + attribute \src "rows.v:170.29-170.49" + cell $add $add$rows.v:170$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110000 + connect \B \digits [11:8] + connect \Y $add$rows.v:170$168_Y + end + attribute \src "rows.v:171.25-171.44" + cell $add $add$rows.v:171$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110000 + connect \B \digits [7:4] + connect \Y $add$rows.v:171$169_Y + end + attribute \src "rows.v:172.26-172.45" + cell $add $add$rows.v:172$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110000 + connect \B \digits [3:0] + connect \Y $add$rows.v:172$170_Y + end + attribute \src "rows.v:162.21-162.37" + cell $eq $eq$rows.v:162$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \stepCounter + connect \B 3'111 + connect \Y $eq$rows.v:162$166_Y + end + attribute \src "rows.v:156.38-156.54" + cell $ge $ge$rows.v:156$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \digits [3:0] + connect \B 3'101 + connect \Y $ge$rows.v:156$157_Y + end + attribute \src "rows.v:156.77-156.93" + cell $ge $ge$rows.v:156$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \digits [7:4] + connect \B 3'101 + connect \Y $ge$rows.v:156$160_Y + end + attribute \src "rows.v:156.117-156.134" + cell $ge $ge$rows.v:156$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \digits [11:8] + connect \B 3'101 + connect \Y $ge$rows.v:156$163_Y + end + attribute \src "rows.v:147.5-176.8" + cell $ff $procdff$514 + parameter \WIDTH 4 + connect \D $0\state[3:0] + connect \Q \state + end + attribute \src "rows.v:147.5-176.8" + cell $ff $procdff$515 + parameter \WIDTH 8 + connect \D $0\hundreds[7:0] + connect \Q \hundreds + end + attribute \src "rows.v:147.5-176.8" + cell $ff $procdff$516 + parameter \WIDTH 8 + connect \D $0\tens[7:0] + connect \Q \tens + end + attribute \src "rows.v:147.5-176.8" + cell $ff $procdff$517 + parameter \WIDTH 8 + connect \D $0\units[7:0] + connect \Q \units + end + attribute \src "rows.v:147.5-176.8" + cell $ff $procdff$518 + parameter \WIDTH 12 + connect \D $0\digits[11:0] + connect \Q \digits + end + attribute \src "rows.v:147.5-176.8" + cell $ff $procdff$519 + parameter \WIDTH 8 + connect \D $0\cachedValue[7:0] + connect \Q \cachedValue + end + attribute \src "rows.v:147.5-176.8" + cell $ff $procdff$520 + parameter \WIDTH 4 + connect \D $0\stepCounter[3:0] + connect \Q \stepCounter + end + attribute \full_case 1 + attribute \src "rows.v:162.21-162.37|rows.v:162.17-167.20" + cell $mux $procmux$467 + parameter \WIDTH 4 + connect \A $add$rows.v:166$167_Y + connect \B \stepCounter + connect \S $eq$rows.v:162$166_Y + connect \Y $procmux$467_Y + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $pmux $procmux$469 + parameter \S_WIDTH 2 + parameter \WIDTH 4 + connect \A \stepCounter + connect \B { 4'0000 $procmux$467_Y } + connect \S { $procmux$471_CMP $procmux$470_CMP } + connect \Y $0\stepCounter[3:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $eq $procmux$470_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \state + connect \B 2'10 + connect \Y $procmux$470_CMP + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $logic_not $procmux$471_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \state + connect \Y $procmux$471_CMP + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $pmux $procmux$473 + parameter \S_WIDTH 2 + parameter \WIDTH 8 + connect \A \cachedValue + connect \B { \value \cachedValue [6:0] 1'0 } + connect \S { $procmux$471_CMP $procmux$470_CMP } + connect \Y $0\cachedValue[7:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $pmux $procmux$477 + parameter \S_WIDTH 3 + parameter \WIDTH 12 + connect \A \digits + connect \B { 12'000000000000 $add$rows.v:156$165_Y \digits [10:0] \cachedValue [7] } + connect \S { $procmux$471_CMP $procmux$479_CMP $procmux$470_CMP } + connect \Y $0\digits[11:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $eq $procmux$479_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \state + connect \B 1'1 + connect \Y $procmux$479_CMP + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $mux $procmux$481 + parameter \WIDTH 8 + connect \A \units + connect \B { 1'0 $add$rows.v:172$170_Y } + connect \S $procmux$482_CMP + connect \Y $0\units[7:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $eq $procmux$482_CMP0 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \state + connect \B 2'11 + connect \Y $procmux$482_CMP + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $mux $procmux$483 + parameter \WIDTH 8 + connect \A \tens + connect \B { 1'0 $add$rows.v:171$169_Y } + connect \S $procmux$482_CMP + connect \Y $0\tens[7:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $mux $procmux$485 + parameter \WIDTH 8 + connect \A \hundreds + connect \B { 1'0 $add$rows.v:170$168_Y } + connect \S $procmux$482_CMP + connect \Y $0\hundreds[7:0] + end + attribute \src "rows.v:0.0-0.0|rows.v:148.9-175.16" + cell $pmux $procmux$487 + parameter \S_WIDTH 4 + parameter \WIDTH 4 + connect \A \state + connect \B { 10'0001001000 $auto$wreduce.cc:461:run$529 [1:0] 4'0000 } + connect \S { $procmux$471_CMP $procmux$479_CMP $procmux$470_CMP $procmux$482_CMP } + connect \Y $0\state[3:0] + end + attribute \full_case 1 + attribute \src "rows.v:162.21-162.37|rows.v:162.17-167.20" + cell $mux $procmux$490 + parameter \WIDTH 2 + connect \A 2'01 + connect \B 2'11 + connect \S $eq$rows.v:162$166_Y + connect \Y $auto$wreduce.cc:461:run$529 [1:0] + end + attribute \src "rows.v:156.37-156.71" + cell $mux $ternary$rows.v:156$158 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'11 + connect \S $ge$rows.v:156$157_Y + connect \Y $auto$wreduce.cc:461:run$530 [1:0] + end + attribute \src "rows.v:156.76-156.111" + cell $mux $ternary$rows.v:156$161 + parameter \WIDTH 6 + connect \A 6'000000 + connect \B 6'110000 + connect \S $ge$rows.v:156$160_Y + connect \Y $auto$wreduce.cc:461:run$531 [5:0] + end + attribute \src "rows.v:156.116-156.153" + cell $mux $ternary$rows.v:156$164 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B 10'1100000000 + connect \S $ge$rows.v:156$163_Y + connect \Y $ternary$rows.v:156$164_Y [9:0] + end + connect $auto$wreduce.cc:461:run$529 [3:2] 2'00 + connect $auto$wreduce.cc:461:run$530 [11:2] 10'0000000000 + connect $auto$wreduce.cc:461:run$531 [11:6] 6'000000 + connect $ternary$rows.v:156$164_Y [11:10] 2'00 +end +attribute \src "rows.v:120.1-128.10" +module \toHex + wire width 7 $0\hexChar[7:0] + wire width 7 $add$rows.v:126$152_Y + wire width 7 $add$rows.v:126$153_Y + attribute \src "rows.v:126.21-126.31" + wire $le$rows.v:126$151_Y + attribute \keep 1 + attribute \replaced_by_gclk 1'1 + attribute \src "rows.v:121.11-121.16" + wire input 1 \clk_i + attribute \init 8'x0110000 + attribute \src "rows.v:123.22-123.29" + wire width 8 output 3 \hexChar + attribute \src "rows.v:122.17-122.22" + wire width 4 input 2 \value + attribute \src "rows.v:126.35-126.48" + cell $add $add$rows.v:126$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110000 + connect \B \value + connect \Y $add$rows.v:126$152_Y + end + attribute \src "rows.v:126.51-126.64" + cell $add $add$rows.v:126$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A 6'110111 + connect \B \value + connect \Y $add$rows.v:126$153_Y + end + attribute \src "rows.v:125.5-127.8" + cell $ff $auto$ff.cc:266:slice$563 + parameter \WIDTH 7 + connect \D $0\hexChar[7:0] + connect \Q \hexChar [6:0] + end + attribute \src "rows.v:126.21-126.31" + cell $le $le$rows.v:126$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \value + connect \B 4'1001 + connect \Y $le$rows.v:126$151_Y + end + attribute \src "rows.v:126.20-126.64" + cell $mux $ternary$rows.v:126$154 + parameter \WIDTH 7 + connect \A $add$rows.v:126$153_Y + connect \B $add$rows.v:126$152_Y + connect \S $le$rows.v:126$151_Y + connect \Y $0\hexChar[7:0] + end + connect \hexChar [7] 1'0 +end diff --git a/screen_data/hexDecRow/model/design_prep.log b/screen_data/hexDecRow/model/design_prep.log new file mode 100644 index 0000000..d3a8531 --- /dev/null +++ b/screen_data/hexDecRow/model/design_prep.log @@ -0,0 +1,119 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) + + +-- Executing script file `design_prep.ys' -- + +1. Executing RTLIL frontend. +Input filename: design.il + +2. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module toHex. +Found 0 SCCs in module toDec. +Found 0 SCCs in module hexDecRow. +Found 0 SCCs. + +3. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4. Executing MEMORY_NORDFF pass (extracting $dff cells from memories). + +5. Executing ASYNC2SYNC pass. + +6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \toHex.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \hexDecRow.. + +7. Executing FORMALFF pass. + +8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \toHex.. +Removed 3 unused cells and 3 unused wires. + + +9. Executing CHECK pass (checking for obvious problems). +Checking module hexDecRow... +Checking module toDec... +Checking module toHex... +Found and reported 0 problems. + +10. Executing SETUNDEF pass (replace undef values with defined constants). + +11. Executing OPT pass (performing simple optimizations). + +11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module hexDecRow. +Optimizing module toDec. +Optimizing module toHex. + +11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\hexDecRow'. +Finding identical cells in module `\toDec'. +Finding identical cells in module `\toHex'. +Removed a total of 0 cells. + +11.3. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 7 on $procdff$495 ($ff) from module toHex. + +11.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \toHex.. + +11.5. Rerunning OPT passes. (Removed registers in this run.) + +11.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module hexDecRow. +Optimizing module toDec. +Optimizing module toHex. + +11.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\hexDecRow'. +Finding identical cells in module `\toDec'. +Finding identical cells in module `\toHex'. +Removed a total of 0 cells. + +11.8. Executing OPT_DFF pass (perform DFF optimizations). + +11.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \toHex.. + +11.10. Finished fast OPT passes. + +12. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \hexDecRow.. +Finding unused cells or wires in module \toDec.. +Finding unused cells or wires in module \toHex.. +Removed 0 unused cells and 22 unused wires. + + +13. Executing RTLIL backend. +Output filename: ../model/design_prep.il + +End of script. Logfile hash: 2b60b9cf4e, CPU: user 0.04s system 0.00s, MEM: 11.05 MB peak +Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) +Time spent: 28% 5x opt_clean (0 sec), 16% 2x opt_expr (0 sec), ... diff --git a/screen_data/hexDecRow/model/design_prep.ys b/screen_data/hexDecRow/model/design_prep.ys new file mode 100644 index 0000000..5d3b6f5 --- /dev/null +++ b/screen_data/hexDecRow/model/design_prep.ys @@ -0,0 +1,16 @@ +# running in hexDecRow/model/ +read_ilang design.il +scc -select; simplemap; select -clear +memory_nordff +async2sync +chformal -assume -early +opt_clean +formalff -setundef -clk2ff -ff2anyinit -hierarchy +chformal -live -fair -cover -remove +opt_clean +check +setundef -undriven -anyseq +opt -fast +rename -witness +opt_clean +write_rtlil ../model/design_prep.il diff --git a/screen_data/hexDecRow/model/design_smt2.log b/screen_data/hexDecRow/model/design_smt2.log new file mode 100644 index 0000000..a16181d --- /dev/null +++ b/screen_data/hexDecRow/model/design_smt2.log @@ -0,0 +1,151 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) + + +-- Executing script file `design_smt2.ys' -- + +1. Executing RTLIL frontend. +Input filename: design_prep.il + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. +Top module: \hexDecRow +Used module: \toHex +Used module: \toDec + +2.2. Analyzing design hierarchy.. +Top module: \hexDecRow +Used module: \toHex +Used module: \toDec +Removed 0 unused modules. +Module hexDecRow directly or indirectly contains formal properties -> setting "keep" attribute. + +3. Executing FORMALFF pass. + +4. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). + +5. Printing statistics. + +=== toHex === + + Number of wires: 8 + Number of wire bits: 36 + Number of public wires: 3 + Number of public wire bits: 13 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 7 + $add 2 + $assume 1 + $ff 1 + $le 1 + $mux 1 + $not 1 + +=== toDec === + + Number of wires: 37 + Number of wire bits: 227 + Number of public wires: 9 + Number of public wire bits: 61 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 36 + $add 7 + $assume 1 + $eq 4 + $ff 7 + $ge 3 + $logic_not 1 + $mux 8 + $not 1 + $pmux 4 + +=== hexDecRow === + + Number of wires: 89 + Number of wire bits: 199 + Number of public wires: 35 + Number of public wire bits: 138 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 88 + $anyinit 12 + $anyseq 11 + $assert 6 + $assume 1 + $eq 22 + $ff 6 + $logic_not 1 + $mux 22 + $not 1 + $pmux 1 + $reduce_or 2 + toDec 1 + toHex 2 + +=== design hierarchy === + + hexDecRow 1 + toDec 1 + toHex 2 + + Number of wires: 142 + Number of wire bits: 498 + Number of public wires: 50 + Number of public wire bits: 225 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 135 + $add 11 + $anyinit 12 + $anyseq 11 + $assert 6 + $assume 4 + $eq 26 + $ff 15 + $ge 3 + $le 2 + $logic_not 2 + $mux 32 + $not 4 + $pmux 5 + $reduce_or 2 + +6. Executing SMT2 backend. + +6.1. Executing BMUXMAP pass. + +6.2. Executing DEMUXMAP pass. +Creating SMT-LIBv2 representation of module toDec. +Creating SMT-LIBv2 representation of module toHex. +Creating SMT-LIBv2 representation of module hexDecRow. + +End of script. Logfile hash: 8321b91b55, CPU: user 0.02s system 0.00s, MEM: 11.17 MB peak +Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) +Time spent: 52% 2x write_smt2 (0 sec), 32% 2x read_ilang (0 sec), ... diff --git a/screen_data/hexDecRow/model/design_smt2.smt2 b/screen_data/hexDecRow/model/design_smt2.smt2 new file mode 100644 index 0000000..2151878 --- /dev/null +++ b/screen_data/hexDecRow/model/design_smt2.smt2 @@ -0,0 +1,484 @@ +; SMT-LIBv2 description generated by Yosys 0.35+36 (git sha1 c95298225, clang 10.0.0-4ubuntu1 -fPIC -Os) +; yosys-smt2-module toDec +(declare-sort |toDec_s| 0) +(declare-fun |toDec_is| (|toDec_s|) Bool) +(declare-fun |toDec#0| (|toDec_s|) (_ BitVec 8)) ; \value +; yosys-smt2-input value 8 +; yosys-smt2-wire value 8 +; yosys-smt2-witness {"offset": 0, "path": ["\\value"], "smtname": "value", "smtoffset": 0, "type": "input", "width": 8} +(define-fun |toDec_n value| ((state |toDec_s|)) (_ BitVec 8) (|toDec#0| state)) +; yosys-smt2-witness {"offset": 0, "path": ["\\units"], "smtname": 1, "smtoffset": 0, "type": "reg", "width": 8} +(declare-fun |toDec#1| (|toDec_s|) (_ BitVec 8)) ; \units +; yosys-smt2-output units 8 +; yosys-smt2-register units 8 +; yosys-smt2-wire units 8 +(define-fun |toDec_n units| ((state |toDec_s|)) (_ BitVec 8) (|toDec#1| state)) +; yosys-smt2-witness {"offset": 0, "path": ["\\tens"], "smtname": 2, "smtoffset": 0, "type": "reg", "width": 8} +(declare-fun |toDec#2| (|toDec_s|) (_ BitVec 8)) ; \tens +; yosys-smt2-output tens 8 +; yosys-smt2-register tens 8 +; yosys-smt2-wire tens 8 +(define-fun |toDec_n tens| ((state |toDec_s|)) (_ BitVec 8) (|toDec#2| state)) +; yosys-smt2-witness {"offset": 0, "path": ["\\stepCounter"], "smtname": 3, "smtoffset": 0, "type": "reg", "width": 4} +(declare-fun |toDec#3| (|toDec_s|) (_ BitVec 4)) ; \stepCounter +; yosys-smt2-register stepCounter 4 +; yosys-smt2-wire stepCounter 4 +(define-fun |toDec_n stepCounter| ((state |toDec_s|)) (_ BitVec 4) (|toDec#3| state)) +; yosys-smt2-witness {"offset": 0, "path": ["\\state"], "smtname": 4, "smtoffset": 0, "type": "reg", "width": 4} +(declare-fun |toDec#4| (|toDec_s|) (_ BitVec 4)) ; \state +; yosys-smt2-register state 4 +; yosys-smt2-wire state 4 +(define-fun |toDec_n state| ((state |toDec_s|)) (_ BitVec 4) (|toDec#4| state)) +; yosys-smt2-witness {"offset": 0, "path": ["\\hundreds"], "smtname": 5, "smtoffset": 0, "type": "reg", "width": 8} +(declare-fun |toDec#5| (|toDec_s|) (_ BitVec 8)) ; \hundreds +; yosys-smt2-output hundreds 8 +; yosys-smt2-register hundreds 8 +; yosys-smt2-wire hundreds 8 +(define-fun |toDec_n hundreds| ((state |toDec_s|)) (_ BitVec 8) (|toDec#5| state)) +; yosys-smt2-witness {"offset": 0, "path": ["\\digits"], "smtname": 6, "smtoffset": 0, "type": "reg", "width": 12} +(declare-fun |toDec#6| (|toDec_s|) (_ BitVec 12)) ; \digits +; yosys-smt2-register digits 12 +; yosys-smt2-wire digits 12 +(define-fun |toDec_n digits| ((state |toDec_s|)) (_ BitVec 12) (|toDec#6| state)) +(declare-fun |toDec#7| (|toDec_s|) Bool) ; \clk_i +; yosys-smt2-input clk_i 1 +; yosys-smt2-wire clk_i 1 +; yosys-smt2-clock clk_i posedge +; yosys-smt2-witness {"offset": 0, "path": ["\\clk_i"], "smtname": "clk_i", "smtoffset": 0, "type": "posedge", "width": 1} +; yosys-smt2-witness {"offset": 0, "path": ["\\clk_i"], "smtname": "clk_i", "smtoffset": 0, "type": "input", "width": 1} +(define-fun |toDec_n clk_i| ((state |toDec_s|)) Bool (|toDec#7| state)) +; yosys-smt2-witness {"offset": 0, "path": ["\\cachedValue"], "smtname": 8, "smtoffset": 0, "type": "reg", "width": 8} +(declare-fun |toDec#8| (|toDec_s|) (_ BitVec 8)) ; \cachedValue +; yosys-smt2-register cachedValue 8 +; yosys-smt2-wire cachedValue 8 +(define-fun |toDec_n cachedValue| ((state |toDec_s|)) (_ BitVec 8) (|toDec#8| state)) +(define-fun |toDec#9| ((state |toDec_s|)) (_ BitVec 1) (bvnot (ite (|toDec#7| state) #b1 #b0))) ; $auto$rtlil.cc:2461:Not$568 +; yosys-smt2-assume 0 $auto$formalff.cc:758:execute$569 +(define-fun |toDec_u 0| ((state |toDec_s|)) Bool (or (= ((_ extract 0 0) (|toDec#9| state)) #b1) (not true))) ; $auto$formalff.cc:758:execute$569 +(define-fun |toDec#10| ((state |toDec_s|)) Bool (= (|toDec#4| state) #b0010)) ; $procmux$470_CMP +(define-fun |toDec#11| ((state |toDec_s|)) Bool (not (or (= ((_ extract 0 0) (|toDec#4| state)) #b1) (= ((_ extract 1 1) (|toDec#4| state)) #b1) (= ((_ extract 2 2) (|toDec#4| state)) #b1) (= ((_ extract 3 3) (|toDec#4| state)) #b1)))) ; $procmux$471_CMP +(define-fun |toDec#12| ((state |toDec_s|)) (_ BitVec 8) (ite (|toDec#11| state) (|toDec#0| state) (ite (|toDec#10| state) (concat ((_ extract 6 0) (|toDec#8| state)) #b0) (|toDec#8| state)))) ; $0\cachedValue[7:0] +(define-fun |toDec#13| ((state |toDec_s|)) Bool (bvuge ((_ extract 3 0) (|toDec#6| state)) #b0101)) ; $ge$rows.v:156$157_Y +(define-fun |toDec#14| ((state |toDec_s|)) (_ BitVec 2) (ite (|toDec#13| state) #b11 #b00)) ; $auto$wreduce.cc:461:run$530 [1:0] +(define-fun |toDec#15| ((state |toDec_s|)) (_ BitVec 12) (bvadd (|toDec#6| state) (concat #b0000000000 (|toDec#14| state)))) ; $add$rows.v:156$159_Y +(define-fun |toDec#16| ((state |toDec_s|)) Bool (bvuge ((_ extract 7 4) (|toDec#6| state)) #b0101)) ; $ge$rows.v:156$160_Y +(define-fun |toDec#17| ((state |toDec_s|)) (_ BitVec 6) (ite (|toDec#16| state) #b110000 #b000000)) ; $auto$wreduce.cc:461:run$531 [5:0] +(define-fun |toDec#18| ((state |toDec_s|)) (_ BitVec 12) (bvadd (|toDec#15| state) (concat #b000000 (|toDec#17| state)))) ; $add$rows.v:156$162_Y +(define-fun |toDec#19| ((state |toDec_s|)) Bool (bvuge ((_ extract 11 8) (|toDec#6| state)) #b0101)) ; $ge$rows.v:156$163_Y +(define-fun |toDec#20| ((state |toDec_s|)) (_ BitVec 10) (ite (|toDec#19| state) #b1100000000 #b0000000000)) ; $ternary$rows.v:156$164_Y [9:0] +(define-fun |toDec#21| ((state |toDec_s|)) (_ BitVec 12) (bvadd (|toDec#18| state) (concat #b00 (|toDec#20| state)))) ; $add$rows.v:156$165_Y +(define-fun |toDec#22| ((state |toDec_s|)) Bool (= (|toDec#4| state) #b0001)) ; $procmux$479_CMP +(define-fun |toDec#23| ((state |toDec_s|)) (_ BitVec 12) (ite (|toDec#11| state) #b000000000000 (ite (|toDec#22| state) (|toDec#21| state) (ite (|toDec#10| state) (concat ((_ extract 10 0) (|toDec#6| state)) ((_ extract 7 7) (|toDec#8| state))) (|toDec#6| state))))) ; $0\digits[11:0] +(define-fun |toDec#24| ((state |toDec_s|)) (_ BitVec 7) (bvadd #b0110000 (concat #b000 ((_ extract 11 8) (|toDec#6| state))))) ; $add$rows.v:170$168_Y +(define-fun |toDec#25| ((state |toDec_s|)) Bool (= (|toDec#4| state) #b0011)) ; $procmux$482_CMP +(define-fun |toDec#26| ((state |toDec_s|)) (_ BitVec 8) (ite (|toDec#25| state) (concat #b0 (|toDec#24| state)) (|toDec#5| state))) ; $0\hundreds[7:0] +(define-fun |toDec#27| ((state |toDec_s|)) Bool (= (|toDec#3| state) #b0111)) ; $eq$rows.v:162$166_Y +(define-fun |toDec#28| ((state |toDec_s|)) (_ BitVec 2) (ite (|toDec#27| state) #b11 #b01)) ; $auto$wreduce.cc:461:run$529 [1:0] +(define-fun |toDec#29| ((state |toDec_s|)) (_ BitVec 4) (ite (|toDec#11| state) #b0001 (ite (|toDec#22| state) #b0010 (ite (|toDec#10| state) (concat #b00 (|toDec#28| state)) (ite (|toDec#25| state) #b0000 (|toDec#4| state)))))) ; $0\state[3:0] +(define-fun |toDec#30| ((state |toDec_s|)) (_ BitVec 4) (bvadd (|toDec#3| state) #b0001)) ; $add$rows.v:166$167_Y +(define-fun |toDec#31| ((state |toDec_s|)) (_ BitVec 4) (ite (|toDec#27| state) (|toDec#3| state) (|toDec#30| state))) ; $procmux$467_Y +(define-fun |toDec#32| ((state |toDec_s|)) (_ BitVec 4) (ite (|toDec#11| state) #b0000 (ite (|toDec#10| state) (|toDec#31| state) (|toDec#3| state)))) ; $0\stepCounter[3:0] +(define-fun |toDec#33| ((state |toDec_s|)) (_ BitVec 7) (bvadd #b0110000 (concat #b000 ((_ extract 7 4) (|toDec#6| state))))) ; $add$rows.v:171$169_Y +(define-fun |toDec#34| ((state |toDec_s|)) (_ BitVec 8) (ite (|toDec#25| state) (concat #b0 (|toDec#33| state)) (|toDec#2| state))) ; $0\tens[7:0] +(define-fun |toDec#35| ((state |toDec_s|)) (_ BitVec 7) (bvadd #b0110000 (concat #b000 ((_ extract 3 0) (|toDec#6| state))))) ; $add$rows.v:172$170_Y +(define-fun |toDec#36| ((state |toDec_s|)) (_ BitVec 8) (ite (|toDec#25| state) (concat #b0 (|toDec#35| state)) (|toDec#1| state))) ; $0\units[7:0] +(define-fun |toDec_a| ((state |toDec_s|)) Bool true) +(define-fun |toDec_u| ((state |toDec_s|)) Bool + (|toDec_u 0| state) +) +(define-fun |toDec_i| ((state |toDec_s|)) Bool (and + (= (|toDec#1| state) #b00110000) ; units + (= (|toDec#2| state) #b00110000) ; tens + (= (|toDec#3| state) #b0000) ; stepCounter + (= (|toDec#4| state) #b0000) ; state + (= (|toDec#5| state) #b00110000) ; hundreds + (= (|toDec#6| state) #b000000000000) ; digits + (= (|toDec#8| state) #b00000000) ; cachedValue +)) +(define-fun |toDec_h| ((state |toDec_s|)) Bool true) +(define-fun |toDec_t| ((state |toDec_s|) (next_state |toDec_s|)) Bool (and + (= (|toDec#12| state) (|toDec#8| next_state)) ; $procdff$519 \cachedValue + (= (|toDec#23| state) (|toDec#6| next_state)) ; $procdff$518 \digits + (= (|toDec#26| state) (|toDec#5| next_state)) ; $procdff$515 \hundreds + (= (|toDec#29| state) (|toDec#4| next_state)) ; $procdff$514 \state + (= (|toDec#32| state) (|toDec#3| next_state)) ; $procdff$520 \stepCounter + (= (|toDec#34| state) (|toDec#2| next_state)) ; $procdff$516 \tens + (= (|toDec#36| state) (|toDec#1| next_state)) ; $procdff$517 \units +)) ; end of module toDec +; yosys-smt2-module toHex +(declare-sort |toHex_s| 0) +(declare-fun |toHex_is| (|toHex_s|) Bool) +(declare-fun |toHex#0| (|toHex_s|) (_ BitVec 4)) ; \value +; yosys-smt2-input value 4 +; yosys-smt2-wire value 4 +; yosys-smt2-witness {"offset": 0, "path": ["\\value"], "smtname": "value", "smtoffset": 0, "type": "input", "width": 4} +(define-fun |toHex_n value| ((state |toHex_s|)) (_ BitVec 4) (|toHex#0| state)) +; yosys-smt2-witness {"offset": 0, "path": ["\\hexChar"], "smtname": 1, "smtoffset": 0, "type": "reg", "width": 7} +(declare-fun |toHex#1| (|toHex_s|) (_ BitVec 7)) ; \hexChar [6:0] +; yosys-smt2-output hexChar 8 +; yosys-smt2-register hexChar 8 +; yosys-smt2-wire hexChar 8 +(define-fun |toHex_n hexChar| ((state |toHex_s|)) (_ BitVec 8) (concat #b0 (|toHex#1| state))) +(declare-fun |toHex#2| (|toHex_s|) Bool) ; \clk_i +; yosys-smt2-input clk_i 1 +; yosys-smt2-wire clk_i 1 +; yosys-smt2-clock clk_i posedge +; yosys-smt2-witness {"offset": 0, "path": ["\\clk_i"], "smtname": "clk_i", "smtoffset": 0, "type": "posedge", "width": 1} +; yosys-smt2-witness {"offset": 0, "path": ["\\clk_i"], "smtname": "clk_i", "smtoffset": 0, "type": "input", "width": 1} +(define-fun |toHex_n clk_i| ((state |toHex_s|)) Bool (|toHex#2| state)) +(define-fun |toHex#3| ((state |toHex_s|)) (_ BitVec 1) (bvnot (ite (|toHex#2| state) #b1 #b0))) ; $auto$rtlil.cc:2461:Not$565 +; yosys-smt2-assume 0 $auto$formalff.cc:758:execute$566 +(define-fun |toHex_u 0| ((state |toHex_s|)) Bool (or (= ((_ extract 0 0) (|toHex#3| state)) #b1) (not true))) ; $auto$formalff.cc:758:execute$566 +(define-fun |toHex#4| ((state |toHex_s|)) (_ BitVec 7) (bvadd #b0110111 (concat #b000 (|toHex#0| state)))) ; $add$rows.v:126$153_Y +(define-fun |toHex#5| ((state |toHex_s|)) (_ BitVec 7) (bvadd #b0110000 (concat #b000 (|toHex#0| state)))) ; $add$rows.v:126$152_Y +(define-fun |toHex#6| ((state |toHex_s|)) Bool (bvule (|toHex#0| state) #b1001)) ; $le$rows.v:126$151_Y +(define-fun |toHex#7| ((state |toHex_s|)) (_ BitVec 7) (ite (|toHex#6| state) (|toHex#5| state) (|toHex#4| state))) ; $0\hexChar[7:0] +(define-fun |toHex_a| ((state |toHex_s|)) Bool true) +(define-fun |toHex_u| ((state |toHex_s|)) Bool + (|toHex_u 0| state) +) +(define-fun |toHex_i| ((state |toHex_s|)) Bool + (= (bvand (concat #b0 (|toHex#1| state)) #b01111111) #b00110000) ; hexChar +) +(define-fun |toHex_h| ((state |toHex_s|)) Bool true) +(define-fun |toHex_t| ((state |toHex_s|) (next_state |toHex_s|)) Bool + (= (|toHex#7| state) (|toHex#1| next_state)) ; $auto$ff.cc:266:slice$563 \hexChar [6:0] +) ; end of module toHex +; yosys-smt2-module hexDecRow +(declare-sort |hexDecRow_s| 0) +(declare-fun |hexDecRow_is| (|hexDecRow_s|) Bool) +(declare-fun |hexDecRow#0| (|hexDecRow_s|) (_ BitVec 8)) ; \value_i +; yosys-smt2-input value_i 8 +; yosys-smt2-wire value_i 8 +; yosys-smt2-witness {"offset": 0, "path": ["\\value_i"], "smtname": "value_i", "smtoffset": 0, "type": "input", "width": 8} +(define-fun |hexDecRow_n value_i| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#0| state)) +(declare-fun |hexDecRow#1| (|hexDecRow_s|) (_ BitVec 4)) ; \outputCharIndex_i +; yosys-smt2-input outputCharIndex_i 4 +; yosys-smt2-wire outputCharIndex_i 4 +; yosys-smt2-witness {"offset": 0, "path": ["\\outputCharIndex_i"], "smtname": "outputCharIndex_i", "smtoffset": 0, "type": "input", "width": 4} +(define-fun |hexDecRow_n outputCharIndex_i| ((state |hexDecRow_s|)) (_ BitVec 4) (|hexDecRow#1| state)) +; yosys-smt2-anyinit hexDecRow#2 8 rows.v:200.5-217.8 +; yosys-smt2-witness {"offset": 0, "path": ["\\outByteReg"], "smtname": 2, "smtoffset": 0, "type": "init", "width": 8} +(declare-fun |hexDecRow#2| (|hexDecRow_s|) (_ BitVec 8)) ; \outByteReg +; yosys-smt2-output outByte_i 8 +; yosys-smt2-wire outByte_i 8 +(define-fun |hexDecRow_n outByte_i| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#2| state)) +; yosys-smt2-register outByteReg 8 +; yosys-smt2-wire outByteReg 8 +(define-fun |hexDecRow_n outByteReg| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#2| state)) +; yosys-smt2-cell toHex h1 +; yosys-smt2-witness {"path": ["\\h1"], "smtname": "h1", "type": "cell"} +(declare-fun |hexDecRow#3| (|hexDecRow_s|) (_ BitVec 8)) ; \lowerHexChar +(declare-fun |hexDecRow_h h1| (|hexDecRow_s|) |toHex_s|) +; yosys-smt2-wire lowerHexChar 8 +(define-fun |hexDecRow_n lowerHexChar| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#3| state)) +; yosys-smt2-cell toHex h2 +; yosys-smt2-witness {"path": ["\\h2"], "smtname": "h2", "type": "cell"} +(declare-fun |hexDecRow#4| (|hexDecRow_s|) (_ BitVec 8)) ; \higherHexChar +(declare-fun |hexDecRow_h h2| (|hexDecRow_s|) |toHex_s|) +; yosys-smt2-wire higherHexChar 8 +(define-fun |hexDecRow_n higherHexChar| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#4| state)) +; yosys-smt2-wire hexLower 4 +(define-fun |hexDecRow_n hexLower| ((state |hexDecRow_s|)) (_ BitVec 4) ((_ extract 3 0) (|hexDecRow#0| state))) +; yosys-smt2-wire hexHigher 4 +(define-fun |hexDecRow_n hexHigher| ((state |hexDecRow_s|)) (_ BitVec 4) ((_ extract 7 4) (|hexDecRow#0| state))) +; yosys-smt2-witness {"offset": 0, "path": ["\\f_past_valid"], "smtname": 5, "smtoffset": 0, "type": "reg", "width": 1} +(declare-fun |hexDecRow#5| (|hexDecRow_s|) (_ BitVec 1)) ; \f_past_valid +; yosys-smt2-register f_past_valid 1 +; yosys-smt2-wire f_past_valid 1 +(define-fun |hexDecRow_n f_past_valid| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1)) +; yosys-smt2-cell toDec dec +; yosys-smt2-witness {"path": ["\\dec"], "smtname": "dec", "type": "cell"} +(declare-fun |hexDecRow#6| (|hexDecRow_s|) (_ BitVec 8)) ; \decChar3 +(declare-fun |hexDecRow#7| (|hexDecRow_s|) (_ BitVec 8)) ; \decChar2 +(declare-fun |hexDecRow#8| (|hexDecRow_s|) (_ BitVec 8)) ; \decChar1 +(declare-fun |hexDecRow_h dec| (|hexDecRow_s|) |toDec_s|) +; yosys-smt2-wire decChar3 8 +(define-fun |hexDecRow_n decChar3| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#6| state)) +; yosys-smt2-wire decChar2 8 +(define-fun |hexDecRow_n decChar2| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#7| state)) +; yosys-smt2-wire decChar1 8 +(define-fun |hexDecRow_n decChar1| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#8| state)) +(declare-fun |hexDecRow#9| (|hexDecRow_s|) Bool) ; \clk_i +; yosys-smt2-input clk_i 1 +; yosys-smt2-wire clk_i 1 +; yosys-smt2-clock clk_i posedge +; yosys-smt2-witness {"offset": 0, "path": ["\\clk_i"], "smtname": "clk_i", "smtoffset": 0, "type": "posedge", "width": 1} +; yosys-smt2-witness {"offset": 0, "path": ["\\clk_i"], "smtname": "clk_i", "smtoffset": 0, "type": "input", "width": 1} +(define-fun |hexDecRow_n clk_i| ((state |hexDecRow_s|)) Bool (|hexDecRow#9| state)) +; yosys-smt2-anyseq hexDecRow#10 1 $auto$setundef.cc:533:execute$561 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_561"], "smtname": 10, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#10| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_561 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_561 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_561| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#10| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#11 1 $auto$setundef.cc:533:execute$559 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_559"], "smtname": 11, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#11| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_559 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_559 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_559| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#11| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#12 1 $auto$setundef.cc:533:execute$557 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_557"], "smtname": 12, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#12| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_557 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_557 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_557| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#12| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#13 1 $auto$setundef.cc:533:execute$555 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_555"], "smtname": 13, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#13| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_555 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_555 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_555| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#13| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#14 1 $auto$setundef.cc:533:execute$553 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_553"], "smtname": 14, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#14| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_553 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_553 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_553| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#14| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#15 1 $auto$setundef.cc:533:execute$551 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_551"], "smtname": 15, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#15| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_551 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_551 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_551| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#15| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#16 1 $auto$setundef.cc:533:execute$549 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_549"], "smtname": 16, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#16| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_549 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_549 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_549| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#16| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#17 1 $auto$setundef.cc:533:execute$547 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_547"], "smtname": 17, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#17| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_547 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_547 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_547| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#17| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#18 1 $auto$setundef.cc:533:execute$545 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_545"], "smtname": 18, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#18| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_545 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_545 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_545| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#18| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#19 1 $auto$setundef.cc:533:execute$543 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_543"], "smtname": 19, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#19| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_543 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_543 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_543| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#19| state)) #b1)) +; yosys-smt2-anyseq hexDecRow#20 1 $auto$setundef.cc:533:execute$541 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_541"], "smtname": 20, "smtoffset": 0, "type": "seq", "width": 1} +(declare-fun |hexDecRow#20| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyseq_auto_setundef_cc_533_execute_541 +; yosys-smt2-wire _witness_.anyseq_auto_setundef_cc_533_execute_541 1 +(define-fun |hexDecRow_n _witness_.anyseq_auto_setundef_cc_533_execute_541| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#20| state)) #b1)) +; yosys-smt2-anyinit hexDecRow#21 1 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_510"], "smtname": 21, "smtoffset": 0, "type": "init", "width": 1} +(declare-fun |hexDecRow#21| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyinit_procdff_510 +; yosys-smt2-register _witness_.anyinit_procdff_510 1 +; yosys-smt2-wire _witness_.anyinit_procdff_510 1 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_510| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#21| state)) #b1)) +; yosys-smt2-anyinit hexDecRow#22 1 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_508"], "smtname": 22, "smtoffset": 0, "type": "init", "width": 1} +(declare-fun |hexDecRow#22| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyinit_procdff_508 +; yosys-smt2-register _witness_.anyinit_procdff_508 1 +; yosys-smt2-wire _witness_.anyinit_procdff_508 1 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_508| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#22| state)) #b1)) +; yosys-smt2-anyinit hexDecRow#23 1 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_506"], "smtname": 23, "smtoffset": 0, "type": "init", "width": 1} +(declare-fun |hexDecRow#23| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyinit_procdff_506 +; yosys-smt2-register _witness_.anyinit_procdff_506 1 +; yosys-smt2-wire _witness_.anyinit_procdff_506 1 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_506| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#23| state)) #b1)) +; yosys-smt2-anyinit hexDecRow#24 1 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_504"], "smtname": 24, "smtoffset": 0, "type": "init", "width": 1} +(declare-fun |hexDecRow#24| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyinit_procdff_504 +; yosys-smt2-register _witness_.anyinit_procdff_504 1 +; yosys-smt2-wire _witness_.anyinit_procdff_504 1 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_504| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#24| state)) #b1)) +; yosys-smt2-anyinit hexDecRow#25 1 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_502"], "smtname": 25, "smtoffset": 0, "type": "init", "width": 1} +(declare-fun |hexDecRow#25| (|hexDecRow_s|) (_ BitVec 1)) ; \_witness_.anyinit_procdff_502 +; yosys-smt2-register _witness_.anyinit_procdff_502 1 +; yosys-smt2-wire _witness_.anyinit_procdff_502 1 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_502| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#25| state)) #b1)) +; yosys-smt2-anyinit hexDecRow#26 8 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_501"], "smtname": 26, "smtoffset": 0, "type": "init", "width": 8} +(declare-fun |hexDecRow#26| (|hexDecRow_s|) (_ BitVec 8)) ; \_witness_.anyinit_procdff_501 +; yosys-smt2-register _witness_.anyinit_procdff_501 8 +; yosys-smt2-wire _witness_.anyinit_procdff_501 8 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_501| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#26| state)) +; yosys-smt2-anyinit hexDecRow#27 8 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_500"], "smtname": 27, "smtoffset": 0, "type": "init", "width": 8} +(declare-fun |hexDecRow#27| (|hexDecRow_s|) (_ BitVec 8)) ; \_witness_.anyinit_procdff_500 +; yosys-smt2-register _witness_.anyinit_procdff_500 8 +; yosys-smt2-wire _witness_.anyinit_procdff_500 8 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_500| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#27| state)) +; yosys-smt2-anyinit hexDecRow#28 8 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_499"], "smtname": 28, "smtoffset": 0, "type": "init", "width": 8} +(declare-fun |hexDecRow#28| (|hexDecRow_s|) (_ BitVec 8)) ; \_witness_.anyinit_procdff_499 +; yosys-smt2-register _witness_.anyinit_procdff_499 8 +; yosys-smt2-wire _witness_.anyinit_procdff_499 8 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_499| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#28| state)) +; yosys-smt2-anyinit hexDecRow#29 8 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_498"], "smtname": 29, "smtoffset": 0, "type": "init", "width": 8} +(declare-fun |hexDecRow#29| (|hexDecRow_s|) (_ BitVec 8)) ; \_witness_.anyinit_procdff_498 +; yosys-smt2-register _witness_.anyinit_procdff_498 8 +; yosys-smt2-wire _witness_.anyinit_procdff_498 8 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_498| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#29| state)) +; yosys-smt2-anyinit hexDecRow#30 8 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_497"], "smtname": 30, "smtoffset": 0, "type": "init", "width": 8} +(declare-fun |hexDecRow#30| (|hexDecRow_s|) (_ BitVec 8)) ; \_witness_.anyinit_procdff_497 +; yosys-smt2-register _witness_.anyinit_procdff_497 8 +; yosys-smt2-wire _witness_.anyinit_procdff_497 8 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_497| ((state |hexDecRow_s|)) (_ BitVec 8) (|hexDecRow#30| state)) +; yosys-smt2-anyinit hexDecRow#31 4 rows.v:246.9-256.12 +; yosys-smt2-witness {"offset": 0, "path": ["\\_witness_", "\\anyinit_procdff_496"], "smtname": 31, "smtoffset": 0, "type": "init", "width": 4} +(declare-fun |hexDecRow#31| (|hexDecRow_s|) (_ BitVec 4)) ; \_witness_.anyinit_procdff_496 +; yosys-smt2-register _witness_.anyinit_procdff_496 4 +; yosys-smt2-wire _witness_.anyinit_procdff_496 4 +(define-fun |hexDecRow_n _witness_.anyinit_procdff_496| ((state |hexDecRow_s|)) (_ BitVec 4) (|hexDecRow#31| state)) +; yosys-smt2-witness {"offset": 0, "path": ["$formal$rows.v:253$189_EN"], "smtname": 32, "smtoffset": 0, "type": "reg", "width": 1} +(declare-fun |hexDecRow#32| (|hexDecRow_s|) (_ BitVec 1)) ; $formal$rows.v:253$189_EN +; yosys-smt2-register $formal$rows.v:253$189_EN 1 +(define-fun |hexDecRow_n $formal$rows.v:253$189_EN| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#32| state)) #b1)) +; yosys-smt2-witness {"offset": 0, "path": ["$formal$rows.v:252$188_EN"], "smtname": 33, "smtoffset": 0, "type": "reg", "width": 1} +(declare-fun |hexDecRow#33| (|hexDecRow_s|) (_ BitVec 1)) ; $formal$rows.v:252$188_EN +; yosys-smt2-register $formal$rows.v:252$188_EN 1 +(define-fun |hexDecRow_n $formal$rows.v:252$188_EN| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#33| state)) #b1)) +; yosys-smt2-witness {"offset": 0, "path": ["$formal$rows.v:251$187_EN"], "smtname": 34, "smtoffset": 0, "type": "reg", "width": 1} +(declare-fun |hexDecRow#34| (|hexDecRow_s|) (_ BitVec 1)) ; $formal$rows.v:251$187_EN +; yosys-smt2-register $formal$rows.v:251$187_EN 1 +(define-fun |hexDecRow_n $formal$rows.v:251$187_EN| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#34| state)) #b1)) +; yosys-smt2-witness {"offset": 0, "path": ["$formal$rows.v:250$186_EN"], "smtname": 35, "smtoffset": 0, "type": "reg", "width": 1} +(declare-fun |hexDecRow#35| (|hexDecRow_s|) (_ BitVec 1)) ; $formal$rows.v:250$186_EN +; yosys-smt2-register $formal$rows.v:250$186_EN 1 +(define-fun |hexDecRow_n $formal$rows.v:250$186_EN| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#35| state)) #b1)) +; yosys-smt2-witness {"offset": 0, "path": ["$formal$rows.v:249$185_EN"], "smtname": 36, "smtoffset": 0, "type": "reg", "width": 1} +(declare-fun |hexDecRow#36| (|hexDecRow_s|) (_ BitVec 1)) ; $formal$rows.v:249$185_EN +; yosys-smt2-register $formal$rows.v:249$185_EN 1 +(define-fun |hexDecRow_n $formal$rows.v:249$185_EN| ((state |hexDecRow_s|)) Bool (= ((_ extract 0 0) (|hexDecRow#36| state)) #b1)) +(define-fun |hexDecRow#37| ((state |hexDecRow_s|)) (_ BitVec 1) (bvnot (ite (|hexDecRow#9| state) #b1 #b0))) ; $auto$rtlil.cc:2461:Not$571 +; yosys-smt2-assume 0 $auto$formalff.cc:758:execute$572 +(define-fun |hexDecRow_u 0| ((state |hexDecRow_s|)) Bool (or (= ((_ extract 0 0) (|hexDecRow#37| state)) #b1) (not true))) ; $auto$formalff.cc:758:execute$572 +; yosys-smt2-assert 0 $assert$rows.v:253$223 rows.v:253.24-253.62 +(define-fun |hexDecRow_a 0| ((state |hexDecRow_s|)) Bool (or (= ((_ extract 0 0) (|hexDecRow#21| state)) #b1) (not (= ((_ extract 0 0) (|hexDecRow#32| state)) #b1)))) ; $assert$rows.v:253$223 +; yosys-smt2-assert 1 $assert$rows.v:252$222 rows.v:252.24-252.62 +(define-fun |hexDecRow_a 1| ((state |hexDecRow_s|)) Bool (or (= ((_ extract 0 0) (|hexDecRow#22| state)) #b1) (not (= ((_ extract 0 0) (|hexDecRow#33| state)) #b1)))) ; $assert$rows.v:252$222 +; yosys-smt2-assert 2 $assert$rows.v:251$221 rows.v:251.24-251.62 +(define-fun |hexDecRow_a 2| ((state |hexDecRow_s|)) Bool (or (= ((_ extract 0 0) (|hexDecRow#23| state)) #b1) (not (= ((_ extract 0 0) (|hexDecRow#34| state)) #b1)))) ; $assert$rows.v:251$221 +; yosys-smt2-assert 3 $assert$rows.v:250$220 rows.v:250.23-250.65 +(define-fun |hexDecRow_a 3| ((state |hexDecRow_s|)) Bool (or (= ((_ extract 0 0) (|hexDecRow#24| state)) #b1) (not (= ((_ extract 0 0) (|hexDecRow#35| state)) #b1)))) ; $assert$rows.v:250$220 +; yosys-smt2-assert 4 $assert$rows.v:249$219 rows.v:249.23-249.66 +(define-fun |hexDecRow_a 4| ((state |hexDecRow_s|)) Bool (or (= ((_ extract 0 0) (|hexDecRow#25| state)) #b1) (not (= ((_ extract 0 0) (|hexDecRow#36| state)) #b1)))) ; $assert$rows.v:249$219 +(define-fun |hexDecRow#38| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) #b1 (|hexDecRow#10| state))) ; $0$formal$rows.v:240$184_CHECK[0:0]$193 +(define-fun |hexDecRow#39| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) #b1 #b0)) ; $0$formal$rows.v:240$184_EN[0:0]$194 +; yosys-smt2-assert 5 $assert$rows.v:240$218 rows.v:240.29-241.48 +(define-fun |hexDecRow_a 5| ((state |hexDecRow_s|)) Bool (or (= ((_ extract 0 0) (|hexDecRow#38| state)) #b1) (not (= ((_ extract 0 0) (|hexDecRow#39| state)) #b1)))) ; $assert$rows.v:240$218 +(define-fun |hexDecRow#40| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#31| state) #b0101)) ; $procmux$391_CMP +(define-fun |hexDecRow#41| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#40| state) #b1 #b0)) ; $procmux$390_Y +(define-fun |hexDecRow#42| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#41| state) #b0)) ; $0$formal$rows.v:249$185_EN[0:0]$204 +(define-fun |hexDecRow#43| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#31| state) #b0110)) ; $procmux$406_CMP +(define-fun |hexDecRow#44| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#43| state) #b1 #b0)) ; $procmux$405_Y +(define-fun |hexDecRow#45| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#44| state) #b0)) ; $0$formal$rows.v:250$186_EN[0:0]$206 +(define-fun |hexDecRow#46| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#31| state) #b1101)) ; $procmux$419_CMP +(define-fun |hexDecRow#47| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#46| state) #b1 #b0)) ; $procmux$418_Y +(define-fun |hexDecRow#48| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#47| state) #b0)) ; $0$formal$rows.v:251$187_EN[0:0]$208 +(define-fun |hexDecRow#49| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#31| state) #b1110)) ; $procmux$430_CMP +(define-fun |hexDecRow#50| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#49| state) #b1 #b0)) ; $procmux$429_Y +(define-fun |hexDecRow#51| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#50| state) #b0)) ; $0$formal$rows.v:252$188_EN[0:0]$210 +(define-fun |hexDecRow#52| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#31| state) #b1111)) ; $procmux$439_CMP +(define-fun |hexDecRow#53| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#52| state) #b1 #b0)) ; $procmux$438_Y +(define-fun |hexDecRow#54| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#53| state) #b0)) ; $0$formal$rows.v:253$189_EN[0:0]$212 +(define-fun |hexDecRow#55| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#2| state) (|hexDecRow#30| state))) ; $eq$rows.v:249$213_Y +(define-fun |hexDecRow#56| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#40| state) (ite (|hexDecRow#55| state) #b1 #b0) (|hexDecRow#20| state))) ; $procmux$398_Y +(define-fun |hexDecRow#57| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#56| state) (|hexDecRow#19| state))) ; $0$formal$rows.v:249$185_CHECK[0:0]$203 +(define-fun |hexDecRow#58| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#2| state) (|hexDecRow#29| state))) ; $eq$rows.v:250$214_Y +(define-fun |hexDecRow#59| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#43| state) (ite (|hexDecRow#58| state) #b1 #b0) (|hexDecRow#18| state))) ; $procmux$412_Y +(define-fun |hexDecRow#60| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#59| state) (|hexDecRow#17| state))) ; $0$formal$rows.v:250$186_CHECK[0:0]$205 +(define-fun |hexDecRow#61| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#2| state) (|hexDecRow#28| state))) ; $eq$rows.v:251$215_Y +(define-fun |hexDecRow#62| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#46| state) (ite (|hexDecRow#61| state) #b1 #b0) (|hexDecRow#16| state))) ; $procmux$424_Y +(define-fun |hexDecRow#63| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#62| state) (|hexDecRow#15| state))) ; $0$formal$rows.v:251$187_CHECK[0:0]$207 +(define-fun |hexDecRow#64| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#2| state) (|hexDecRow#27| state))) ; $eq$rows.v:252$216_Y +(define-fun |hexDecRow#65| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#49| state) (ite (|hexDecRow#64| state) #b1 #b0) (|hexDecRow#14| state))) ; $procmux$434_Y +(define-fun |hexDecRow#66| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#65| state) (|hexDecRow#13| state))) ; $0$formal$rows.v:252$188_CHECK[0:0]$209 +(define-fun |hexDecRow#67| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#2| state) (|hexDecRow#26| state))) ; $eq$rows.v:253$217_Y +(define-fun |hexDecRow#68| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (|hexDecRow#52| state) (ite (|hexDecRow#67| state) #b1 #b0) (|hexDecRow#12| state))) ; $procmux$442_Y +(define-fun |hexDecRow#69| ((state |hexDecRow_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) (|hexDecRow#68| state) (|hexDecRow#11| state))) ; $0$formal$rows.v:253$189_CHECK[0:0]$211 +(define-fun |hexDecRow#70| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b1111)) ; $procmux$452_CMP +(define-fun |hexDecRow#71| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b1110)) ; $procmux$453_CMP +(define-fun |hexDecRow#72| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b1101)) ; $procmux$454_CMP +(define-fun |hexDecRow#73| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b0011)) ; $procmux$461_CMP +(define-fun |hexDecRow#74| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b1011)) ; $procmux$455_CMP +(define-fun |hexDecRow#75| ((state |hexDecRow_s|)) Bool (or (|hexDecRow#73| state) (|hexDecRow#74| state))) ; $auto$opt_reduce.cc:134:opt_pmux$522 +(define-fun |hexDecRow#76| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b1010)) ; $procmux$456_CMP +(define-fun |hexDecRow#77| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b0001)) ; $procmux$463_CMP +(define-fun |hexDecRow#78| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b1001)) ; $procmux$457_CMP +(define-fun |hexDecRow#79| ((state |hexDecRow_s|)) Bool (or (|hexDecRow#77| state) (|hexDecRow#78| state))) ; $auto$opt_reduce.cc:134:opt_pmux$524 +(define-fun |hexDecRow#80| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b1000)) ; $procmux$458_CMP +(define-fun |hexDecRow#81| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b0110)) ; $procmux$459_CMP +(define-fun |hexDecRow#82| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b0101)) ; $procmux$460_CMP +(define-fun |hexDecRow#83| ((state |hexDecRow_s|)) Bool (= (|hexDecRow#1| state) #b0010)) ; $procmux$462_CMP +(define-fun |hexDecRow#84| ((state |hexDecRow_s|)) Bool (not (or (= ((_ extract 0 0) (|hexDecRow#1| state)) #b1) (= ((_ extract 1 1) (|hexDecRow#1| state)) #b1) (= ((_ extract 2 2) (|hexDecRow#1| state)) #b1) (= ((_ extract 3 3) (|hexDecRow#1| state)) #b1)))) ; $procmux$464_CMP +(define-fun |hexDecRow#85| ((state |hexDecRow_s|)) (_ BitVec 8) (ite (|hexDecRow#84| state) #b01001000 (ite (|hexDecRow#83| state) #b01111000 (ite (|hexDecRow#82| state) (|hexDecRow#4| state) (ite (|hexDecRow#81| state) (|hexDecRow#3| state) (ite (|hexDecRow#80| state) #b01000100 (ite (|hexDecRow#79| state) #b01100101 (ite (|hexDecRow#76| state) #b01100011 (ite (|hexDecRow#75| state) #b00111010 (ite (|hexDecRow#72| state) (|hexDecRow#8| state) (ite (|hexDecRow#71| state) (|hexDecRow#7| state) (ite (|hexDecRow#70| state) (|hexDecRow#6| state) #b00100000)))))))))))) ; $0\outByteReg[7:0] +(define-fun |hexDecRow_a| ((state |hexDecRow_s|)) Bool (and + (|hexDecRow_a 0| state) + (|hexDecRow_a 1| state) + (|hexDecRow_a 2| state) + (|hexDecRow_a 3| state) + (|hexDecRow_a 4| state) + (|hexDecRow_a 5| state) + (|toDec_a| (|hexDecRow_h dec| state)) + (|toHex_a| (|hexDecRow_h h1| state)) + (|toHex_a| (|hexDecRow_h h2| state)) +)) +(define-fun |hexDecRow_u| ((state |hexDecRow_s|)) Bool (and + (|hexDecRow_u 0| state) + (|toDec_u| (|hexDecRow_h dec| state)) + (|toHex_u| (|hexDecRow_h h1| state)) + (|toHex_u| (|hexDecRow_h h2| state)) +)) +(define-fun |hexDecRow_i| ((state |hexDecRow_s|)) Bool (and + (= (= ((_ extract 0 0) (|hexDecRow#5| state)) #b1) false) ; f_past_valid + (= (= ((_ extract 0 0) (|hexDecRow#32| state)) #b1) false) ; $formal$rows.v:253$189_EN + (= (= ((_ extract 0 0) (|hexDecRow#33| state)) #b1) false) ; $formal$rows.v:252$188_EN + (= (= ((_ extract 0 0) (|hexDecRow#34| state)) #b1) false) ; $formal$rows.v:251$187_EN + (= (= ((_ extract 0 0) (|hexDecRow#35| state)) #b1) false) ; $formal$rows.v:250$186_EN + (= (= ((_ extract 0 0) (|hexDecRow#36| state)) #b1) false) ; $formal$rows.v:249$185_EN + (|toDec_i| (|hexDecRow_h dec| state)) + (|toHex_i| (|hexDecRow_h h1| state)) + (|toHex_i| (|hexDecRow_h h2| state)) +)) +(define-fun |hexDecRow_h| ((state |hexDecRow_s|)) Bool (and + (= (|hexDecRow_is| state) (|toDec_is| (|hexDecRow_h dec| state))) + (= (|hexDecRow#0| state) (|toDec_n value| (|hexDecRow_h dec| state))) ; toDec.value + (= (|hexDecRow#6| state) (|toDec_n units| (|hexDecRow_h dec| state))) ; toDec.units + (= (|hexDecRow#7| state) (|toDec_n tens| (|hexDecRow_h dec| state))) ; toDec.tens + (= (|hexDecRow#8| state) (|toDec_n hundreds| (|hexDecRow_h dec| state))) ; toDec.hundreds + (= (|hexDecRow#9| state) (|toDec_n clk_i| (|hexDecRow_h dec| state))) ; toDec.clk_i + (= (|hexDecRow_is| state) (|toHex_is| (|hexDecRow_h h1| state))) + (= ((_ extract 3 0) (|hexDecRow#0| state)) (|toHex_n value| (|hexDecRow_h h1| state))) ; toHex.value + (= (|hexDecRow#3| state) (|toHex_n hexChar| (|hexDecRow_h h1| state))) ; toHex.hexChar + (= (|hexDecRow#9| state) (|toHex_n clk_i| (|hexDecRow_h h1| state))) ; toHex.clk_i + (= (|hexDecRow_is| state) (|toHex_is| (|hexDecRow_h h2| state))) + (= ((_ extract 7 4) (|hexDecRow#0| state)) (|toHex_n value| (|hexDecRow_h h2| state))) ; toHex.value + (= (|hexDecRow#4| state) (|toHex_n hexChar| (|hexDecRow_h h2| state))) ; toHex.hexChar + (= (|hexDecRow#9| state) (|toHex_n clk_i| (|hexDecRow_h h2| state))) ; toHex.clk_i + (|toDec_h| (|hexDecRow_h dec| state)) + (|toHex_h| (|hexDecRow_h h1| state)) + (|toHex_h| (|hexDecRow_h h2| state)) +)) +(define-fun |hexDecRow_t| ((state |hexDecRow_s|) (next_state |hexDecRow_s|)) Bool (and + (= (|hexDecRow#42| state) (|hexDecRow#36| next_state)) ; $procdff$503 $formal$rows.v:249$185_EN + (= (|hexDecRow#45| state) (|hexDecRow#35| next_state)) ; $procdff$505 $formal$rows.v:250$186_EN + (= (|hexDecRow#48| state) (|hexDecRow#34| next_state)) ; $procdff$507 $formal$rows.v:251$187_EN + (= (|hexDecRow#51| state) (|hexDecRow#33| next_state)) ; $procdff$509 $formal$rows.v:252$188_EN + (= (|hexDecRow#54| state) (|hexDecRow#32| next_state)) ; $procdff$511 $formal$rows.v:253$189_EN + (= (|hexDecRow#1| state) (|hexDecRow#31| next_state)) ; $procdff$496 \_witness_.anyinit_procdff_496 + (= (|hexDecRow#4| state) (|hexDecRow#30| next_state)) ; $procdff$497 \_witness_.anyinit_procdff_497 + (= (|hexDecRow#3| state) (|hexDecRow#29| next_state)) ; $procdff$498 \_witness_.anyinit_procdff_498 + (= (|hexDecRow#8| state) (|hexDecRow#28| next_state)) ; $procdff$499 \_witness_.anyinit_procdff_499 + (= (|hexDecRow#7| state) (|hexDecRow#27| next_state)) ; $procdff$500 \_witness_.anyinit_procdff_500 + (= (|hexDecRow#6| state) (|hexDecRow#26| next_state)) ; $procdff$501 \_witness_.anyinit_procdff_501 + (= (|hexDecRow#57| state) (|hexDecRow#25| next_state)) ; $procdff$502 \_witness_.anyinit_procdff_502 + (= (|hexDecRow#60| state) (|hexDecRow#24| next_state)) ; $procdff$504 \_witness_.anyinit_procdff_504 + (= (|hexDecRow#63| state) (|hexDecRow#23| next_state)) ; $procdff$506 \_witness_.anyinit_procdff_506 + (= (|hexDecRow#66| state) (|hexDecRow#22| next_state)) ; $procdff$508 \_witness_.anyinit_procdff_508 + (= (|hexDecRow#69| state) (|hexDecRow#21| next_state)) ; $procdff$510 \_witness_.anyinit_procdff_510 + (= #b1 (|hexDecRow#5| next_state)) ; $procdff$512 \f_past_valid + (= (|hexDecRow#85| state) (|hexDecRow#2| next_state)) ; $procdff$513 \outByteReg + (|toDec_t| (|hexDecRow_h dec| state) (|hexDecRow_h dec| next_state)) + (|toHex_t| (|hexDecRow_h h1| state) (|hexDecRow_h h1| next_state)) + (|toHex_t| (|hexDecRow_h h2| state) (|hexDecRow_h h2| next_state)) +)) ; end of module hexDecRow +; yosys-smt2-topmod hexDecRow +; end of yosys output diff --git a/screen_data/hexDecRow/model/design_smt2.ys b/screen_data/hexDecRow/model/design_smt2.ys new file mode 100644 index 0000000..2138c4f --- /dev/null +++ b/screen_data/hexDecRow/model/design_smt2.ys @@ -0,0 +1,7 @@ +# running in hexDecRow/model/ +read_ilang design_prep.il +hierarchy -smtcheck +formalff -assume +dffunmap +stat +write_smt2 -wires design_smt2.smt2 diff --git a/screen_data/hexDecRow/src/rows.v b/screen_data/hexDecRow/src/rows.v new file mode 100644 index 0000000..4222126 --- /dev/null +++ b/screen_data/hexDecRow/src/rows.v @@ -0,0 +1,410 @@ +`ifdef FORMAL +`default_nettype none +`endif +module uartTextRow ( + input clk_i, + input byteReady_i, + input [7:0] data_i, + input [3:0] outputCharIndex_i, + output [7:0] outByte_o +); + localparam bufferWidth = 128; + reg [(bufferWidth-1):0] textBuffer = 0; + reg [3:0] inputCharIndex = 0; + reg [1:0] state = 0; + + localparam WAIT_FOR_NEXT_CHAR_STATE = 0; + localparam WAIT_FOR_TRANSFER_FINISH = 1; + localparam SAVING_CHARACTER_STATE = 2; + + always @(posedge clk_i) begin + case (state) + WAIT_FOR_NEXT_CHAR_STATE: begin + if (byteReady_i == 0) + state <= WAIT_FOR_TRANSFER_FINISH; + end + WAIT_FOR_TRANSFER_FINISH: begin + if (byteReady_i == 1) + state <= SAVING_CHARACTER_STATE; + end + SAVING_CHARACTER_STATE: begin + if (data_i == 8'd8 || data_i == 8'd127) begin + inputCharIndex <= inputCharIndex - 1; + textBuffer[({4'd0,inputCharIndex-4'd1}<<3)+:8] <= 8'd32; + end + else begin + inputCharIndex <= inputCharIndex + 1; + textBuffer[({4'd0,inputCharIndex}<<3)+:8] <= data_i; + end + state <= WAIT_FOR_NEXT_CHAR_STATE; + end + endcase + end + + assign outByte_o = textBuffer[({4'd0, outputCharIndex_i} << 3)+:8]; + + // + // FORMAL VERIFICATION + // + `ifdef FORMAL + + `ifdef UART_TEXT_ROW + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that outByte_o is assigned correctly + always @(*) + if(f_past_valid) + assert(outByte_o == (textBuffer[({4'd0, outputCharIndex_i} << 3)+:8])); + + // + // Formal Verification + // + always @(posedge clk_i) begin + if((f_past_valid)) begin + case ($past(state)) + SAVING_CHARACTER_STATE: begin + // `ASSUME(data_i == 8'd8 || data_i == 8'd127); + if ($past(data_i) == 8'd8 || $past(data_i) == 8'd127) begin + if($past(inputCharIndex) != 0) + assert(inputCharIndex == ($past(inputCharIndex) - 1)); + assert(textBuffer[({4'd0, $past(inputCharIndex)-4'd1}<<3)+:8] == 8'd32); + end else begin + if($past(inputCharIndex) != 8'hF) + assert(inputCharIndex == ($past(inputCharIndex) + 1)); + assert(textBuffer[({4'd0,$past(inputCharIndex)}<<3)+:8] == $past(data_i)); + end + end + endcase + end + end + +`endif + +endmodule + +module binaryRow( + input clk_i, + input [7:0] value, + input [3:0] outputCharIndex, + output [7:0] outByte +); + reg [7:0] outByteReg; + wire [2:0] bitNumber; + + assign bitNumber = outputCharIndex - 5; + + always @(posedge clk_i) begin + case (outputCharIndex) + 0: outByteReg <= "B"; + 1: outByteReg <= "i"; + 2: outByteReg <= "n"; + 3: outByteReg <= ":"; + 4: outByteReg <= " "; + 13, 14, 15: outByteReg <= " "; + default: outByteReg <= (value[7-bitNumber]) ? "1" : "0"; + endcase + end + + assign outByte = outByteReg; +endmodule + +module toHex( + input clk_i, + input [3:0] value, + output reg [7:0] hexChar = "0" +); + always @(posedge clk_i) begin + hexChar <= (value <= 9) ? 8'd48 + value : 8'd55 + value; + end +endmodule + +module toDec( + input clk_i, + input [7:0] value, + output reg [7:0] hundreds = "0", + output reg [7:0] tens = "0", + output reg [7:0] units = "0" +); + reg [11:0] digits = 0; + reg [7:0] cachedValue = 0; + reg [3:0] stepCounter = 0; + reg [3:0] state = 0; + + localparam START_STATE = 0; + localparam ADD3_STATE = 1; + localparam SHIFT_STATE = 2; + localparam DONE_STATE = 3; + + always @(posedge clk_i) begin + case (state) + START_STATE: begin + cachedValue <= value; + stepCounter <= 0; + digits <= 0; + state <= ADD3_STATE; + end + ADD3_STATE: begin + digits <= digits + ((digits[3:0] >= 5) ? 12'd3 : 12'd0) + ((digits[7:4] >= 5) ? 12'd48 : 12'd0) + ((digits[11:8] >= 5) ? 12'd768 : 12'd0); + state <= SHIFT_STATE; + end + SHIFT_STATE: begin + digits <= {digits[10:0],cachedValue[7]}; + cachedValue <= {cachedValue[6:0],1'b0}; + if (stepCounter == 7) + state <= DONE_STATE; + else begin + state <= ADD3_STATE; + stepCounter <= stepCounter + 1; + end + end + DONE_STATE: begin + hundreds <= 8'd48 + digits[11:8]; + tens <= 8'd48 + digits[7:4]; + units <= 8'd48 + digits[3:0]; + state <= START_STATE; + end + endcase + end +endmodule + + +module hexDecRow( + input clk_i, + input [7:0] value_i, + input [3:0] outputCharIndex_i, + output [7:0] outByte_i +); + reg [7:0] outByteReg; + + wire [3:0] hexLower, hexHigher; + wire [7:0] lowerHexChar, higherHexChar; + + assign hexLower = value_i[3:0]; + assign hexHigher = value_i[7:4]; + + toHex h1(clk_i, hexLower, lowerHexChar); + toHex h2(clk_i, hexHigher, higherHexChar); + + wire [7:0] decChar1, decChar2, decChar3; + toDec dec(clk_i, value_i, decChar1, decChar2, decChar3); + + always @(posedge clk_i) begin + case (outputCharIndex_i) + 0: outByteReg <= "H"; + 1: outByteReg <= "e"; + 2: outByteReg <= "x"; + 3: outByteReg <= ":"; + 5: outByteReg <= higherHexChar; + 6: outByteReg <= lowerHexChar; + 8: outByteReg <= "D"; + 9: outByteReg <= "e"; + 10: outByteReg <= "c"; + 11: outByteReg <= ":"; + 13: outByteReg <= decChar1; + 14: outByteReg <= decChar2; + 15: outByteReg <= decChar3; + default: outByteReg <= " "; + endcase + end + + assign outByte_i = outByteReg; + + // + // FORMAL VERIFICATION + // + `ifdef FORMAL + + `ifdef HEX_DEC_ROW + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that outByte_i is assigned correctly + always @(*) + if(f_past_valid) + assert(outByte_i == outByteReg); + + // + // Contract + // + always @(posedge clk_i) begin + if(f_past_valid) begin + case ($past(outputCharIndex_i)) + 5: assert(outByteReg == $past(higherHexChar)); + 6: assert(outByteReg == $past(lowerHexChar)); + 13: assert(outByteReg == $past(decChar1)); + 14: assert(outByteReg == $past(decChar2)); + 15: assert(outByteReg == $past(decChar3)); + endcase + end + end + + + `endif // FORMAL +endmodule + +module progressRow( + input clk_i, + input reset_i, + input [7:0] value_i, + input [9:0] pixelAddress_i, + output [7:0] outByte_o +); + reg [7:0] outByteReg; + reg [7:0] bar, border; + wire topRow; + wire [6:0] column; + + assign topRow = !pixelAddress_i[7]; + assign column = pixelAddress_i[6:0]; + + always @(posedge clk_i) begin + if (topRow) begin + case (column) + 0, 127: begin + bar = 8'b1100_0000; + border = 8'b1100_0000; + end + 1, 126: begin + bar = 8'b1110_0000; + border = 8'b0110_0000; + end + 2, 125: begin + bar = 8'b1110_0000; + border = 8'b0011_0000; + end + default: begin + bar = 8'b1111_0000; + border = 8'b0001_0000; + end + endcase + end else begin + case (column) + 0, 127: begin + bar = 8'b0000_0011; + border = 8'b0000_0011; + end + 1, 126: begin + bar = 8'b0000_0111; + border = 8'b0000_0110; + end + 2, 125: begin + bar = 8'b0000_0111; + border = 8'b0000_1100; + end + default: begin + bar = 8'b0000_1111; + border = 8'b0000_1000; + end + endcase + end + + if (column > value_i[7:1]) + outByteReg <= border; + else + outByteReg <= bar; + end + + assign outByte_o = outByteReg; + + // + // FORMAL VERIFICATION + // + `ifdef FORMAL + + `ifdef PROGRESS_ROW + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that topRow gets assigned correctly + always @(*) + if(f_past_valid) + assert(topRow == !pixelAddress_i[7]); + + // Prove that column gets assigned correctly + always @(*) + if(f_past_valid) + assert(column == pixelAddress_i[6:0]); + + // Prove that outByte_o gets assigned correctly + always @(*) + if(f_past_valid) + assert(outByte_o == outByteReg); + + + + // + // Contract + // + always @(posedge clk_i) begin + if((f_past_valid)&&($past(f_past_valid))&&(!reset_i)) begin + `ASSUME(pixelAddress_i == $past(pixelAddress_i)); + if (topRow) begin + case (column) + 0, 127: begin + assert(bar == 8'b1100_0000); + assert(border == 8'b1100_0000); + end + 1, 126: begin + assert(bar == 8'b1110_0000); + assert(border == 8'b0110_0000); + end + 2, 125: begin + assert(bar == 8'b1110_0000); + assert(border == 8'b0011_0000); + end + default: begin + assert(bar == 8'b1111_0000); + assert(border == 8'b0001_0000); + end + endcase + end else begin + case (column) + 0, 127: begin + assert(bar == 8'b0000_0011); + assert(border == 8'b0000_0011); + end + 1, 126: begin + assert(bar == 8'b0000_0111); + assert(border == 8'b0000_0110); + end + 2, 125: begin + assert(bar == 8'b0000_0111); + assert(border == 8'b0000_1100); + end + default: begin + assert(bar == 8'b0000_1111); + assert(border == 8'b0000_1000); + end + endcase + end + end + end + + `endif + +endmodule \ No newline at end of file diff --git a/screen_data/hexDecRow/status b/screen_data/hexDecRow/status new file mode 100644 index 0000000..11ec008 --- /dev/null +++ b/screen_data/hexDecRow/status @@ -0,0 +1 @@ +PASS 0 0 diff --git a/screen_data/progressRow.sby b/screen_data/progressRow.sby new file mode 100644 index 0000000..5f849d7 --- /dev/null +++ b/screen_data/progressRow.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DPROGRESS_ROW -formal rows.v +prep -top progressRow + +[files] +rows.v diff --git a/screen_data/rows.v b/screen_data/rows.v index a4e7ef5..4222126 100644 --- a/screen_data/rows.v +++ b/screen_data/rows.v @@ -1,11 +1,12 @@ +`ifdef FORMAL `default_nettype none - +`endif module uartTextRow ( - input clk, - input byteReady, - input [7:0] data, - input [3:0] outputCharIndex, - output [7:0] outByte + input clk_i, + input byteReady_i, + input [7:0] data_i, + input [3:0] outputCharIndex_i, + output [7:0] outByte_o ); localparam bufferWidth = 128; reg [(bufferWidth-1):0] textBuffer = 0; @@ -16,35 +17,82 @@ module uartTextRow ( localparam WAIT_FOR_TRANSFER_FINISH = 1; localparam SAVING_CHARACTER_STATE = 2; - always @(posedge clk) begin + always @(posedge clk_i) begin case (state) WAIT_FOR_NEXT_CHAR_STATE: begin - if (byteReady == 0) + if (byteReady_i == 0) state <= WAIT_FOR_TRANSFER_FINISH; end WAIT_FOR_TRANSFER_FINISH: begin - if (byteReady == 1) + if (byteReady_i == 1) state <= SAVING_CHARACTER_STATE; end SAVING_CHARACTER_STATE: begin - if (data == 8'd8 || data == 8'd127) begin + if (data_i == 8'd8 || data_i == 8'd127) begin inputCharIndex <= inputCharIndex - 1; textBuffer[({4'd0,inputCharIndex-4'd1}<<3)+:8] <= 8'd32; end else begin inputCharIndex <= inputCharIndex + 1; - textBuffer[({4'd0,inputCharIndex}<<3)+:8] <= data; + textBuffer[({4'd0,inputCharIndex}<<3)+:8] <= data_i; end state <= WAIT_FOR_NEXT_CHAR_STATE; end endcase end - assign outByte = textBuffer[({4'd0, outputCharIndex} << 3)+:8]; + assign outByte_o = textBuffer[({4'd0, outputCharIndex_i} << 3)+:8]; + + // + // FORMAL VERIFICATION + // + `ifdef FORMAL + + `ifdef UART_TEXT_ROW + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that outByte_o is assigned correctly + always @(*) + if(f_past_valid) + assert(outByte_o == (textBuffer[({4'd0, outputCharIndex_i} << 3)+:8])); + + // + // Formal Verification + // + always @(posedge clk_i) begin + if((f_past_valid)) begin + case ($past(state)) + SAVING_CHARACTER_STATE: begin + // `ASSUME(data_i == 8'd8 || data_i == 8'd127); + if ($past(data_i) == 8'd8 || $past(data_i) == 8'd127) begin + if($past(inputCharIndex) != 0) + assert(inputCharIndex == ($past(inputCharIndex) - 1)); + assert(textBuffer[({4'd0, $past(inputCharIndex)-4'd1}<<3)+:8] == 8'd32); + end else begin + if($past(inputCharIndex) != 8'hF) + assert(inputCharIndex == ($past(inputCharIndex) + 1)); + assert(textBuffer[({4'd0,$past(inputCharIndex)}<<3)+:8] == $past(data_i)); + end + end + endcase + end + end + +`endif + endmodule module binaryRow( - input clk, + input clk_i, input [7:0] value, input [3:0] outputCharIndex, output [7:0] outByte @@ -54,7 +102,7 @@ module binaryRow( assign bitNumber = outputCharIndex - 5; - always @(posedge clk) begin + always @(posedge clk_i) begin case (outputCharIndex) 0: outByteReg <= "B"; 1: outByteReg <= "i"; @@ -70,17 +118,17 @@ module binaryRow( endmodule module toHex( - input clk, + input clk_i, input [3:0] value, output reg [7:0] hexChar = "0" ); - always @(posedge clk) begin + always @(posedge clk_i) begin hexChar <= (value <= 9) ? 8'd48 + value : 8'd55 + value; end endmodule module toDec( - input clk, + input clk_i, input [7:0] value, output reg [7:0] hundreds = "0", output reg [7:0] tens = "0", @@ -96,7 +144,7 @@ module toDec( localparam SHIFT_STATE = 2; localparam DONE_STATE = 3; - always @(posedge clk) begin + always @(posedge clk_i) begin case (state) START_STATE: begin cachedValue <= value; @@ -130,27 +178,27 @@ endmodule module hexDecRow( - input clk, - input [7:0] value, - input [3:0] outputCharIndex, - output [7:0] outByte + input clk_i, + input [7:0] value_i, + input [3:0] outputCharIndex_i, + output [7:0] outByte_i ); reg [7:0] outByteReg; wire [3:0] hexLower, hexHigher; wire [7:0] lowerHexChar, higherHexChar; - assign hexLower = value[3:0]; - assign hexHigher = value[7:4]; + assign hexLower = value_i[3:0]; + assign hexHigher = value_i[7:4]; - toHex h1(clk, hexLower, lowerHexChar); - toHex h2(clk, hexHigher, higherHexChar); + toHex h1(clk_i, hexLower, lowerHexChar); + toHex h2(clk_i, hexHigher, higherHexChar); wire [7:0] decChar1, decChar2, decChar3; - toDec dec(clk, value, decChar1, decChar2, decChar3); + toDec dec(clk_i, value_i, decChar1, decChar2, decChar3); - always @(posedge clk) begin - case (outputCharIndex) + always @(posedge clk_i) begin + case (outputCharIndex_i) 0: outByteReg <= "H"; 1: outByteReg <= "e"; 2: outByteReg <= "x"; @@ -168,70 +216,195 @@ module hexDecRow( endcase end - assign outByte = outByteReg; + assign outByte_i = outByteReg; + + // + // FORMAL VERIFICATION + // + `ifdef FORMAL + + `ifdef HEX_DEC_ROW + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that outByte_i is assigned correctly + always @(*) + if(f_past_valid) + assert(outByte_i == outByteReg); + + // + // Contract + // + always @(posedge clk_i) begin + if(f_past_valid) begin + case ($past(outputCharIndex_i)) + 5: assert(outByteReg == $past(higherHexChar)); + 6: assert(outByteReg == $past(lowerHexChar)); + 13: assert(outByteReg == $past(decChar1)); + 14: assert(outByteReg == $past(decChar2)); + 15: assert(outByteReg == $past(decChar3)); + endcase + end + end + + + `endif // FORMAL endmodule module progressRow( - input clk, - input [7:0] value, - input [9:0] pixelAddress, - output [7:0] outByte + input clk_i, + input reset_i, + input [7:0] value_i, + input [9:0] pixelAddress_i, + output [7:0] outByte_o ); reg [7:0] outByteReg; reg [7:0] bar, border; wire topRow; wire [6:0] column; - assign topRow = !pixelAddress[7]; - assign column = pixelAddress[6:0]; + assign topRow = !pixelAddress_i[7]; + assign column = pixelAddress_i[6:0]; - always @(posedge clk) begin + always @(posedge clk_i) begin if (topRow) begin case (column) 0, 127: begin - bar = 8'b11000000; - border = 8'b11000000; + bar = 8'b1100_0000; + border = 8'b1100_0000; end 1, 126: begin - bar = 8'b11100000; - border = 8'b01100000; + bar = 8'b1110_0000; + border = 8'b0110_0000; end 2, 125: begin - bar = 8'b11100000; - border = 8'b00110000; + bar = 8'b1110_0000; + border = 8'b0011_0000; end default: begin - bar = 8'b11110000; - border = 8'b00010000; + bar = 8'b1111_0000; + border = 8'b0001_0000; end endcase - end - else begin + end else begin case (column) 0, 127: begin - bar = 8'b00000011; - border = 8'b00000011; + bar = 8'b0000_0011; + border = 8'b0000_0011; end 1, 126: begin - bar = 8'b00000111; - border = 8'b00000110; + bar = 8'b0000_0111; + border = 8'b0000_0110; end 2, 125: begin - bar = 8'b00000111; - border = 8'b00001100; + bar = 8'b0000_0111; + border = 8'b0000_1100; end default: begin - bar = 8'b00001111; - border = 8'b00001000; + bar = 8'b0000_1111; + border = 8'b0000_1000; end endcase end - if (column > value[7:1]) + if (column > value_i[7:1]) outByteReg <= border; else outByteReg <= bar; end - assign outByte = outByteReg; + assign outByte_o = outByteReg; + + // + // FORMAL VERIFICATION + // + `ifdef FORMAL + + `ifdef PROGRESS_ROW + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that topRow gets assigned correctly + always @(*) + if(f_past_valid) + assert(topRow == !pixelAddress_i[7]); + + // Prove that column gets assigned correctly + always @(*) + if(f_past_valid) + assert(column == pixelAddress_i[6:0]); + + // Prove that outByte_o gets assigned correctly + always @(*) + if(f_past_valid) + assert(outByte_o == outByteReg); + + + + // + // Contract + // + always @(posedge clk_i) begin + if((f_past_valid)&&($past(f_past_valid))&&(!reset_i)) begin + `ASSUME(pixelAddress_i == $past(pixelAddress_i)); + if (topRow) begin + case (column) + 0, 127: begin + assert(bar == 8'b1100_0000); + assert(border == 8'b1100_0000); + end + 1, 126: begin + assert(bar == 8'b1110_0000); + assert(border == 8'b0110_0000); + end + 2, 125: begin + assert(bar == 8'b1110_0000); + assert(border == 8'b0011_0000); + end + default: begin + assert(bar == 8'b1111_0000); + assert(border == 8'b0001_0000); + end + endcase + end else begin + case (column) + 0, 127: begin + assert(bar == 8'b0000_0011); + assert(border == 8'b0000_0011); + end + 1, 126: begin + assert(bar == 8'b0000_0111); + assert(border == 8'b0000_0110); + end + 2, 125: begin + assert(bar == 8'b0000_0111); + assert(border == 8'b0000_1100); + end + default: begin + assert(bar == 8'b0000_1111); + assert(border == 8'b0000_1000); + end + endcase + end + end + end + + `endif + endmodule \ No newline at end of file diff --git a/screen_data/run_formal_verification.sh b/screen_data/run_formal_verification.sh new file mode 100644 index 0000000..dc1b444 --- /dev/null +++ b/screen_data/run_formal_verification.sh @@ -0,0 +1,25 @@ +#!/bin/bash + +# Start +echo "Running Formal Verification..." + +# UART +echo " uart" +sby -f uart.sby + +# SCREEN +echo " screen" +sby -f screen.sby + +# TEXT +echo " text" +sby -f text.sby + +# ROWS +echo " rows" +echo " module uartTextRow()" +sby -f uartTextRow.sby +echo " module progressRow()" +sby -f progressRow.sby +echo " module hexDecRow()" +sby -f hexDecRow.sby \ No newline at end of file diff --git a/screen_data/screen.sby b/screen_data/screen.sby new file mode 100644 index 0000000..8f587db --- /dev/null +++ b/screen_data/screen.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DSCREEN -formal screen.v +prep -top screen + +[files] +screen.v diff --git a/screen_data/screen.v b/screen_data/screen.v index f1dba87..8785eb7 100644 --- a/screen_data/screen.v +++ b/screen_data/screen.v @@ -1,143 +1,250 @@ +`ifdef FORMAL `default_nettype none - -module screen -#( - parameter STARTUP_WAIT = 32'd10000000 +`endif +module screen #( +`ifdef FORMAL + parameter STARTUP_WAIT = 32'd25 +`else + parameter STARTUP_WAIT = 32'd10000000 +`endif ) ( - input clk, - output ioSclk, - output ioSdin, - output ioCs, - output ioDc, - output ioReset, - output [9:0] pixelAddress, - input [7:0] pixelData + input clk_i, + input reset_i, + // OLED + output io_sclk_o, + output io_sdin_o, + output io_cs_o, + output io_dc_o, + output io_reset_o, + output [9:0] pixelAddress_i, + input [7:0] pixelData_i ); - localparam STATE_INIT_POWER = 8'd0; localparam STATE_LOAD_INIT_CMD = 8'd1; localparam STATE_SEND = 8'd2; localparam STATE_CHECK_FINISHED_INIT = 8'd3; localparam STATE_LOAD_DATA = 8'd4; - reg [32:0] counter = 0; - reg [2:0] state = 0; + localparam STARTUP_WAIT_2x = 2 * STARTUP_WAIT; + localparam STARTUP_WAIT_3x = 3 * STARTUP_WAIT; + localparam STARTUP_WAIT_MAX = STARTUP_WAIT_3x; + + localparam MAX_NUMBER_OF_PIXELS = 136; + reg [32:0] counter = 0; + reg [2:0] state = STATE_INIT_POWER; + reg dc = 1; reg sclk = 1; reg sdin = 0; reg reset = 1; reg cs = 0; - + reg [7:0] dataToSend = 0; reg [3:0] bitNumber = 0; reg [9:0] pixelCounter = 0; localparam SETUP_INSTRUCTIONS = 23; reg [(SETUP_INSTRUCTIONS*8)-1:0] startupCommands = { - 8'hAE, // display off - - 8'h81, // contast value to 0x7F according to datasheet - 8'h7F, - - 8'hA6, // normal screen mode (not inverted) - - 8'h20, // horizontal addressing mode - 8'h00, - - 8'hC8, // normal scan direction - - 8'h40, // first line to start scanning from - - 8'hA1, // address 0 is segment 0 - - 8'hA8, // mux ratio - 8'h3f, // 63 (64 -1) - - 8'hD3, // display offset - 8'h00, // no offset - - 8'hD5, // clock divide ratio - 8'h80, // set to default ratio/osc frequency + 8'hAE, // display off + 8'h81, // contast value to 0x7F according to datasheet + 8'h7F, + 8'hA6, // normal screen mode (not inverted) + 8'h20, // horizontal addressing mode + 8'h00, + 8'hC8, // normal scan direction + 8'h40, // first line to start scanning from + 8'hA1, // address 0 is segment 0 + 8'hA8, // mux ratio + 8'h3f, // 63 (64 -1) + 8'hD3, // display offset + 8'h00, // no offset + 8'hD5, // clock divide ratio + 8'h80, // set to default ratio/osc frequency + 8'hD9, // set precharge + 8'h22, // switch precharge to 0x22 default + 8'hDB, // vcom deselect level + 8'h20, // 0x20 + 8'h8D, // charge pump config + 8'h14, // enable charge pump + 8'hA4, // resume RAM content + 8'hAF // display on + }; + reg [7:0] commandIndex = SETUP_INSTRUCTIONS * 8; - 8'hD9, // set precharge - 8'h22, // switch precharge to 0x22 default + assign io_sclk_o = sclk; + assign io_sdin_o = sdin; + assign io_dc_o = dc; + assign io_reset_o = reset; + assign io_cs_o = cs; + + // State Machine + always @(posedge clk_i) begin + if(reset_i) begin + counter <= 0; + state <= STATE_INIT_POWER; + dc <= 1; + sclk <= 1; + sdin <= 0; + reset <= 1; + cs <= 0; + dataToSend <= 0; + bitNumber <= 0; + pixelCounter <= 0; + end else begin + case (state) + STATE_INIT_POWER: begin + counter <= counter + 1; + if (counter < STARTUP_WAIT) + reset <= 1; + else if (counter < STARTUP_WAIT_2x) + reset <= 0; + else if (counter < STARTUP_WAIT_3x) + reset <= 1; + else begin + state <= STATE_LOAD_INIT_CMD; + counter <= 32'b0; + end + end + STATE_LOAD_INIT_CMD: begin + dc <= 0; + dataToSend <= startupCommands[(commandIndex-1)-:8'd8]; + state <= STATE_SEND; + bitNumber <= 3'd7; + cs <= 0; + commandIndex <= commandIndex - 8'd8; + end + STATE_SEND: begin + if (counter == 32'd0) begin + sclk <= 0; + sdin <= dataToSend[bitNumber]; + counter <= 32'd1; + end else begin + counter <= 32'd0; + sclk <= 1; + if (bitNumber == 0) + state <= STATE_CHECK_FINISHED_INIT; + else + bitNumber <= bitNumber - 1; + end + end + STATE_CHECK_FINISHED_INIT: begin + cs <= 1; + if (commandIndex == 0) + state <= STATE_LOAD_DATA; + else + state <= STATE_LOAD_INIT_CMD; + end + STATE_LOAD_DATA: begin + pixelCounter <= pixelCounter + 1; + cs <= 0; + dc <= 1; + bitNumber <= 3'd7; + state <= STATE_SEND; + dataToSend <= pixelData_i; + end + endcase + end + end - 8'hDB, // vcom deselect level - 8'h20, // 0x20 + assign pixelAddress_i = pixelCounter; + +// +// FORMAL VERIFICATION +// +`ifdef FORMAL + + `ifdef SCREEN + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that state is always in a valid state + always@(*) + if((f_past_valid)&&(!reset_i)) + assert(state <= STATE_LOAD_DATA); + + // Prove that counter is always valid + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(counter <= STARTUP_WAIT_MAX); + + // Prove that after a reset registers get initialized + always @(posedge clk_i) begin + if(($past(f_past_valid))&&($past(reset_i))) begin + assert(counter == 0); + assert(state == STATE_INIT_POWER); + assert(dc == 1); + assert(sclk == 1); + assert(sdin == 0); + assert(reset == 1); + assert(cs == 0); + assert(dataToSend == 0); + assert(bitNumber == 0); + assert(pixelCounter == 0); + end + end + + // + // Contract + // + always @(posedge clk_i) begin + if((f_past_valid)&&($past(f_past_valid))&&(!reset_i)&&(!$past(reset_i))) begin + case($past(state)) + STATE_INIT_POWER: begin + if(state == STATE_INIT_POWER) + assert(counter == ($past(counter)+1)); + // reset + if (counter <= STARTUP_WAIT) + assert(reset == 1); + else if (counter <= STARTUP_WAIT_2x) + assert(reset == 0); + else if (counter <= STARTUP_WAIT_3x) + assert(reset == 1); + end + STATE_LOAD_INIT_CMD: begin + assert(dc == 0); + assert(cs == 0); + assert(bitNumber == 3'd7); + assert(commandIndex == $past(commandIndex - 8'd8)); + assert(dataToSend == startupCommands[($past(commandIndex)-1)-:8'd8]); + end + STATE_SEND: begin + if ($past(counter) == 32'd0) begin + assert(sclk == 0); + assert(sdin == $past(dataToSend[bitNumber])); + assert(counter == 32'd1); + end else begin + assert(counter == 32'd0); + assert(sclk == 1); + if (bitNumber != 0) + assert(bitNumber == $past(bitNumber-1)); + end + end + STATE_CHECK_FINISHED_INIT: assert(cs == 1); + STATE_LOAD_DATA: begin + if(pixelCounter != 0) + assert(pixelCounter == $past(pixelCounter+1)); + assert(cs == 0); + assert(dc == 1); + assert(bitNumber == 3'd7); + assert(dataToSend == $past(pixelData_i)); + end + default: assert(0); // We should never ever be here + endcase + end + end - 8'h8D, // charge pump config - 8'h14, // enable charge pump - 8'hA4, // resume RAM content - 8'hAF // display on - }; - reg [7:0] commandIndex = SETUP_INSTRUCTIONS * 8; +`endif // FORMAL - assign ioSclk = sclk; - assign ioSdin = sdin; - assign ioDc = dc; - assign ioReset = reset; - assign ioCs = cs; - - assign pixelAddress = pixelCounter; - - always @(posedge clk) begin - case (state) - STATE_INIT_POWER: begin - counter <= counter + 1; - if (counter < STARTUP_WAIT*2) - reset <= 1; - else if (counter < STARTUP_WAIT * 3) - reset <= 0; - else if (counter < STARTUP_WAIT * 4) - reset <= 1; - else begin - state <= STATE_LOAD_INIT_CMD; - counter <= 32'b0; - end - end - STATE_LOAD_INIT_CMD: begin - dc <= 0; - dataToSend <= startupCommands[(commandIndex-1)-:8'd8]; - state <= STATE_SEND; - bitNumber <= 3'd7; - cs <= 0; - commandIndex <= commandIndex - 8'd8; - end - STATE_SEND: begin - if (counter == 32'd0) begin - sclk <= 0; - sdin <= dataToSend[bitNumber]; - counter <= 32'd1; - end - else begin - counter <= 32'd0; - sclk <= 1; - if (bitNumber == 0) - state <= STATE_CHECK_FINISHED_INIT; - else - bitNumber <= bitNumber - 1; - end - end - STATE_CHECK_FINISHED_INIT: begin - cs <= 1; - if (commandIndex == 0) begin - state <= STATE_LOAD_DATA; - end - else - state <= STATE_LOAD_INIT_CMD; - end - STATE_LOAD_DATA: begin - pixelCounter <= pixelCounter + 1; - cs <= 0; - dc <= 1; - bitNumber <= 3'd7; - state <= STATE_SEND; - dataToSend <= pixelData; - end - endcase - end -endmodule +endmodule \ No newline at end of file diff --git a/screen_data/screen_Data.gprj b/screen_data/screen_Data.gprj new file mode 100644 index 0000000..62668d0 --- /dev/null +++ b/screen_data/screen_Data.gprj @@ -0,0 +1,19 @@ + + + + + 5 + gw1nr9c-004 + + + + + + + + + + + + + diff --git a/screen_data/text.sby b/screen_data/text.sby new file mode 100644 index 0000000..2cf93f4 --- /dev/null +++ b/screen_data/text.sby @@ -0,0 +1,19 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DTEXT -formal text.v +read -formal screen.v +prep -top textEngine + +[files] +text.v +screen.v +font.hex diff --git a/screen_data/text.v b/screen_data/text.v index e5997c0..dac69f9 100644 --- a/screen_data/text.v +++ b/screen_data/text.v @@ -1,11 +1,62 @@ +`ifdef FORMAL `default_nettype none +`endif +module textRow #( + parameter ADDRESS_OFFSET = 8'd0 +) ( + input clk_i, + input [7:0] readAddress_i, + output [7:0] outByte_o +); + reg [7:0] textBuffer [15:0]; + + integer i; + + initial begin + for (i=0; i<15; i=i+1) begin + textBuffer[i] = 'd48 + ADDRESS_OFFSET + i; + end + end + + assign outByte_o = textBuffer[(readAddress_i-ADDRESS_OFFSET)]; + + // + // FORMAL VERIFICATION + // + `ifdef FORMAL + + `ifdef TEXT + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // Prove outByte_o is assigned correctly + always @(*) + if(f_past_valid) + assert(outByte_o == textBuffer[(readAddress_i-ADDRESS_OFFSET)]); + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // + // Contract + // + + `endif // FORMAL + +endmodule module textEngine ( - input clk, - input [9:0] pixelAddress, - output [7:0] pixelData, - output [5:0] charAddress, - input [7:0] charOutput + input clk_i, + input reset_i, + input [9:0] pixelAddress_i, + output [7:0] pixelData_o, + output [5:0] charAddress_o, + input [7:0] charOutput_i ); reg [7:0] fontBuffer [1519:0]; initial $readmemh("font.hex", fontBuffer); @@ -16,14 +67,65 @@ module textEngine ( reg [7:0] outputBuffer; wire [7:0] chosenChar; - always @(posedge clk) begin + always @(posedge clk_i) begin outputBuffer <= fontBuffer[((chosenChar-8'd32) << 4) + (columnAddress << 1) + (topRow ? 0 : 1)]; end - assign charAddress = {pixelAddress[9:8],pixelAddress[6:3]}; - assign columnAddress = pixelAddress[2:0]; - assign topRow = !pixelAddress[7]; + assign charAddress_o = {pixelAddress_i[9:8],pixelAddress_i[6:3]}; + assign columnAddress = pixelAddress_i[2:0]; + assign topRow = !pixelAddress_i[7]; + + assign chosenChar = (charOutput_i >= 32 && charOutput_i <= 126) ? charOutput_i : 32; + assign pixelData_o = outputBuffer; + + // + // FORMAL VERIFICATION + // + `ifdef FORMAL + + `ifdef TEXT + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that charAddress_o is assigned correctly + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(charAddress_o == {pixelAddress_i[9:8],pixelAddress_i[6:3]}); + + // Prove that topRow is assigned correctly + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(topRow == !pixelAddress_i[7]); + + // Prove that pixelData_o is assigned correctly + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(pixelData_o == outputBuffer); + + // Prove that columnAddress is assigned correctly + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(columnAddress == pixelAddress_i[2:0]); + + // + // Contract + // + always @(*) + if((f_past_valid)&&(!reset_i)) + if((charOutput_i >= 32) && (charOutput_i <= 126)) + assert(chosenChar == charOutput_i); + else + assert(chosenChar == 32); + + + `endif // FORMAL - assign chosenChar = (charOutput >= 32 && charOutput <= 126) ? charOutput : 32; - assign pixelData = outputBuffer; endmodule \ No newline at end of file diff --git a/screen_data/top.v b/screen_data/top.v index b08b2f7..8347e95 100644 --- a/screen_data/top.v +++ b/screen_data/top.v @@ -1,8 +1,10 @@ +`ifdef FORMAL `default_nettype none +`endif module counterM( input clk, - output reg [7:0] counterValue = 0, + output reg [7:0] counterValue = 0 ); reg [32:0] clockCounter = 0; @@ -43,8 +45,12 @@ module top wire [7:0] counterValue; + wire sys_reset; + assign sys_reset = 0; + screen #(STARTUP_WAIT) scr( - clk, + clk, + sys_reset, ioSclk, ioSdin, ioCs, @@ -56,6 +62,7 @@ module top textEngine te( clk, + sys_reset, pixelAddress, textPixelData, charAddress, @@ -66,6 +73,7 @@ module top uart u( clk, + sys_reset, uartRx, uartByteReady, uartDataIn @@ -97,6 +105,7 @@ module top progressRow row4( clk, + sys_reset, counterValue, pixelAddress, progressPixelData @@ -111,4 +120,4 @@ module top endcase end assign chosenPixelData = (rowNumber == 3) ? progressPixelData : textPixelData; -endmodule +endmodule \ No newline at end of file diff --git a/screen_data/uart.sby b/screen_data/uart.sby new file mode 100644 index 0000000..623c194 --- /dev/null +++ b/screen_data/uart.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 250 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DUART -formal uart.v +prep -top uart + +[files] +uart.v diff --git a/screen_data/uart.v b/screen_data/uart.v index 47b748b..74c1914 100644 --- a/screen_data/uart.v +++ b/screen_data/uart.v @@ -1,14 +1,17 @@ +`ifdef FORMAL `default_nettype none +`endif module uart #( parameter DELAY_FRAMES = 234 // 27,000,000 (27Mhz) / 115200 Baud rate ) ( - input clk, - input uartRx, - output reg byteReady, - output reg [7:0] dataIn + input clk_i, + input reset_i, + input uartRx_i, + output reg byteReady_o, + output reg [7:0] dataIn_o ); localparam HALF_DELAY_WAIT = (DELAY_FRAMES / 2); @@ -23,46 +26,130 @@ localparam RX_STATE_READ_WAIT = 2; localparam RX_STATE_READ = 3; localparam RX_STATE_STOP_BIT = 5; -always @(posedge clk) begin - case (rxState) - RX_STATE_IDLE: begin - if (uartRx == 0) begin - rxState <= RX_STATE_START_BIT; - rxCounter <= 1; - rxBitNumber <= 0; - byteReady <= 0; +always @(posedge clk_i) begin + if(reset_i) begin + rxState <= RX_STATE_IDLE; + rxCounter <= 0; + rxBitNumber <= 0; + byteReady_o <= 0; + dataIn_o <= 6'b11_1111; + end else begin + case (rxState) + RX_STATE_IDLE: begin + if (uartRx_i == 0) begin + rxState <= RX_STATE_START_BIT; + rxCounter <= 1; + rxBitNumber <= 0; + byteReady_o <= 0; + end + end + RX_STATE_START_BIT: begin + if (rxCounter == HALF_DELAY_WAIT) begin + rxState <= RX_STATE_READ_WAIT; + rxCounter <= 1; + end else + rxCounter <= rxCounter + 1; + end + RX_STATE_READ_WAIT: begin + rxCounter <= rxCounter + 1; + if ((rxCounter + 1) == DELAY_FRAMES) begin + rxState <= RX_STATE_READ; + end end - end - RX_STATE_START_BIT: begin - if (rxCounter == HALF_DELAY_WAIT) begin - rxState <= RX_STATE_READ_WAIT; + RX_STATE_READ: begin rxCounter <= 1; - end else + dataIn_o <= {uartRx_i, dataIn_o[7:1]}; + rxBitNumber <= rxBitNumber + 1; + if (rxBitNumber == 3'b111) + rxState <= RX_STATE_STOP_BIT; + else + rxState <= RX_STATE_READ_WAIT; + end + RX_STATE_STOP_BIT: begin rxCounter <= rxCounter + 1; - end - RX_STATE_READ_WAIT: begin - rxCounter <= rxCounter + 1; - if ((rxCounter + 1) == DELAY_FRAMES) begin - rxState <= RX_STATE_READ; + if ((rxCounter + 1) == DELAY_FRAMES) begin + rxState <= RX_STATE_IDLE; + rxCounter <= 0; + byteReady_o <= 1; + end end + endcase + end +end + +// +// FORMAL VERIFICATION +// +`ifdef FORMAL + + `ifdef UART + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove rxState is always in a valid state + always @(*) + if(f_past_valid) + assert(rxState <= RX_STATE_STOP_BIT); + + // Prove rxCount is always in a valid state + always @(*) + if(f_past_valid) + assert(rxCounter <= DELAY_FRAMES); + + always@(posedge clk_i) + `ASSUME(uartRx_i == $past(uartRx_i)); + + // Prove that after a reset, registers get initialized + always @(posedge clk_i) begin + if(((f_past_valid)&&($past(f_past_valid)))&&($past(reset_i))) begin + assert(rxState == RX_STATE_IDLE); + assert(rxCounter == 0); + assert(rxBitNumber == 0); + assert(byteReady_o == 0); + assert(dataIn_o == 6'b11_1111); end - RX_STATE_READ: begin - rxCounter <= 1; - dataIn <= {uartRx, dataIn[7:1]}; - rxBitNumber <= rxBitNumber + 1; - if (rxBitNumber == 3'b111) - rxState <= RX_STATE_STOP_BIT; - else - rxState <= RX_STATE_READ_WAIT; - end - RX_STATE_STOP_BIT: begin - rxCounter <= rxCounter + 1; - if ((rxCounter + 1) == DELAY_FRAMES) begin - rxState <= RX_STATE_IDLE; - rxCounter <= 0; - byteReady <= 1; - end + end + + // + // Contract + // + always@(posedge clk_i) begin + if((f_past_valid)&&(!reset_i)) + case(rxState) + RX_STATE_IDLE: assert(rxCounter == 0); // No byte sent + RX_STATE_START_BIT: assert(rxCounter == ($past(rxCounter)+1)); + RX_STATE_READ_WAIT: begin + if(($past(rxState == RX_STATE_START_BIT))||($past(rxState == RX_STATE_READ))||($past(rxState == RX_STATE_STOP_BIT))) + assert(rxCounter == 1); + else + assert(rxCounter == ($past(rxCounter)+1)); + end + RX_STATE_READ: assert(rxCounter == DELAY_FRAMES); + RX_STATE_STOP_BIT: begin + if(($past(rxState == RX_STATE_READ))) + assert(rxCounter == 1); + else + assert(rxCounter == ($past(rxCounter)+1)); + end + endcase + end + + always @(posedge clk_i) + if((f_past_valid)&&(!reset_i)&&($past(rxState) == RX_STATE_READ)&&(rxState == (RX_STATE_READ_WAIT || RX_STATE_STOP_BIT))) begin + assert(rxBitNumber == ($past(rxBitNumber)+1)); + assert(dataIn_o == {uartRx_i, dataIn_o[7:1]}); end - endcase -end + + +`endif // FORMAL + + endmodule \ No newline at end of file diff --git a/screen_data/uartTextRow.sby b/screen_data/uartTextRow.sby new file mode 100644 index 0000000..bc4f4f1 --- /dev/null +++ b/screen_data/uartTextRow.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DUART_TEXT_ROW -formal rows.v +prep -top uartTextRow + +[files] +rows.v diff --git a/screen_text/.gitignore b/screen_text/.gitignore new file mode 100644 index 0000000..66dfc51 --- /dev/null +++ b/screen_text/.gitignore @@ -0,0 +1,5 @@ +*.gprj.user +*.user +impl/ +screen/ +text/ \ No newline at end of file diff --git a/screen_text/screen.sby b/screen_text/screen.sby new file mode 100644 index 0000000..8f587db --- /dev/null +++ b/screen_text/screen.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DSCREEN -formal screen.v +prep -top screen + +[files] +screen.v diff --git a/screen_text/screen.v b/screen_text/screen.v index f1dba87..95f1d7a 100644 --- a/screen_text/screen.v +++ b/screen_text/screen.v @@ -1,143 +1,247 @@ -`default_nettype none - -module screen -#( - parameter STARTUP_WAIT = 32'd10000000 +module screen #( +`ifdef FORMAL + parameter STARTUP_WAIT = 32'd25 +`else + parameter STARTUP_WAIT = 32'd10000000 +`endif ) ( - input clk, - output ioSclk, - output ioSdin, - output ioCs, - output ioDc, - output ioReset, - output [9:0] pixelAddress, - input [7:0] pixelData + input clk_i, + input reset_i, + // OLED + output io_sclk_o, + output io_sdin_o, + output io_cs_o, + output io_dc_o, + output io_reset_o, + output [9:0] pixelAddress_i, + input [7:0] pixelData_i ); - localparam STATE_INIT_POWER = 8'd0; localparam STATE_LOAD_INIT_CMD = 8'd1; localparam STATE_SEND = 8'd2; localparam STATE_CHECK_FINISHED_INIT = 8'd3; localparam STATE_LOAD_DATA = 8'd4; - reg [32:0] counter = 0; - reg [2:0] state = 0; + localparam STARTUP_WAIT_2x = 2 * STARTUP_WAIT; + localparam STARTUP_WAIT_3x = 3 * STARTUP_WAIT; + localparam STARTUP_WAIT_MAX = STARTUP_WAIT_3x; + + localparam MAX_NUMBER_OF_PIXELS = 136; + reg [32:0] counter = 0; + reg [2:0] state = STATE_INIT_POWER; + reg dc = 1; reg sclk = 1; reg sdin = 0; reg reset = 1; reg cs = 0; - + reg [7:0] dataToSend = 0; reg [3:0] bitNumber = 0; reg [9:0] pixelCounter = 0; localparam SETUP_INSTRUCTIONS = 23; reg [(SETUP_INSTRUCTIONS*8)-1:0] startupCommands = { - 8'hAE, // display off - - 8'h81, // contast value to 0x7F according to datasheet - 8'h7F, - - 8'hA6, // normal screen mode (not inverted) - - 8'h20, // horizontal addressing mode - 8'h00, - - 8'hC8, // normal scan direction - - 8'h40, // first line to start scanning from - - 8'hA1, // address 0 is segment 0 - - 8'hA8, // mux ratio - 8'h3f, // 63 (64 -1) - - 8'hD3, // display offset - 8'h00, // no offset - - 8'hD5, // clock divide ratio - 8'h80, // set to default ratio/osc frequency + 8'hAE, // display off + 8'h81, // contast value to 0x7F according to datasheet + 8'h7F, + 8'hA6, // normal screen mode (not inverted) + 8'h20, // horizontal addressing mode + 8'h00, + 8'hC8, // normal scan direction + 8'h40, // first line to start scanning from + 8'hA1, // address 0 is segment 0 + 8'hA8, // mux ratio + 8'h3f, // 63 (64 -1) + 8'hD3, // display offset + 8'h00, // no offset + 8'hD5, // clock divide ratio + 8'h80, // set to default ratio/osc frequency + 8'hD9, // set precharge + 8'h22, // switch precharge to 0x22 default + 8'hDB, // vcom deselect level + 8'h20, // 0x20 + 8'h8D, // charge pump config + 8'h14, // enable charge pump + 8'hA4, // resume RAM content + 8'hAF // display on + }; + reg [7:0] commandIndex = SETUP_INSTRUCTIONS * 8; - 8'hD9, // set precharge - 8'h22, // switch precharge to 0x22 default + assign io_sclk_o = sclk; + assign io_sdin_o = sdin; + assign io_dc_o = dc; + assign io_reset_o = reset; + assign io_cs_o = cs; + + // State Machine + always @(posedge clk_i) begin + if(reset_i) begin + counter <= 0; + state <= STATE_INIT_POWER; + dc <= 1; + sclk <= 1; + sdin <= 0; + reset <= 1; + cs <= 0; + dataToSend <= 0; + bitNumber <= 0; + pixelCounter <= 0; + end else begin + case (state) + STATE_INIT_POWER: begin + counter <= counter + 1; + if (counter < STARTUP_WAIT) + reset <= 1; + else if (counter < STARTUP_WAIT_2x) + reset <= 0; + else if (counter < STARTUP_WAIT_3x) + reset <= 1; + else begin + state <= STATE_LOAD_INIT_CMD; + counter <= 32'b0; + end + end + STATE_LOAD_INIT_CMD: begin + dc <= 0; + dataToSend <= startupCommands[(commandIndex-1)-:8'd8]; + state <= STATE_SEND; + bitNumber <= 3'd7; + cs <= 0; + commandIndex <= commandIndex - 8'd8; + end + STATE_SEND: begin + if (counter == 32'd0) begin + sclk <= 0; + sdin <= dataToSend[bitNumber]; + counter <= 32'd1; + end else begin + counter <= 32'd0; + sclk <= 1; + if (bitNumber == 0) + state <= STATE_CHECK_FINISHED_INIT; + else + bitNumber <= bitNumber - 1; + end + end + STATE_CHECK_FINISHED_INIT: begin + cs <= 1; + if (commandIndex == 0) + state <= STATE_LOAD_DATA; + else + state <= STATE_LOAD_INIT_CMD; + end + STATE_LOAD_DATA: begin + pixelCounter <= pixelCounter + 1; + cs <= 0; + dc <= 1; + bitNumber <= 3'd7; + state <= STATE_SEND; + dataToSend <= pixelData_i; + end + endcase + end + end - 8'hDB, // vcom deselect level - 8'h20, // 0x20 + assign pixelAddress_i = pixelCounter; + +// +// FORMAL VERIFICATION +// +`ifdef FORMAL + + `ifdef SCREEN + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that state is always in a valid state + always@(*) + if((f_past_valid)&&(!reset_i)) + assert(state <= STATE_LOAD_DATA); + + // Prove that counter is always valid + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(counter <= STARTUP_WAIT_MAX); + + // Prove that after a reset registers get initialized + always @(posedge clk_i) begin + if(($past(f_past_valid))&&($past(reset_i))) begin + assert(counter == 0); + assert(state == STATE_INIT_POWER); + assert(dc == 1); + assert(sclk == 1); + assert(sdin == 0); + assert(reset == 1); + assert(cs == 0); + assert(dataToSend == 0); + assert(bitNumber == 0); + assert(pixelCounter == 0); + end + end + + // + // Contract + // + always @(posedge clk_i) begin + if((f_past_valid)&&($past(f_past_valid))&&(!reset_i)&&(!$past(reset_i))) begin + case($past(state)) + STATE_INIT_POWER: begin + if(state == STATE_INIT_POWER) + assert(counter == ($past(counter)+1)); + // reset + if (counter <= STARTUP_WAIT) + assert(reset == 1); + else if (counter <= STARTUP_WAIT_2x) + assert(reset == 0); + else if (counter <= STARTUP_WAIT_3x) + assert(reset == 1); + end + STATE_LOAD_INIT_CMD: begin + assert(dc == 0); + assert(cs == 0); + assert(bitNumber == 3'd7); + assert(commandIndex == $past(commandIndex - 8'd8)); + assert(dataToSend == startupCommands[($past(commandIndex)-1)-:8'd8]); + end + STATE_SEND: begin + if ($past(counter) == 32'd0) begin + assert(sclk == 0); + assert(sdin == $past(dataToSend[bitNumber])); + assert(counter == 32'd1); + end else begin + assert(counter == 32'd0); + assert(sclk == 1); + if (bitNumber != 0) + assert(bitNumber == $past(bitNumber-1)); + end + end + STATE_CHECK_FINISHED_INIT: assert(cs == 1); + STATE_LOAD_DATA: begin + if(pixelCounter != 0) + assert(pixelCounter == $past(pixelCounter+1)); + assert(cs == 0); + assert(dc == 1); + assert(bitNumber == 3'd7); + assert(dataToSend == $past(pixelData_i)); + end + default: assert(0); // We should never ever be here + endcase + end + end - 8'h8D, // charge pump config - 8'h14, // enable charge pump - 8'hA4, // resume RAM content - 8'hAF // display on - }; - reg [7:0] commandIndex = SETUP_INSTRUCTIONS * 8; +`endif // FORMAL - assign ioSclk = sclk; - assign ioSdin = sdin; - assign ioDc = dc; - assign ioReset = reset; - assign ioCs = cs; - - assign pixelAddress = pixelCounter; - - always @(posedge clk) begin - case (state) - STATE_INIT_POWER: begin - counter <= counter + 1; - if (counter < STARTUP_WAIT*2) - reset <= 1; - else if (counter < STARTUP_WAIT * 3) - reset <= 0; - else if (counter < STARTUP_WAIT * 4) - reset <= 1; - else begin - state <= STATE_LOAD_INIT_CMD; - counter <= 32'b0; - end - end - STATE_LOAD_INIT_CMD: begin - dc <= 0; - dataToSend <= startupCommands[(commandIndex-1)-:8'd8]; - state <= STATE_SEND; - bitNumber <= 3'd7; - cs <= 0; - commandIndex <= commandIndex - 8'd8; - end - STATE_SEND: begin - if (counter == 32'd0) begin - sclk <= 0; - sdin <= dataToSend[bitNumber]; - counter <= 32'd1; - end - else begin - counter <= 32'd0; - sclk <= 1; - if (bitNumber == 0) - state <= STATE_CHECK_FINISHED_INIT; - else - bitNumber <= bitNumber - 1; - end - end - STATE_CHECK_FINISHED_INIT: begin - cs <= 1; - if (commandIndex == 0) begin - state <= STATE_LOAD_DATA; - end - else - state <= STATE_LOAD_INIT_CMD; - end - STATE_LOAD_DATA: begin - pixelCounter <= pixelCounter + 1; - cs <= 0; - dc <= 1; - bitNumber <= 3'd7; - state <= STATE_SEND; - dataToSend <= pixelData; - end - endcase - end -endmodule +endmodule \ No newline at end of file diff --git a/screen_text/text.gprj b/screen_text/text.gprj new file mode 100644 index 0000000..1a47f19 --- /dev/null +++ b/screen_text/text.gprj @@ -0,0 +1,13 @@ + + + + + 5 + gw1nr9c-004 + + + + + + + diff --git a/screen_text/text.sby b/screen_text/text.sby new file mode 100644 index 0000000..2cf93f4 --- /dev/null +++ b/screen_text/text.sby @@ -0,0 +1,19 @@ +[options] +mode prove +depth 25 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DTEXT -formal text.v +read -formal screen.v +prep -top textEngine + +[files] +text.v +screen.v +font.hex diff --git a/screen_text/text.v b/screen_text/text.v index ae579f8..ed047fa 100644 --- a/screen_text/text.v +++ b/screen_text/text.v @@ -1,84 +1,171 @@ -`default_nettype none - module textRow #( parameter ADDRESS_OFFSET = 8'd0 ) ( - input clk, - input [7:0] readAddress, - output [7:0] outByte + input clk_i, + input [7:0] readAddress_i, + output [7:0] outByte_o ); reg [7:0] textBuffer [15:0]; + integer i; + initial begin for (i=0; i<15; i=i+1) begin - textBuffer[i] = 0; + textBuffer[i] = 'd48 + ADDRESS_OFFSET + i; end - textBuffer[0] = "L"; - textBuffer[1] = "u"; - textBuffer[2] = "s"; - textBuffer[3] = "h"; - textBuffer[4] = "a"; - textBuffer[5] = "y"; - textBuffer[6] = " "; - textBuffer[7] = "L"; - textBuffer[8] = "a"; - textBuffer[9] = "b"; - textBuffer[10] = "s"; - textBuffer[11] = "!"; end - assign outByte = textBuffer[(readAddress-ADDRESS_OFFSET)]; + assign outByte_o = textBuffer[(readAddress_i-ADDRESS_OFFSET)]; + +// +// FORMAL VERIFICATION +// +`ifdef FORMAL + + `ifdef TEXT + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // Prove outByte_o is assigned correctly + always @(*) + if(f_past_valid) + assert(outByte_o == textBuffer[(readAddress_i-ADDRESS_OFFSET)]); + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // + // Contract + // + +`endif // FORMAL + endmodule module textEngine ( - input clk, + input clk_i, + input reset_i, input [9:0] pixelAddress, output [7:0] pixelData ); reg [7:0] fontBuffer [1519:0]; initial $readmemh("font.hex", fontBuffer); - wire [5:0] charAddress; - wire [2:0] columnAddress; - wire topRow; + // Next we know how to split up the address from a pixel index to the desired character index column and whether or not we are on the top row: + wire [5:0] charAddress; + wire [2:0] columnAddress; + wire topRow; reg [7:0] outputBuffer; + // We also need a buffer to store the output byte. Connecting these up is simple now that we understand the mapping: + // The column address is the last 3 bits, the character address is made up of a lower 16 counter and the higher 4 counter for the rows. For the flag which indicates whether we are on the top row or bottom row we can just take a look at bit number 8 where it will be 0 if we are on the top row and 1 if it is the second iteration and we are on the bottom, so we invert it to match the flag name. Last but not least we hookup the outputBuffer to the pixelData output wires. + assign charAddress = {pixelAddress[9:8],pixelAddress[6:3]}; + assign columnAddress = pixelAddress[2:0]; + assign topRow = !pixelAddress[7]; + + assign pixelData = outputBuffer; + // To get started we can create some more wires to store the current char and the current char we want to display. wire [7:0] charOutput, chosenChar; + + // We have two variables for this because our font memory only has values for the character codes 32-126 other character codes would give an undefined behavior. So charOutput will be the actual character we want to output, and chosenChar will check if it is in range and if not replace the character with a space (character code 32) so it will simply be blank: + // If we look back at how we stored our font data, we stored the first column top byte then the first column second byte then the next column top byte and so on. + assign chosenChar = (charOutput >= 32 && charOutput <= 126) ? charOutput : 32; + // So if we want the letter "A" in memory, we know that its ascii code is 65 and our memory starts from ascii code 32 subtracting them gives us the number of characters from the start of memory we need to skip which in this case is 33. We need to multiply this number by 16 as each character is 16 bytes long giving us 528 bytes. Next if we wanted column index 3 we know each column is 2 bytes so we would need to skip another 6 bytes. Lastly once at the column boundary we know the first byte is for the top row and the second byte is for the bottom row of the character, so depending on which we need we optionally skip another byte. + // We take the character we want to display, subtract 32 to get the offset from start of memory. Multiply by 16 (by shifting left 4 times) to get the start of the character. Add to this the column address multiplied by 2 (again by shifting left by 1) and optionally adding another 1 if we are on the bottom row. + // This can be used to access the exact byte from the font memory needed: + always @(posedge clk_i) begin + // With this one line we are mapping the desired character to the exact pixels for the specific column and row. + outputBuffer <= fontBuffer[((chosenChar-8'd32) << 4) + (columnAddress << 1) + (topRow ? 0 : 1)]; + end + + // // The only thing missing is to know which character to output, but for now if we just add: + // assign charOutput = "A"; + + // + // + // wire [7:0] charOutput1, charOutput2, charOutput3, charOutput4; textRow #(6'd0) t1( - clk, + clk_i, charAddress, charOutput1 ); textRow #(6'd16) t2( - clk, + clk_i, charAddress, charOutput2 ); textRow #(6'd32) t3( - clk, + clk_i, charAddress, charOutput3 ); textRow #(6'd48) t4( - clk, + clk_i, charAddress, charOutput4 ); - always @(posedge clk) begin - outputBuffer <= fontBuffer[((chosenChar-8'd32) << 4) + (columnAddress << 1) + (topRow ? 0 : 1)]; - end + assign charOutput = (charAddress[5] && charAddress[4]) ? charOutput4 : ((charAddress[5]) ? charOutput3 : ((charAddress[4]) ? charOutput2 : charOutput1)); - assign charAddress = {pixelAddress[9:8],pixelAddress[6:3]}; - assign columnAddress = pixelAddress[2:0]; - assign topRow = !pixelAddress[7]; - assign charOutput = (charAddress[5] && charAddress[4]) ? charOutput4 : ((charAddress[5]) ? charOutput3 : ((charAddress[4]) ? charOutput2 : charOutput1)); - assign chosenChar = (charOutput >= 32 && charOutput <= 126) ? charOutput : 32; - assign pixelData = outputBuffer; +// +// FORMAL VERIFICATION +// +`ifdef FORMAL + + `ifdef TEXT + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove that charAddress is assigned correctly + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(charAddress == {pixelAddress[9:8],pixelAddress[6:3]}); + + // Prove that columnAddress is assigned correctly + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(columnAddress == pixelAddress[2:0]); + + // Prove that topRow is assigned correctly + always @(*) + if((f_past_valid)&&(!reset_i)) + assert(topRow == !pixelAddress[7]); + + + // + // Contract + // + always @(*) + if((f_past_valid)&&(!reset_i)) + if((charAddress[5])&&(charAddress[4])) + assert(charOutput == charOutput4); + else if(charAddress[5]) + assert(charOutput == charOutput3); + else if(charAddress[4]) + assert(charOutput == charOutput2); + else + assert(charOutput == charOutput1); + + +`endif // FORMAL + endmodule \ No newline at end of file diff --git a/uart/.gitignore b/uart/.gitignore new file mode 100644 index 0000000..57d29c3 --- /dev/null +++ b/uart/.gitignore @@ -0,0 +1,2 @@ +uart/ + diff --git a/uart/run_formal_verification.sh b/uart/run_formal_verification.sh new file mode 100644 index 0000000..b163b92 --- /dev/null +++ b/uart/run_formal_verification.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +# Run SymbiYosis +sby -f uart.sby \ No newline at end of file diff --git a/uart/uart.sby b/uart/uart.sby new file mode 100644 index 0000000..623c194 --- /dev/null +++ b/uart/uart.sby @@ -0,0 +1,16 @@ +[options] +mode prove +depth 250 + +[engines] +smtbmc +# abc pdr +# aiger avy +# aiger suprove + +[script] +read_verilog -DUART -formal uart.v +prep -top uart + +[files] +uart.v diff --git a/uart/uart.v b/uart/uart.v index f4df061..e8352a4 100644 --- a/uart/uart.v +++ b/uart/uart.v @@ -1,24 +1,21 @@ +`ifdef FORMAL `default_nettype none +`endif module uart #( - parameter DELAY_FRAMES = 234 // 27,000,000 (27Mhz) / 115200 Baud rate + parameter DELAY_FRAMES = 234 // 27,000,000 (27Mhz) / 115_200 Baud rate ) ( - input clk, - input uart_rx, - output uart_tx, - output reg [5:0] led, + input clk_i, + input reset_i, + input uart_rx_i, + output uart_tx_o, + output reg [5:0] led_o, input btn1 ); -localparam HALF_DELAY_WAIT = (DELAY_FRAMES / 2); - -reg [3:0] rxState = 0; -reg [12:0] rxCounter = 0; -reg [7:0] dataIn = 0; -reg [2:0] rxBitNumber = 0; -reg byteReady = 0; +localparam HALF_DELAY_WAIT = (DELAY_FRAMES/ 2); localparam RX_STATE_IDLE = 0; localparam RX_STATE_START_BIT = 1; @@ -26,143 +23,150 @@ localparam RX_STATE_READ_WAIT = 2; localparam RX_STATE_READ = 3; localparam RX_STATE_STOP_BIT = 5; -always @(posedge clk) begin - case (rxState) - RX_STATE_IDLE: begin - if (uart_rx == 0) begin - rxState <= RX_STATE_START_BIT; - rxCounter <= 1; - rxBitNumber <= 0; - byteReady <= 0; +reg [3:0] rxState; +reg [12:0] rxCounter; +reg [2:0] rxBitNumber; +reg [7:0] dataIn; +reg byteReady; + +initial rxState = RX_STATE_IDLE; +initial rxCounter = 0; +initial rxBitNumber = 0; +initial dataIn = 6'b11_1111; +initial byteReady = 0; + +always @(posedge clk_i) begin + if(reset_i) begin + rxState <= RX_STATE_IDLE; + rxCounter <= 0; + rxBitNumber <= 0; + byteReady <= 0; + dataIn <= 6'b11_1111; + end else begin + case (rxState) + RX_STATE_IDLE: begin + if (uart_rx_i == 0) begin + rxState <= RX_STATE_START_BIT; + rxCounter <= 1; + rxBitNumber <= 0; + byteReady <= 0; + end + end + RX_STATE_START_BIT: begin + if (rxCounter == HALF_DELAY_WAIT) begin + rxState <= RX_STATE_READ_WAIT; + rxCounter <= 1; + end else + rxCounter <= rxCounter + 1; end - end - RX_STATE_START_BIT: begin - if (rxCounter == HALF_DELAY_WAIT) begin - rxState <= RX_STATE_READ_WAIT; - rxCounter <= 1; - end else + RX_STATE_READ_WAIT: begin rxCounter <= rxCounter + 1; - end - RX_STATE_READ_WAIT: begin - rxCounter <= rxCounter + 1; - if ((rxCounter + 1) == DELAY_FRAMES) begin - rxState <= RX_STATE_READ; + if ((rxCounter + 1) == DELAY_FRAMES) begin + rxState <= RX_STATE_READ; + end end - end - RX_STATE_READ: begin - rxCounter <= 1; - dataIn <= {uart_rx, dataIn[7:1]}; - rxBitNumber <= rxBitNumber + 1; - if (rxBitNumber == 3'b111) - rxState <= RX_STATE_STOP_BIT; - else - rxState <= RX_STATE_READ_WAIT; - end - RX_STATE_STOP_BIT: begin - rxCounter <= rxCounter + 1; - if ((rxCounter + 1) == DELAY_FRAMES) begin - rxState <= RX_STATE_IDLE; - rxCounter <= 0; - byteReady <= 1; + RX_STATE_READ: begin + rxCounter <= 1; + dataIn <= {uart_rx_i, dataIn[7:1]}; + rxBitNumber <= rxBitNumber + 1; + if (rxBitNumber == 3'b111) + rxState <= RX_STATE_STOP_BIT; + else + rxState <= RX_STATE_READ_WAIT; end - end - endcase -end - -always @(posedge clk) begin - if (byteReady) begin - led <= ~dataIn[5:0]; + RX_STATE_STOP_BIT: begin + rxCounter <= rxCounter + 1; + if ((rxCounter + 1) == DELAY_FRAMES) begin + rxState <= RX_STATE_IDLE; + rxCounter <= 0; + byteReady <= 1; + end + end + endcase end end -reg [3:0] txState = 0; -reg [24:0] txCounter = 0; -reg [7:0] dataOut = 0; -reg txPinRegister = 1; -reg [2:0] txBitNumber = 0; -reg [3:0] txByteCounter = 0; - -assign uart_tx = txPinRegister; - -localparam MEMORY_LENGTH = 12; -reg [7:0] testMemory [MEMORY_LENGTH-1:0]; - -initial begin - testMemory[0] = "L"; - testMemory[1] = "u"; - testMemory[2] = "s"; - testMemory[3] = "h"; - testMemory[4] = "a"; - testMemory[5] = "y"; - testMemory[6] = " "; - testMemory[7] = "L"; - testMemory[8] = "a"; - testMemory[9] = "b"; - testMemory[10] = "s"; - testMemory[11] = " "; +always @(posedge clk_i) begin + if(reset_i) + led_o <= 6'b11_1111; + else + if (byteReady) + led_o <= ~dataIn[5:0]; end -localparam TX_STATE_IDLE = 0; -localparam TX_STATE_START_BIT = 1; -localparam TX_STATE_WRITE = 2; -localparam TX_STATE_STOP_BIT = 3; -localparam TX_STATE_DEBOUNCE = 4; - -always @(posedge clk) begin - case (txState) - TX_STATE_IDLE: begin - if (btn1 == 0) begin - txState <= TX_STATE_START_BIT; - txCounter <= 0; - txByteCounter <= 0; - end - else begin - txPinRegister <= 1; - end - end - TX_STATE_START_BIT: begin - txPinRegister <= 0; - if ((txCounter + 1) == DELAY_FRAMES) begin - txState <= TX_STATE_WRITE; - dataOut <= testMemory[txByteCounter]; - txBitNumber <= 0; - txCounter <= 0; - end else - txCounter <= txCounter + 1; + +// +// FORMAL VERIFICATION +// +`ifdef FORMAL + + `ifdef UART + `define ASSUME assume + `else + `define ASSUME assert + `endif + + // f_past_valid + reg f_past_valid; + initial f_past_valid = 1'b0; + always @(posedge clk_i) + f_past_valid <= 1'b1; + + // Prove rxState is always in a valid state + always @(*) + if(f_past_valid) + assert(rxState <= RX_STATE_STOP_BIT); + + // Prove rxCount is always in a valid state + always @(*) + if(f_past_valid) + assert(rxCounter <= DELAY_FRAMES); + + always@(posedge clk_i) + `ASSUME(uart_rx_i == $past(uart_rx_i)); + + // Prove that after a reset, registers get initialized + always @(posedge clk_i) begin + if(($past(f_past_valid))&&($past(reset_i))) begin + assert(rxState == RX_STATE_IDLE); + assert(rxCounter == 0); + assert(rxBitNumber == 0); + assert(byteReady == 0); + assert(dataIn == 6'b11_1111); end - TX_STATE_WRITE: begin - txPinRegister <= dataOut[txBitNumber]; - if ((txCounter + 1) == DELAY_FRAMES) begin - if (txBitNumber == 3'b111) begin - txState <= TX_STATE_STOP_BIT; - end else begin - txState <= TX_STATE_WRITE; - txBitNumber <= txBitNumber + 1; + end + + // + // Contract + // + always@(posedge clk_i) begin + if((f_past_valid)&&(!reset_i)) + case(rxState) + RX_STATE_IDLE: assert(rxCounter == 0); // No byte sent + RX_STATE_START_BIT: assert(rxCounter == ($past(rxCounter)+1)); + RX_STATE_READ_WAIT: begin + if(($past(rxState == RX_STATE_START_BIT))||($past(rxState == RX_STATE_READ))||($past(rxState == RX_STATE_STOP_BIT))) + assert(rxCounter == 1); + else + assert(rxCounter == ($past(rxCounter)+1)); end - txCounter <= 0; - end else - txCounter <= txCounter + 1; - end - TX_STATE_STOP_BIT: begin - txPinRegister <= 1; - if ((txCounter + 1) == DELAY_FRAMES) begin - if (txByteCounter == MEMORY_LENGTH - 1) begin - txState <= TX_STATE_DEBOUNCE; - end else begin - txByteCounter <= txByteCounter + 1; - txState <= TX_STATE_START_BIT; + RX_STATE_READ: assert(rxCounter == DELAY_FRAMES); + RX_STATE_STOP_BIT: begin + if(($past(rxState == RX_STATE_READ))) + assert(rxCounter == 1); + else + assert(rxCounter == ($past(rxCounter)+1)); end - txCounter <= 0; - end else - txCounter <= txCounter + 1; - end - TX_STATE_DEBOUNCE: begin - if (txCounter == 23'b111111111111111111) begin - if (btn1 == 1) - txState <= TX_STATE_IDLE; - end else - txCounter <= txCounter + 1; + endcase + end + + always @(posedge clk_i) + if((f_past_valid)&&(!reset_i)&&($past(rxState) == RX_STATE_READ)&&(rxState == (RX_STATE_READ_WAIT || RX_STATE_STOP_BIT))) begin + assert(rxBitNumber == ($past(rxBitNumber)+1)); + assert(dataIn == {uart_rx_i, dataIn[7:1]}); end - endcase -end -endmodule \ No newline at end of file + + +`endif // FORMAL + +endmodule \ No newline at end of file