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vsyrjalalutzbichler
vsyrjala
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lutzbichler
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drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bits
Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc. style. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎drivers/gpu/drm/i915/gt/intel_engine_cs.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -771,9 +771,8 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt)
771771
if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))
772772
media_fuse = ~media_fuse;
773773

774-
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
775-
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
776-
GEN11_GT_VEBOX_DISABLE_SHIFT;
774+
vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse);
775+
vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse);
777776

778777
if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {
779778
fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);

‎drivers/gpu/drm/i915/gt/intel_gt_mcr.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -121,9 +121,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
121121
gt->info.mslice_mask =
122122
intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
123123
GEN_DSS_PER_MSLICE);
124-
gt->info.mslice_mask |=
125-
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
126-
GEN12_MEML3_EN_MASK);
124+
gt->info.mslice_mask |= REG_FIELD_GET(GEN12_MEML3_EN_MASK,
125+
intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3));
127126

128127
if (!gt->info.mslice_mask) /* should be impossible! */
129128
gt_warn(gt, "mslice mask all zero!\n");

‎drivers/gpu/drm/i915/gt/intel_gt_regs.h‎

Lines changed: 27 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -517,24 +517,24 @@
517517
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
518518
#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
519519
((slice) % 3) * 0x4)
520-
#define GEN9_PGCTL_SLICE_ACK (1 << 0)
521-
#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
522-
#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
520+
#define GEN9_PGCTL_SLICE_ACK REG_BIT(0)
521+
#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2)
522+
#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0))
523523

524524
#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
525525
#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
526526
((slice) % 3) * 0x8)
527527
#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
528528
#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
529529
((slice) % 3) * 0x8)
530-
#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
531-
#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
532-
#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
533-
#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
534-
#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
535-
#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
536-
#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
537-
#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
530+
#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0)
531+
#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2)
532+
#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4)
533+
#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6)
534+
#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8)
535+
#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10)
536+
#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12)
537+
#define GEN9_PGCTL_SSB_EU311_ACK REG_BIT(14)
538538

539539
#define VF_PREEMPTION _MMIO(0x83a4)
540540
#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
@@ -591,7 +591,7 @@
591591
#define GEN10_L3BANK_MASK 0x0F
592592
/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
593593
#define GEN12_MAX_MSLICES 4
594-
#define GEN12_MEML3_EN_MASK 0x0F
594+
#define GEN12_MEML3_EN_MASK REG_GENMASK(3, 0)
595595

596596
#define HSW_PAVP_FUSE1 _MMIO(0x911c)
597597
#define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
@@ -601,47 +601,39 @@
601601
#define HSW_F1_EU_DIS_6EUS 2
602602

603603
#define GEN8_FUSE2 _MMIO(0x9120)
604-
#define GEN8_F2_SS_DIS_SHIFT 21
605-
#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
606-
#define GEN8_F2_S_ENA_SHIFT 25
607-
#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
608-
#define GEN9_F2_SS_DIS_SHIFT 20
609-
#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
610-
#define GEN10_F2_S_ENA_SHIFT 22
611-
#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
612-
#define GEN10_F2_SS_DIS_SHIFT 18
613-
#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
604+
#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21)
605+
#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25)
606+
#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20)
607+
#define GEN10_F2_S_ENA_MASK REG_GENMASK(27, 22)
608+
#define GEN10_F2_SS_DIS_MASK REG_GENMASK(21, 18)
614609

615610
#define GEN8_EU_DISABLE0 _MMIO(0x9134)
616611
#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
617612
#define GEN11_EU_DISABLE _MMIO(0x9134)
618-
#define GEN8_EU_DIS0_S0_MASK 0xffffff
619-
#define GEN8_EU_DIS0_S1_SHIFT 24
620-
#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
621-
#define GEN11_EU_DIS_MASK 0xFF
613+
#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0)
614+
#define GEN8_EU_DIS0_S1_MASK REG_GENMASK(31, 24)
615+
#define GEN11_EU_DIS_MASK REG_GENMASK(7, 0)
622616
#define XEHP_EU_ENABLE _MMIO(0x9134)
623-
#define XEHP_EU_ENA_MASK 0xFF
617+
#define XEHP_EU_ENA_MASK REG_GENMASK(7, 0)
624618

625619
#define GEN8_EU_DISABLE1 _MMIO(0x9138)
626-
#define GEN8_EU_DIS1_S1_MASK 0xffff
627-
#define GEN8_EU_DIS1_S2_SHIFT 16
628-
#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
620+
#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0)
621+
#define GEN8_EU_DIS1_S2_MASK REG_GENMASK(31, 16)
629622

630623
#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
631-
#define GEN11_GT_S_ENA_MASK 0xFF
624+
#define GEN11_GT_S_ENA_MASK REG_GENMASK(7, 0)
632625

633626
#define GEN8_EU_DISABLE2 _MMIO(0x913c)
634-
#define GEN8_EU_DIS2_S2_MASK 0xff
627+
#define GEN8_EU_DIS2_S2_MASK REG_GENMASK(7, 0)
635628

636629
#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c)
637630
#define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c)
638631

639632
#define GEN10_EU_DISABLE3 _MMIO(0x9140)
640633
#define GEN10_EU_DIS_SS_MASK 0xff
641634
#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
642-
#define GEN11_GT_VDBOX_DISABLE_MASK 0xff
643-
#define GEN11_GT_VEBOX_DISABLE_SHIFT 16
644-
#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
635+
#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0)
636+
#define GEN11_GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16)
645637

646638
#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
647639
#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)

‎drivers/gpu/drm/i915/gt/intel_sseu.c‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,8 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
239239
GEN12_GT_COMPUTE_DSS_ENABLE,
240240
XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
241241

242-
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
242+
eu_en_fuse = REG_FIELD_GET(XEHP_EU_ENA_MASK,
243+
intel_uncore_read(uncore, XEHP_EU_ENABLE));
243244

244245
if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))
245246
eu_en = eu_en_fuse;
@@ -272,15 +273,15 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
272273
* Although gen12 architecture supported multiple slices, TGL, RKL,
273274
* DG1, and ADL only had a single slice.
274275
*/
275-
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
276-
GEN11_GT_S_ENA_MASK;
276+
s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,
277+
intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE));
277278
drm_WARN_ON(&gt->i915->drm, s_en != 0x1);
278279

279280
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
280281

281282
/* one bit per pair of EUs */
282-
eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
283-
GEN11_EU_DIS_MASK);
283+
eu_en_fuse = ~REG_FIELD_GET(GEN11_EU_DIS_MASK,
284+
intel_uncore_read(uncore, GEN11_EU_DISABLE));
284285

285286
for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
286287
if (eu_en_fuse & BIT(eu))
@@ -309,14 +310,14 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
309310
* Although gen11 architecture supported multiple slices, ICL and
310311
* EHL/JSL only had a single slice in practice.
311312
*/
312-
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
313-
GEN11_GT_S_ENA_MASK;
313+
s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK,
314+
intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE));
314315
drm_WARN_ON(&gt->i915->drm, s_en != 0x1);
315316

316317
ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
317318

318-
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
319-
GEN11_EU_DIS_MASK);
319+
eu_en = ~REG_FIELD_GET(GEN11_EU_DIS_MASK,
320+
intel_uncore_read(uncore, GEN11_EU_DISABLE));
320321

321322
gen11_compute_sseu_info(sseu, ss_en, eu_en);
322323

@@ -384,7 +385,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
384385
int s, ss;
385386

386387
fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
387-
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
388+
sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);
388389

389390
/* BXT has a single slice and at most 3 subslices. */
390391
intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3,
@@ -395,8 +396,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
395396
* to each of the enabled slices.
396397
*/
397398
subslice_mask = (1 << sseu->max_subslices) - 1;
398-
subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
399-
GEN9_F2_SS_DIS_SHIFT);
399+
subslice_mask &= ~REG_FIELD_GET(GEN9_F2_SS_DIS_MASK, fuse2);
400400

401401
/*
402402
* Iterate through enabled slices and subslices to
@@ -489,26 +489,26 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
489489
u32 eu_disable0, eu_disable1, eu_disable2;
490490

491491
fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
492-
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
492+
sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2);
493493
intel_sseu_set_info(sseu, 3, 3, 8);
494494

495495
/*
496496
* The subslice disable field is global, i.e. it applies
497497
* to each of the enabled slices.
498498
*/
499499
subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
500-
subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
501-
GEN8_F2_SS_DIS_SHIFT);
500+
subslice_mask &= ~REG_FIELD_GET(GEN8_F2_SS_DIS_MASK, fuse2);
502501
eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0);
503502
eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1);
504503
eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2);
505-
eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK;
506-
eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) |
507-
((eu_disable1 & GEN8_EU_DIS1_S1_MASK) <<
508-
(32 - GEN8_EU_DIS0_S1_SHIFT));
509-
eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) |
510-
((eu_disable2 & GEN8_EU_DIS2_S2_MASK) <<
511-
(32 - GEN8_EU_DIS1_S2_SHIFT));
504+
eu_disable[0] =
505+
REG_FIELD_GET(GEN8_EU_DIS0_S0_MASK, eu_disable0);
506+
eu_disable[1] =
507+
REG_FIELD_GET(GEN8_EU_DIS0_S1_MASK, eu_disable0) |
508+
REG_FIELD_GET(GEN8_EU_DIS1_S1_MASK, eu_disable1) << hweight32(GEN8_EU_DIS0_S1_MASK);
509+
eu_disable[2] =
510+
REG_FIELD_GET(GEN8_EU_DIS1_S2_MASK, eu_disable1) |
511+
REG_FIELD_GET(GEN8_EU_DIS2_S2_MASK, eu_disable2) << hweight32(GEN8_EU_DIS1_S2_MASK);
512512

513513
/*
514514
* Iterate through enabled slices and subslices to

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