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target/riscv: move riscv_log_dmi_scan
Change-Id: Iade30374331e9bde31a411b82056d47207cc39a8 Signed-off-by: Evgeniy Naydanov <[email protected]>
1 parent 3bed4c8 commit 7f8c43a

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3 files changed

+78
-84
lines changed

3 files changed

+78
-84
lines changed

‎src/target/riscv/batch.c‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66

77
#include "batch.h"
88
#include "debug_defines.h"
9+
#include "debug_reg_printer.h"
910
#include "riscv.h"
1011
#include "field_helpers.h"
1112

@@ -142,6 +143,83 @@ static int get_delay(const struct riscv_batch *batch, size_t scan_idx,
142143
return delay;
143144
}
144145

146+
static unsigned int decode_dmi(const struct target *target, char *text, uint32_t address, uint32_t data)
147+
{
148+
static const struct {
149+
uint32_t address;
150+
enum riscv_debug_reg_ordinal ordinal;
151+
} description[] = {
152+
{DM_DMCONTROL, DM_DMCONTROL_ORDINAL},
153+
{DM_DMSTATUS, DM_DMSTATUS_ORDINAL},
154+
{DM_ABSTRACTCS, DM_ABSTRACTCS_ORDINAL},
155+
{DM_COMMAND, DM_COMMAND_ORDINAL},
156+
{DM_SBCS, DM_SBCS_ORDINAL}
157+
};
158+
159+
for (unsigned int i = 0; i < ARRAY_SIZE(description); i++) {
160+
if (riscv_get_dmi_address(target, description[i].address) == address) {
161+
const riscv_debug_reg_ctx_t context = {
162+
.XLEN = { .value = 0, .is_set = false },
163+
.DXLEN = { .value = 0, .is_set = false },
164+
.abits = { .value = 0, .is_set = false },
165+
};
166+
return riscv_debug_reg_to_s(text, description[i].ordinal,
167+
context, data, RISCV_DEBUG_REG_HIDE_ALL_0);
168+
}
169+
}
170+
if (text)
171+
text[0] = '\0';
172+
return 0;
173+
}
174+
175+
static void riscv_log_dmi_scan(const struct target *target, int idle,
176+
const struct scan_field *field)
177+
{
178+
static const char * const op_string[] = {"-", "r", "w", "?"};
179+
static const char * const status_string[] = {"+", "?", "F", "b"};
180+
181+
if (debug_level < LOG_LVL_DEBUG)
182+
return;
183+
184+
assert(field->out_value);
185+
const uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
186+
const unsigned int out_op = get_field(out, DTM_DMI_OP);
187+
const uint32_t out_data = get_field(out, DTM_DMI_DATA);
188+
const uint32_t out_address = out >> DTM_DMI_ADDRESS_OFFSET;
189+
190+
if (field->in_value) {
191+
const uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
192+
const unsigned int in_op = get_field(in, DTM_DMI_OP);
193+
const uint32_t in_data = get_field(in, DTM_DMI_DATA);
194+
const uint32_t in_address = in >> DTM_DMI_ADDRESS_OFFSET;
195+
196+
LOG_DEBUG("%db %s %08" PRIx32 " @%02" PRIx32 " -> %s %08" PRIx32 " @%02" PRIx32 "; %di",
197+
field->num_bits, op_string[out_op], out_data, out_address,
198+
status_string[in_op], in_data, in_address, idle);
199+
200+
if (in_op == DTM_DMI_OP_SUCCESS) {
201+
char in_decoded[decode_dmi(target, NULL, in_address, in_data) + 1];
202+
decode_dmi(target, in_decoded, in_address, in_data);
203+
/* FIXME: The current code assumes that the hardware
204+
* provides the read address in the dmi.address field
205+
* when returning the dmi.data. That is however not
206+
* required by the spec, and therefore not guaranteed.
207+
* See https://github.com/riscv-collab/riscv-openocd/issues/1043
208+
*/
209+
LOG_DEBUG("read: %s", in_decoded);
210+
}
211+
} else {
212+
LOG_DEBUG("%db %s %08" PRIx32 " @%02" PRIx32 " -> ?; %di",
213+
field->num_bits, op_string[out_op], out_data, out_address,
214+
idle);
215+
}
216+
if (out_op == DTM_DMI_OP_WRITE) {
217+
char out_decoded[decode_dmi(target, NULL, out_address, out_data) + 1];
218+
decode_dmi(target, out_decoded, out_address, out_data);
219+
LOG_DEBUG("write: %s", out_decoded);
220+
}
221+
}
222+
145223
int riscv_batch_run_from(struct riscv_batch *batch, size_t start_idx,
146224
const struct riscv_scan_delays *delays, bool resets_delays,
147225
size_t reset_delays_after)

‎src/target/riscv/batch.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -228,10 +228,4 @@ size_t riscv_batch_available_scans(struct riscv_batch *batch);
228228
/* Return true iff the last scan in the batch returned DMI_OP_BUSY. */
229229
bool riscv_batch_was_batch_busy(const struct riscv_batch *batch);
230230

231-
/* TODO: The function is defined in `riscv-013.c`. This is done to reduce the
232-
* diff of the commit. The intention is to move the function definition to
233-
* a separate module (e.g. `riscv013-jtag-dtm.c/h`) in another commit. */
234-
void riscv_log_dmi_scan(const struct target *target, int idle,
235-
const struct scan_field *field);
236-
237231
#endif /* OPENOCD_TARGET_RISCV_BATCH_H */

‎src/target/riscv/riscv-013.c‎

Lines changed: 0 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -349,84 +349,6 @@ static uint32_t set_dmcontrol_hartsel(uint32_t initial, int hart_index)
349349
return initial;
350350
}
351351

352-
static unsigned int decode_dmi(const struct target *target, char *text, uint32_t address, uint32_t data)
353-
{
354-
static const struct {
355-
uint32_t address;
356-
enum riscv_debug_reg_ordinal ordinal;
357-
} description[] = {
358-
{DM_DMCONTROL, DM_DMCONTROL_ORDINAL},
359-
{DM_DMSTATUS, DM_DMSTATUS_ORDINAL},
360-
{DM_ABSTRACTCS, DM_ABSTRACTCS_ORDINAL},
361-
{DM_COMMAND, DM_COMMAND_ORDINAL},
362-
{DM_SBCS, DM_SBCS_ORDINAL}
363-
};
364-
365-
for (unsigned i = 0; i < ARRAY_SIZE(description); i++) {
366-
if (riscv_get_dmi_address(target, description[i].address) == address) {
367-
const riscv_debug_reg_ctx_t context = {
368-
.XLEN = { .value = 0, .is_set = false },
369-
.DXLEN = { .value = 0, .is_set = false },
370-
.abits = { .value = 0, .is_set = false },
371-
};
372-
return riscv_debug_reg_to_s(text, description[i].ordinal,
373-
context, data, RISCV_DEBUG_REG_HIDE_ALL_0);
374-
}
375-
}
376-
if (text)
377-
text[0] = '\0';
378-
return 0;
379-
}
380-
381-
/* TODO: Move this function to "batch.c" and make it static. */
382-
void riscv_log_dmi_scan(const struct target *target, int idle,
383-
const struct scan_field *field)
384-
{
385-
static const char * const op_string[] = {"-", "r", "w", "?"};
386-
static const char * const status_string[] = {"+", "?", "F", "b"};
387-
388-
if (debug_level < LOG_LVL_DEBUG)
389-
return;
390-
391-
assert(field->out_value);
392-
const uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
393-
const unsigned int out_op = get_field(out, DTM_DMI_OP);
394-
const uint32_t out_data = get_field(out, DTM_DMI_DATA);
395-
const uint32_t out_address = out >> DTM_DMI_ADDRESS_OFFSET;
396-
397-
if (field->in_value) {
398-
const uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
399-
const unsigned int in_op = get_field(in, DTM_DMI_OP);
400-
const uint32_t in_data = get_field(in, DTM_DMI_DATA);
401-
const uint32_t in_address = in >> DTM_DMI_ADDRESS_OFFSET;
402-
403-
LOG_DEBUG("%db %s %08" PRIx32 " @%02" PRIx32 " -> %s %08" PRIx32 " @%02" PRIx32 "; %di",
404-
field->num_bits, op_string[out_op], out_data, out_address,
405-
status_string[in_op], in_data, in_address, idle);
406-
407-
if (in_op == DTM_DMI_OP_SUCCESS) {
408-
char in_decoded[decode_dmi(target, NULL, in_address, in_data) + 1];
409-
decode_dmi(target, in_decoded, in_address, in_data);
410-
/* FIXME: The current code assumes that the hardware
411-
* provides the read address in the dmi.address field
412-
* when returning the dmi.data. That is however not
413-
* required by the spec, and therefore not guaranteed.
414-
* See https://github.com/riscv-collab/riscv-openocd/issues/1043
415-
*/
416-
LOG_DEBUG("read: %s", in_decoded);
417-
}
418-
} else {
419-
LOG_DEBUG("%db %s %08" PRIx32 " @%02" PRIx32 " -> ?; %di",
420-
field->num_bits, op_string[out_op], out_data, out_address,
421-
idle);
422-
}
423-
if (out_op == DTM_DMI_OP_WRITE) {
424-
char out_decoded[decode_dmi(target, NULL, out_address, out_data) + 1];
425-
decode_dmi(target, out_decoded, out_address, out_data);
426-
LOG_DEBUG("write: %s", out_decoded);
427-
}
428-
}
429-
430352
/*** Utility functions. ***/
431353

432354
static void select_dmi(struct target *target)

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