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tcl/target: add Bouffalo Lab BL602 and BL702L chip series support
BL602, BL702 and BL702L series of chips are sharing same architecture, so they all need same software reset mechanism as well. Only difference (in terms of configuration needed for JTAG) are TAP ID, workarea address and size. This is addressed by creating bl602_common.cfg tcl file, which contains all those common stuff between the chips. The script is prefixed by bl602, as this was first *publicly* available chip from Bouffalo with this architecture. This patch also improves reset mechanism. Previous reset mechanism did not worked properly when slower JTAG adapter was used (it attached too late). New reset mechanism uses various methods to keep CPU in BootROM, until the JTAG adapter does not attach again after reset. Additionally, we trigger SW Reset by directly using DMI commands to write to register with system bus method, to avoid getting error about unsuccessful write. The new method works on both FT232H (8MHz JTAG clock) and unnamed CMSIS-DAP dongle (1.5MHz JTAG clock). Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae Signed-off-by: Marek Kraus <[email protected]> Reviewed-on: https://review.openocd.org/c/openocd/+/8593 Tested-by: jenkins Reviewed-by: Antonio Borneo <[email protected]>
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‎tcl/target/bl602.cfg‎

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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Bouffalo Labs BL602 and BL604 target
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#
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# https://en.bouffalolab.com/product/?type=detail&id=1
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#
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# Default JTAG pins: (if not changed by eFuse configuration)
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# TDO - GPIO11
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# TMS - GPIO12
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# TCK - GPIO14
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# TDI - GPIO17
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#
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if { [info exists CHIPNAME] } {
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set BL602_CHIPNAME $CHIPNAME
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} else {
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set BL602_CHIPNAME bl602
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}
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set CPUTAPID 0x20000c05
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# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP
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set WORKAREAADDR 0x42014000
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set WORKAREASIZE 0xC000
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source [find target/bl602_common.cfg]
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# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information
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$_TARGETNAME configure -event reset-assert {
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halt
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bl602_sw_reset_hbn_wait
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}

‎tcl/target/bl602_common.cfg‎

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# SPDX-License-Identifier: GPL-2.0-or-later
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# Script for Bouffalo chips with similar architecture used in BL602
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# based on SiFive E21 core
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source [find mem_helper.tcl]
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transport select jtag
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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error "you must specify a tap id"
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}
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if { [info exists BL602_CHIPNAME] } {
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set _CHIPNAME $BL602_CHIPNAME
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} else {
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error "you must specify a chip name"
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}
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if { [info exists WORKAREAADDR] } {
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set _WORKAREAADDR $WORKAREAADDR
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} else {
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error "you must specify a work area address"
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}
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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error "you must specify a work area size"
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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riscv set_mem_access sysbus
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riscv set_enable_virt2phys off
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$_TARGETNAME configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1
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# Internal RC ticks on 32 MHz, so this speed should be safe to use.
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adapter speed 8000
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# Useful functions
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set dmcontrol 0x10
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set dmcontrol_dmactive [expr {1 << 0}]
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set dmcontrol_ndmreset [expr {1 << 1}]
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set dmcontrol_resumereq [expr {1 << 30}]
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set dmcontrol_haltreq [expr {1 << 31}]
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proc bl602_restore_clock_defaults { } {
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# Switch clock to internal RC32M
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# In HBN_GLB, set ROOT_CLK_SEL = 0
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mmw 0x4000f030 0x0 0x00000003
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# Wait for clock switch
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sleep 10
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# GLB_REG_BCLK_DIS_FALSE
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mww 0x40000ffc 0x0
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# HCLK is RC32M, so BCLK/HCLK doesn't need divider
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# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
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mmw 0x40000000 0x0 0x00FFFF00
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# Wait for clock to stabilize
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sleep 10
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}
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# By spec, ndmreset should reset whole chip. This implementation resets only few parts of the chip.
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# CTRL_PWRON_RESET register in GLB core triggers full "power-on like" reset, so we use it instead
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# for full software reset.
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proc bl602_sw_reset { } {
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# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
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mmw 0x40000018 0x0 0x00000007
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# This Software reset method resets everything, so CPU as well.
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# It does that in not much good way, resulting in Debug Module being reset as well.
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# This also means, that right after CPU and Debug Module are turned on, we need to
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# enable Debug Module and halt CPU if needed. Additionally, we trigger this SW reset
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# through system bus access directly with DMI commands, to avoid errors printed by
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# OpenOCD about unsuccessful register write.
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# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
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riscv dmi_write 0x39 0x40000018
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riscv dmi_write 0x3c 0x7
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# We need to wait for chip to finish reset and execute BootROM
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sleep 1
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# JTAG Debug Transport Module is reset as well, so we need to get into RUN/IDLE state
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runtest 10
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# We need to enable Debug Module and halt the CPU, so we can reset Program Counter
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# and to do additional clean-ups. If reset was called without halt, resume is handled
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# by reset-deassert-post event handler.
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# In Debug Module Control (dmcontrol), set dmactive to 1 and then haltreq to 1
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riscv dmi_write $::dmcontrol $::dmcontrol_dmactive
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riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_haltreq} ]
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# Set Program Counter to start of BootROM
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set_reg {pc 0x21000000}
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}
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# On BL602 and BL702, the only way to force chip stay in BootROM (until JTAG attaches)
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# is by putting infinity loop into HBN RAM (which is not reset by sw reset), and then
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# configure HBN registers, which will cause BootROM to jump into our code early in BootROM.
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proc bl602_sw_reset_hbn_wait {} {
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# Restore clocks to defaults
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bl602_restore_clock_defaults
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# In HBN RAM, write infinity loop instruction
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# beq zero, zero, 0
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mww 0x40010000 0x00000063
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# In HNB, set HBN_RSV0 (Status Flag) to "EHBN" (as uint32_t)
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mww 0x4000f100 0x4e424845
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# In HBN, set HBN_RSV1 (WakeUp Address) to HBN RAM address
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mww 0x4000f104 0x40010000
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# Perform software reset
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bl602_sw_reset
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# Clear HBN RAM, HBN_RSV0 and HBN_RSV1
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mww 0x40010000 0x00000000
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mww 0x4000f100 0x00000000
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mww 0x4000f104 0x00000000
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# This early jump method locks up BootROM through Trust Zone Controller.
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# That means any read of BootROM returns 0xDEADBEEF.
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# Only way to reset it, is through JTAG Reset, thus toggling ndmreset in dmcontrol.
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riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_ndmreset} ]
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riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive} ]
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}
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$_TARGETNAME configure -event reset-deassert-post {
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# Resume the processor if reset was triggered without halt request
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if {$halt == 0} {
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riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_resumereq} ]
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}
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}

‎tcl/target/bl702.cfg‎

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# TDO - GPIO9
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#
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source [find mem_helper.tcl]
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transport select jtag
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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set BL602_CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME bl702
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set BL602_CHIPNAME bl702
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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riscv set_mem_access sysbus
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set CPUTAPID 0x20000e05
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$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
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# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP
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set WORKAREAADDR 0x22014000
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set WORKAREASIZE 0xC000
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# Internal RC ticks on 32 MHz, so this speed should be safe to use.
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adapter speed 4000
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source [find target/bl602_common.cfg]
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# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
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# CTRL_PWRON_RESET triggers full "power-on like" reset.
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# This means that pinmux configuration to access JTAG is reset as well, and configured back early
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# in BootROM.
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$_TARGETNAME configure -event reset-assert-pre {
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# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information
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$_TARGETNAME configure -event reset-assert {
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halt
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# Switch clock to internal RC32M
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# In HBN_GLB, set ROOT_CLK_SEL = 0
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mmw 0x4000f030 0x0 0x00000003
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# Wait for clock switch
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sleep 10
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# GLB_REG_BCLK_DIS_FALSE
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mww 0x40000ffc 0x0
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# HCLK is RC32M, so BCLK/HCLK doesn't need divider
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# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
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mmw 0x40000000 0x0 0x00FFFF00
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# Wait for clock to stabilize
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sleep 10
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# Do reset
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# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
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mmw 0x40000018 0x0 0x00000007
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# Since this full software reset resets GPIO pinmux as well, we will lose access
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# to JTAG right away after writing to register. This chip doesn't support abstract
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# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
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# if write was successful or not, and will print error about that. Since receiving of
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# this error is expected, we will turn off log printing for a moment,
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set lvl [lindex [debug_level] 1]
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debug_level -1
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# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
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catch {mmw 0x40000018 0x7 0x0}
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debug_level $lvl
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bl602_sw_reset_hbn_wait
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}

‎tcl/target/bl702l.cfg‎

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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Bouffalo Labs BL702L and BL704L target
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#
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# https://en.bouffalolab.com/product/?type=detail&id=26
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#
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# Default JTAG pins: (if not changed by eFuse configuration)
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# TMS - GPIO0
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# TDI - GPIO1
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# TCK - GPIO2
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# TDO - GPIO7
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#
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if { [info exists CHIPNAME] } {
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set BL602_CHIPNAME $CHIPNAME
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} else {
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set BL602_CHIPNAME bl702l
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}
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set CPUTAPID 0x20000e05
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# For work-area we use beginning of OCRAM, since BL702L have only ITCM, which can be taken
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# by L1 cache and XIP during runtime.
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set WORKAREAADDR 0x42020000
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set WORKAREASIZE 0x10000
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source [find target/bl602_common.cfg]
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# JTAG reset is broken. Read comment of bl602_sw_reset function for more information
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# On BL702L, we are forcing boot into ISP mode, so chip stays in BootROM until JTAG re-attach
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$_TARGETNAME configure -event reset-assert {
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halt
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# Restore clocks to defaults
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bl602_restore_clock_defaults
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# In HBN_RSV2, set HBN_RELEASE_CORE to HBN_RELEASE_CORE_FLAG (4)
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# and HBN_USER_BOOT_SEL to 1 (ISP)
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mww 0x4000f108 0x44000000
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# Perform software reset
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bl602_sw_reset
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# Reset HBN_RSV2 so BootROM will not force ISP mode again
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mww 0x4000f108 0x00000000
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}

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