Mirny: `set_output_power_mu` call change frequency output

[hubuke]

Bug report

Summary

Calling set_output_power_mu cause the output frequency change to unexpected value.

Reproduce script

from artiq.experiment import *

class MirnyBug(EnvExperiment):
    def build(self):
        self.setattr_device("core")
        self.setattr_device("mirny0_ch0")
        self.setattr_device("mirny0_cpld")

    @kernel
    def run(self):
        self.core.reset()
        self.core.break_realtime()
        self.mirny0_cpld.init()
        self.mirny0_ch0.init()
        self.mirny0_ch0.set_output_power_mu(3)
        self.mirny0_ch0.set_att(20*dB)
        self.mirny0_ch0.set_frequency(250*MHz)
        self.mirny0_ch0.sw.on()
        delay(100*s)

Comment out the self.mirny0_ch0.set_output_power_mu(3) would have correct output frequency.

System

Artiq master branch
Mirny with XO clk.

Potential Cause

1. set_output_power_mu writing the wrong register
2. self.sync() update the wrong register

[hubuke]

Expected output frequency

Actual output frequency