Skip to content

Commit c9c9307

Browse files
author
whitequark
committed
test_sim: add missing add_process().
Fixes #43.
1 parent 23a07b9 commit c9c9307

File tree

1 file changed

+3
-2
lines changed

1 file changed

+3
-2
lines changed

nmigen/test/test_sim.py

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -376,9 +376,10 @@ def test_run_until(self):
376376
with self.assertSimulation(Module(), deadline=100e-6) as sim:
377377
sim.add_clock(1e-6)
378378
def process():
379-
for _ in range(100):
380-
yield
379+
for _ in range(101):
380+
yield Delay(1e-6)
381381
self.fail()
382+
sim.add_process(process)
382383

383384
def test_add_process_wrong(self):
384385
with self.assertSimulation(Module()) as sim:

0 commit comments

Comments
 (0)