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mag-mgamag-mga
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Fix compress-opt-select test after merge llvm#115297
This test has been failed after commit [RISCV] Implement tail call optimization in machine outliner (PR llvm#115297). Changes to the same file were merged today earlier [TTI][RISCV] Unconditionally break critical edges to sink ADDI (PR llvm#108889).
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lines changed

1 file changed

+48
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‎llvm/test/CodeGen/RISCV/compress-opt-select.ll‎

Lines changed: 48 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -13,11 +13,9 @@ define i32 @ne_small_pos(i32 %in0) minsize {
1313
; RV32IFDC-NEXT: c.li a1, 20
1414
; RV32IFDC-NEXT: bne a0, a1, .LBB0_2
1515
; RV32IFDC-NEXT: # %bb.1:
16-
; RV32IFDC-NEXT: addi a0, zero, 42
17-
; RV32IFDC-NEXT: c.jr ra
16+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
1817
; RV32IFDC-NEXT: .LBB0_2:
19-
; RV32IFDC-NEXT: addi a0, zero, -99
20-
; RV32IFDC-NEXT: c.jr ra
18+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
2119
;
2220
; RV32IFD-LABEL: ne_small_pos:
2321
; RV32IFD: # %bb.0:
@@ -41,11 +39,9 @@ define i32 @ne_small_neg(i32 %in0) minsize {
4139
; RV32IFDC-NEXT: c.li a1, -20
4240
; RV32IFDC-NEXT: bne a0, a1, .LBB1_2
4341
; RV32IFDC-NEXT: # %bb.1:
44-
; RV32IFDC-NEXT: addi a0, zero, 42
45-
; RV32IFDC-NEXT: c.jr ra
42+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
4643
; RV32IFDC-NEXT: .LBB1_2:
47-
; RV32IFDC-NEXT: addi a0, zero, -99
48-
; RV32IFDC-NEXT: c.jr ra
44+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
4945
;
5046
; RV32IFD-LABEL: ne_small_neg:
5147
; RV32IFD: # %bb.0:
@@ -69,11 +65,9 @@ define i32 @ne_small_edge_pos(i32 %in0) minsize {
6965
; RV32IFDC-NEXT: c.li a1, 31
7066
; RV32IFDC-NEXT: bne a0, a1, .LBB2_2
7167
; RV32IFDC-NEXT: # %bb.1:
72-
; RV32IFDC-NEXT: addi a0, zero, 42
73-
; RV32IFDC-NEXT: c.jr ra
68+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
7469
; RV32IFDC-NEXT: .LBB2_2:
75-
; RV32IFDC-NEXT: addi a0, zero, -99
76-
; RV32IFDC-NEXT: c.jr ra
70+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
7771
;
7872
; RV32IFD-LABEL: ne_small_edge_pos:
7973
; RV32IFD: # %bb.0:
@@ -97,11 +91,9 @@ define i32 @ne_small_edge_neg(i32 %in0) minsize {
9791
; RV32IFDC-NEXT: c.li a1, -32
9892
; RV32IFDC-NEXT: bne a0, a1, .LBB3_2
9993
; RV32IFDC-NEXT: # %bb.1:
100-
; RV32IFDC-NEXT: addi a0, zero, 42
101-
; RV32IFDC-NEXT: c.jr ra
94+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
10295
; RV32IFDC-NEXT: .LBB3_2:
103-
; RV32IFDC-NEXT: addi a0, zero, -99
104-
; RV32IFDC-NEXT: c.jr ra
96+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
10597
;
10698
; RV32IFD-LABEL: ne_small_edge_neg:
10799
; RV32IFD: # %bb.0:
@@ -126,11 +118,9 @@ define i32 @ne_medium_ledge_pos(i32 %in0) minsize {
126118
; RV32IFDC-NEXT: addi a0, a0, -33
127119
; RV32IFDC-NEXT: c.bnez a0, .LBB4_2
128120
; RV32IFDC-NEXT: # %bb.1:
129-
; RV32IFDC-NEXT: addi a0, zero, 42
130-
; RV32IFDC-NEXT: c.jr ra
121+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
131122
; RV32IFDC-NEXT: .LBB4_2:
132-
; RV32IFDC-NEXT: addi a0, zero, -99
133-
; RV32IFDC-NEXT: c.jr ra
123+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
134124
;
135125
; RV32IFD-LABEL: ne_medium_ledge_pos:
136126
; RV32IFD: # %bb.0:
@@ -155,11 +145,9 @@ define i32 @ne_medium_ledge_neg(i32 %in0) minsize {
155145
; RV32IFDC-NEXT: addi a0, a0, 33
156146
; RV32IFDC-NEXT: c.bnez a0, .LBB5_2
157147
; RV32IFDC-NEXT: # %bb.1:
158-
; RV32IFDC-NEXT: addi a0, zero, 42
159-
; RV32IFDC-NEXT: c.jr ra
148+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
160149
; RV32IFDC-NEXT: .LBB5_2:
161-
; RV32IFDC-NEXT: addi a0, zero, -99
162-
; RV32IFDC-NEXT: c.jr ra
150+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
163151
;
164152
; RV32IFD-LABEL: ne_medium_ledge_neg:
165153
; RV32IFD: # %bb.0:
@@ -184,11 +172,9 @@ define i32 @ne_medium_pos(i32 %in0) minsize {
184172
; RV32IFDC-NEXT: addi a0, a0, -63
185173
; RV32IFDC-NEXT: c.bnez a0, .LBB6_2
186174
; RV32IFDC-NEXT: # %bb.1:
187-
; RV32IFDC-NEXT: addi a0, zero, 42
188-
; RV32IFDC-NEXT: c.jr ra
175+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
189176
; RV32IFDC-NEXT: .LBB6_2:
190-
; RV32IFDC-NEXT: addi a0, zero, -99
191-
; RV32IFDC-NEXT: c.jr ra
177+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
192178
;
193179
; RV32IFD-LABEL: ne_medium_pos:
194180
; RV32IFD: # %bb.0:
@@ -213,11 +199,9 @@ define i32 @ne_medium_neg(i32 %in0) minsize {
213199
; RV32IFDC-NEXT: addi a0, a0, 63
214200
; RV32IFDC-NEXT: c.bnez a0, .LBB7_2
215201
; RV32IFDC-NEXT: # %bb.1:
216-
; RV32IFDC-NEXT: addi a0, zero, 42
217-
; RV32IFDC-NEXT: c.jr ra
202+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
218203
; RV32IFDC-NEXT: .LBB7_2:
219-
; RV32IFDC-NEXT: addi a0, zero, -99
220-
; RV32IFDC-NEXT: c.jr ra
204+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
221205
;
222206
; RV32IFD-LABEL: ne_medium_neg:
223207
; RV32IFD: # %bb.0:
@@ -242,11 +226,9 @@ define i32 @ne_medium_bedge_pos(i32 %in0) minsize {
242226
; RV32IFDC-NEXT: addi a0, a0, -2047
243227
; RV32IFDC-NEXT: c.bnez a0, .LBB8_2
244228
; RV32IFDC-NEXT: # %bb.1:
245-
; RV32IFDC-NEXT: addi a0, zero, 42
246-
; RV32IFDC-NEXT: c.jr ra
229+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
247230
; RV32IFDC-NEXT: .LBB8_2:
248-
; RV32IFDC-NEXT: addi a0, zero, -99
249-
; RV32IFDC-NEXT: c.jr ra
231+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
250232
;
251233
; RV32IFD-LABEL: ne_medium_bedge_pos:
252234
; RV32IFD: # %bb.0:
@@ -271,11 +253,9 @@ define i32 @ne_medium_bedge_neg(i32 %in0) minsize {
271253
; RV32IFDC-NEXT: addi a0, a0, 2047
272254
; RV32IFDC-NEXT: c.bnez a0, .LBB9_2
273255
; RV32IFDC-NEXT: # %bb.1:
274-
; RV32IFDC-NEXT: addi a0, zero, 42
275-
; RV32IFDC-NEXT: c.jr ra
256+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
276257
; RV32IFDC-NEXT: .LBB9_2:
277-
; RV32IFDC-NEXT: addi a0, zero, -99
278-
; RV32IFDC-NEXT: c.jr ra
258+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
279259
;
280260
; RV32IFD-LABEL: ne_medium_bedge_neg:
281261
; RV32IFD: # %bb.0:
@@ -300,11 +280,9 @@ define i32 @ne_big_ledge_pos(i32 %in0) minsize {
300280
; RV32IFDC-NEXT: c.slli a1, 11
301281
; RV32IFDC-NEXT: bne a0, a1, .LBB10_2
302282
; RV32IFDC-NEXT: # %bb.1:
303-
; RV32IFDC-NEXT: addi a0, zero, 42
304-
; RV32IFDC-NEXT: c.jr ra
283+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
305284
; RV32IFDC-NEXT: .LBB10_2:
306-
; RV32IFDC-NEXT: addi a0, zero, -99
307-
; RV32IFDC-NEXT: c.jr ra
285+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
308286
;
309287
; RV32IFD-LABEL: ne_big_ledge_pos:
310288
; RV32IFD: # %bb.0:
@@ -329,11 +307,9 @@ define i32 @ne_big_ledge_neg(i32 %in0) minsize {
329307
; RV32IFDC-NEXT: addi a1, zero, -2048
330308
; RV32IFDC-NEXT: bne a0, a1, .LBB11_2
331309
; RV32IFDC-NEXT: # %bb.1:
332-
; RV32IFDC-NEXT: addi a0, zero, 42
333-
; RV32IFDC-NEXT: c.jr ra
310+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
334311
; RV32IFDC-NEXT: .LBB11_2:
335-
; RV32IFDC-NEXT: addi a0, zero, -99
336-
; RV32IFDC-NEXT: c.jr ra
312+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
337313
;
338314
; RV32IFD-LABEL: ne_big_ledge_neg:
339315
; RV32IFD: # %bb.0:
@@ -360,11 +336,9 @@ define i32 @eq_small_pos(i32 %in0) minsize {
360336
; RV32IFDC-NEXT: c.li a1, 20
361337
; RV32IFDC-NEXT: beq a0, a1, .LBB12_2
362338
; RV32IFDC-NEXT: # %bb.1:
363-
; RV32IFDC-NEXT: addi a0, zero, 42
364-
; RV32IFDC-NEXT: c.jr ra
339+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
365340
; RV32IFDC-NEXT: .LBB12_2:
366-
; RV32IFDC-NEXT: addi a0, zero, -99
367-
; RV32IFDC-NEXT: c.jr ra
341+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
368342
;
369343
; RV32IFD-LABEL: eq_small_pos:
370344
; RV32IFD: # %bb.0:
@@ -388,11 +362,9 @@ define i32 @eq_small_neg(i32 %in0) minsize {
388362
; RV32IFDC-NEXT: c.li a1, -20
389363
; RV32IFDC-NEXT: beq a0, a1, .LBB13_2
390364
; RV32IFDC-NEXT: # %bb.1:
391-
; RV32IFDC-NEXT: addi a0, zero, 42
392-
; RV32IFDC-NEXT: c.jr ra
365+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
393366
; RV32IFDC-NEXT: .LBB13_2:
394-
; RV32IFDC-NEXT: addi a0, zero, -99
395-
; RV32IFDC-NEXT: c.jr ra
367+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
396368
;
397369
; RV32IFD-LABEL: eq_small_neg:
398370
; RV32IFD: # %bb.0:
@@ -416,11 +388,9 @@ define i32 @eq_small_edge_pos(i32 %in0) minsize {
416388
; RV32IFDC-NEXT: c.li a1, 31
417389
; RV32IFDC-NEXT: beq a0, a1, .LBB14_2
418390
; RV32IFDC-NEXT: # %bb.1:
419-
; RV32IFDC-NEXT: addi a0, zero, 42
420-
; RV32IFDC-NEXT: c.jr ra
391+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
421392
; RV32IFDC-NEXT: .LBB14_2:
422-
; RV32IFDC-NEXT: addi a0, zero, -99
423-
; RV32IFDC-NEXT: c.jr ra
393+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
424394
;
425395
; RV32IFD-LABEL: eq_small_edge_pos:
426396
; RV32IFD: # %bb.0:
@@ -444,11 +414,9 @@ define i32 @eq_small_edge_neg(i32 %in0) minsize {
444414
; RV32IFDC-NEXT: c.li a1, -32
445415
; RV32IFDC-NEXT: beq a0, a1, .LBB15_2
446416
; RV32IFDC-NEXT: # %bb.1:
447-
; RV32IFDC-NEXT: addi a0, zero, 42
448-
; RV32IFDC-NEXT: c.jr ra
417+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
449418
; RV32IFDC-NEXT: .LBB15_2:
450-
; RV32IFDC-NEXT: addi a0, zero, -99
451-
; RV32IFDC-NEXT: c.jr ra
419+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
452420
;
453421
; RV32IFD-LABEL: eq_small_edge_neg:
454422
; RV32IFD: # %bb.0:
@@ -473,11 +441,9 @@ define i32 @eq_medium_ledge_pos(i32 %in0) minsize {
473441
; RV32IFDC-NEXT: addi a0, a0, -33
474442
; RV32IFDC-NEXT: c.beqz a0, .LBB16_2
475443
; RV32IFDC-NEXT: # %bb.1:
476-
; RV32IFDC-NEXT: addi a0, zero, 42
477-
; RV32IFDC-NEXT: c.jr ra
444+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
478445
; RV32IFDC-NEXT: .LBB16_2:
479-
; RV32IFDC-NEXT: addi a0, zero, -99
480-
; RV32IFDC-NEXT: c.jr ra
446+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
481447
;
482448
; RV32IFD-LABEL: eq_medium_ledge_pos:
483449
; RV32IFD: # %bb.0:
@@ -502,11 +468,9 @@ define i32 @eq_medium_ledge_neg(i32 %in0) minsize {
502468
; RV32IFDC-NEXT: addi a0, a0, 33
503469
; RV32IFDC-NEXT: c.beqz a0, .LBB17_2
504470
; RV32IFDC-NEXT: # %bb.1:
505-
; RV32IFDC-NEXT: addi a0, zero, 42
506-
; RV32IFDC-NEXT: c.jr ra
471+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
507472
; RV32IFDC-NEXT: .LBB17_2:
508-
; RV32IFDC-NEXT: addi a0, zero, -99
509-
; RV32IFDC-NEXT: c.jr ra
473+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
510474
;
511475
; RV32IFD-LABEL: eq_medium_ledge_neg:
512476
; RV32IFD: # %bb.0:
@@ -531,11 +495,9 @@ define i32 @eq_medium_pos(i32 %in0) minsize {
531495
; RV32IFDC-NEXT: addi a0, a0, -63
532496
; RV32IFDC-NEXT: c.beqz a0, .LBB18_2
533497
; RV32IFDC-NEXT: # %bb.1:
534-
; RV32IFDC-NEXT: addi a0, zero, 42
535-
; RV32IFDC-NEXT: c.jr ra
498+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
536499
; RV32IFDC-NEXT: .LBB18_2:
537-
; RV32IFDC-NEXT: addi a0, zero, -99
538-
; RV32IFDC-NEXT: c.jr ra
500+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
539501
;
540502
; RV32IFD-LABEL: eq_medium_pos:
541503
; RV32IFD: # %bb.0:
@@ -560,11 +522,9 @@ define i32 @eq_medium_neg(i32 %in0) minsize {
560522
; RV32IFDC-NEXT: addi a0, a0, 63
561523
; RV32IFDC-NEXT: c.beqz a0, .LBB19_2
562524
; RV32IFDC-NEXT: # %bb.1:
563-
; RV32IFDC-NEXT: addi a0, zero, 42
564-
; RV32IFDC-NEXT: c.jr ra
525+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
565526
; RV32IFDC-NEXT: .LBB19_2:
566-
; RV32IFDC-NEXT: addi a0, zero, -99
567-
; RV32IFDC-NEXT: c.jr ra
527+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
568528
;
569529
; RV32IFD-LABEL: eq_medium_neg:
570530
; RV32IFD: # %bb.0:
@@ -589,11 +549,9 @@ define i32 @eq_medium_bedge_pos(i32 %in0) minsize {
589549
; RV32IFDC-NEXT: addi a0, a0, -2047
590550
; RV32IFDC-NEXT: c.beqz a0, .LBB20_2
591551
; RV32IFDC-NEXT: # %bb.1:
592-
; RV32IFDC-NEXT: addi a0, zero, 42
593-
; RV32IFDC-NEXT: c.jr ra
552+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
594553
; RV32IFDC-NEXT: .LBB20_2:
595-
; RV32IFDC-NEXT: addi a0, zero, -99
596-
; RV32IFDC-NEXT: c.jr ra
554+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
597555
;
598556
; RV32IFD-LABEL: eq_medium_bedge_pos:
599557
; RV32IFD: # %bb.0:
@@ -618,11 +576,9 @@ define i32 @eq_medium_bedge_neg(i32 %in0) minsize {
618576
; RV32IFDC-NEXT: addi a0, a0, 2047
619577
; RV32IFDC-NEXT: c.beqz a0, .LBB21_2
620578
; RV32IFDC-NEXT: # %bb.1:
621-
; RV32IFDC-NEXT: addi a0, zero, 42
622-
; RV32IFDC-NEXT: c.jr ra
579+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
623580
; RV32IFDC-NEXT: .LBB21_2:
624-
; RV32IFDC-NEXT: addi a0, zero, -99
625-
; RV32IFDC-NEXT: c.jr ra
581+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
626582
;
627583
; RV32IFD-LABEL: eq_medium_bedge_neg:
628584
; RV32IFD: # %bb.0:
@@ -647,11 +603,9 @@ define i32 @eq_big_ledge_pos(i32 %in0) minsize {
647603
; RV32IFDC-NEXT: c.slli a1, 11
648604
; RV32IFDC-NEXT: beq a0, a1, .LBB22_2
649605
; RV32IFDC-NEXT: # %bb.1:
650-
; RV32IFDC-NEXT: addi a0, zero, 42
651-
; RV32IFDC-NEXT: c.jr ra
606+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
652607
; RV32IFDC-NEXT: .LBB22_2:
653-
; RV32IFDC-NEXT: addi a0, zero, -99
654-
; RV32IFDC-NEXT: c.jr ra
608+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
655609
;
656610
; RV32IFD-LABEL: eq_big_ledge_pos:
657611
; RV32IFD: # %bb.0:
@@ -676,11 +630,9 @@ define i32 @eq_big_ledge_neg(i32 %in0) minsize {
676630
; RV32IFDC-NEXT: addi a1, zero, -2048
677631
; RV32IFDC-NEXT: beq a0, a1, .LBB23_2
678632
; RV32IFDC-NEXT: # %bb.1:
679-
; RV32IFDC-NEXT: addi a0, zero, 42
680-
; RV32IFDC-NEXT: c.jr ra
633+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_1
681634
; RV32IFDC-NEXT: .LBB23_2:
682-
; RV32IFDC-NEXT: addi a0, zero, -99
683-
; RV32IFDC-NEXT: c.jr ra
635+
; RV32IFDC-NEXT: tail OUTLINED_FUNCTION_0
684636
;
685637
; RV32IFD-LABEL: eq_big_ledge_neg:
686638
; RV32IFD: # %bb.0:

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