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[AArch64] Add tests for partial reduction of shl.
Add tests with partial reductions where the operand is a shift instead of a mul.
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‎llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll‎

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@@ -1255,3 +1255,151 @@ entry:
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%partial.reduce = tail call <2 x i64> @llvm.vector.partial.reduce.add(<2 x i64> %acc, <8 x i64> %input.wide)
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ret <2 x i64> %partial.reduce
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}
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define <4 x i32> @partial_reduce_shl_sext_const_rhs6(<16 x i8> %l, <4 x i32> %part) {
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; CHECK-COMMON-LABEL: partial_reduce_shl_sext_const_rhs6:
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; CHECK-COMMON: // %bb.0:
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; CHECK-COMMON-NEXT: sshll v2.8h, v0.8b, #0
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; CHECK-COMMON-NEXT: sshll2 v0.8h, v0.16b, #0
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; CHECK-COMMON-NEXT: sshll v3.4s, v0.4h, #6
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; CHECK-COMMON-NEXT: sshll2 v4.4s, v2.8h, #6
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; CHECK-COMMON-NEXT: sshll v2.4s, v2.4h, #6
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; CHECK-COMMON-NEXT: sshll2 v0.4s, v0.8h, #6
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v2.4s, v4.4s, v3.4s
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-COMMON-NEXT: ret
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%ext = sext <16 x i8> %l to <16 x i32>
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%shift = shl nsw <16 x i32> %ext, splat (i32 6)
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%red = tail call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %part, <16 x i32> %shift)
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ret <4 x i32> %red
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}
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define <4 x i32> @partial_reduce_shl_sext_const_rhs8(<16 x i8> %l, <4 x i32> %part) {
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; CHECK-COMMON-LABEL: partial_reduce_shl_sext_const_rhs8:
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; CHECK-COMMON: // %bb.0:
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; CHECK-COMMON-NEXT: sshll v2.8h, v0.8b, #0
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; CHECK-COMMON-NEXT: sshll2 v0.8h, v0.16b, #0
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; CHECK-COMMON-NEXT: sshll v3.4s, v0.4h, #8
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; CHECK-COMMON-NEXT: sshll2 v4.4s, v2.8h, #8
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; CHECK-COMMON-NEXT: sshll v2.4s, v2.4h, #8
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; CHECK-COMMON-NEXT: sshll2 v0.4s, v0.8h, #8
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v2.4s, v4.4s, v3.4s
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-COMMON-NEXT: ret
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%ext = sext <16 x i8> %l to <16 x i32>
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%shift = shl nsw <16 x i32> %ext, splat (i32 8)
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%red = tail call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %part, <16 x i32> %shift)
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ret <4 x i32> %red
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}
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define <4 x i32> @partial_reduce_shl_sext_const_rhs_9(<16 x i8> %l, <4 x i32> %part) {
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; CHECK-COMMON-LABEL: partial_reduce_shl_sext_const_rhs_9:
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; CHECK-COMMON: // %bb.0:
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; CHECK-COMMON-NEXT: ret
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%ext = sext <16 x i8> %l to <16 x i32>
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%shift = shl nsw <16 x i32> %ext, splat (i32 32)
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%red = tail call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %part, <16 x i32> %shift)
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ret <4 x i32> %red
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}
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define <4 x i32> @partial_reduce_shl_sext_non_const_rhs(<16 x i8> %l, <4 x i32> %part) {
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; CHECK-COMMON-LABEL: partial_reduce_shl_sext_non_const_rhs:
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; CHECK-COMMON: // %bb.0:
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; CHECK-COMMON-NEXT: sshll v2.8h, v0.8b, #0
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; CHECK-COMMON-NEXT: sshll2 v0.8h, v0.16b, #0
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; CHECK-COMMON-NEXT: sshll v3.4s, v2.4h, #0
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; CHECK-COMMON-NEXT: sshll2 v2.4s, v2.8h, #0
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; CHECK-COMMON-NEXT: sshll v4.4s, v0.4h, #0
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; CHECK-COMMON-NEXT: sshll2 v0.4s, v0.8h, #0
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; CHECK-COMMON-NEXT: ushl v4.4s, v4.4s, v4.4s
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; CHECK-COMMON-NEXT: ushl v2.4s, v2.4s, v2.4s
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; CHECK-COMMON-NEXT: ushl v3.4s, v3.4s, v3.4s
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; CHECK-COMMON-NEXT: ushl v0.4s, v0.4s, v0.4s
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v3.4s
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; CHECK-COMMON-NEXT: add v2.4s, v2.4s, v4.4s
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-COMMON-NEXT: ret
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%ext = sext <16 x i8> %l to <16 x i32>
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%shift = shl nsw <16 x i32> %ext, %ext
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%red = tail call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %part, <16 x i32> %shift)
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ret <4 x i32> %red
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}
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define <4 x i32> @partial_reduce_shl_zext_const_rhs6(<16 x i8> %l, <4 x i32> %part) {
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; CHECK-COMMON-LABEL: partial_reduce_shl_zext_const_rhs6:
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; CHECK-COMMON: // %bb.0:
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; CHECK-COMMON-NEXT: ushll v2.8h, v0.8b, #0
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; CHECK-COMMON-NEXT: ushll2 v0.8h, v0.16b, #0
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; CHECK-COMMON-NEXT: ushll v3.4s, v0.4h, #6
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; CHECK-COMMON-NEXT: ushll2 v4.4s, v2.8h, #6
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; CHECK-COMMON-NEXT: ushll v2.4s, v2.4h, #6
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; CHECK-COMMON-NEXT: ushll2 v0.4s, v0.8h, #6
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v2.4s, v4.4s, v3.4s
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-COMMON-NEXT: ret
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%ext = zext <16 x i8> %l to <16 x i32>
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%shift = shl nsw <16 x i32> %ext, splat (i32 6)
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%red = tail call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %part, <16 x i32> %shift)
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ret <4 x i32> %red
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}
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define <4 x i32> @partial_reduce_shl_zext_const_rhs8(<16 x i8> %l, <4 x i32> %part) {
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; CHECK-COMMON-LABEL: partial_reduce_shl_zext_const_rhs8:
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; CHECK-COMMON: // %bb.0:
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; CHECK-COMMON-NEXT: ushll v2.8h, v0.8b, #0
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; CHECK-COMMON-NEXT: ushll2 v0.8h, v0.16b, #0
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; CHECK-COMMON-NEXT: ushll v3.4s, v0.4h, #8
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; CHECK-COMMON-NEXT: ushll2 v4.4s, v2.8h, #8
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; CHECK-COMMON-NEXT: ushll v2.4s, v2.4h, #8
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; CHECK-COMMON-NEXT: ushll2 v0.4s, v0.8h, #8
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v2.4s, v4.4s, v3.4s
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-COMMON-NEXT: ret
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%ext = zext <16 x i8> %l to <16 x i32>
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%shift = shl nsw <16 x i32> %ext, splat (i32 8)
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%red = tail call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %part, <16 x i32> %shift)
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ret <4 x i32> %red
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}
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define <4 x i32> @partial_reduce_shl_zext_const_rhs_9(<16 x i8> %l, <4 x i32> %part) {
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; CHECK-COMMON-LABEL: partial_reduce_shl_zext_const_rhs_9:
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; CHECK-COMMON: // %bb.0:
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; CHECK-COMMON-NEXT: ret
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%ext = zext <16 x i8> %l to <16 x i32>
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%shift = shl nsw <16 x i32> %ext, splat (i32 32)
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%red = tail call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %part, <16 x i32> %shift)
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ret <4 x i32> %red
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}
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define <4 x i32> @partial_reduce_shl_zext_non_const_rhs(<16 x i8> %l, <4 x i32> %part) {
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; CHECK-COMMON-LABEL: partial_reduce_shl_zext_non_const_rhs:
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; CHECK-COMMON: // %bb.0:
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; CHECK-COMMON-NEXT: ushll v2.8h, v0.8b, #0
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; CHECK-COMMON-NEXT: ushll2 v0.8h, v0.16b, #0
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; CHECK-COMMON-NEXT: ushll v3.4s, v2.4h, #0
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; CHECK-COMMON-NEXT: ushll2 v2.4s, v2.8h, #0
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; CHECK-COMMON-NEXT: ushll v4.4s, v0.4h, #0
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; CHECK-COMMON-NEXT: ushll2 v0.4s, v0.8h, #0
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; CHECK-COMMON-NEXT: ushl v4.4s, v4.4s, v4.4s
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; CHECK-COMMON-NEXT: ushl v2.4s, v2.4s, v2.4s
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; CHECK-COMMON-NEXT: ushl v3.4s, v3.4s, v3.4s
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; CHECK-COMMON-NEXT: ushl v0.4s, v0.4s, v0.4s
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v3.4s
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; CHECK-COMMON-NEXT: add v2.4s, v2.4s, v4.4s
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; CHECK-COMMON-NEXT: add v1.4s, v1.4s, v2.4s
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; CHECK-COMMON-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-COMMON-NEXT: ret
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%ext = zext <16 x i8> %l to <16 x i32>
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%shift = shl nsw <16 x i32> %ext, %ext
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%red = tail call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %part, <16 x i32> %shift)
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ret <4 x i32> %red
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}

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