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zhaoqi5mahesh-attarde
zhaoqi5
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mahesh-attarde
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[LoongArch][NFC] Pre-commit tests for [x]vadda.{b/h/w/d} 
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  • llvm/test/CodeGen/LoongArch

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‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/adda.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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define void @vadda_b(ptr %res, ptr %a, ptr %b) nounwind {
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; CHECK-LABEL: vadda_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvneg.b $xr2, $xr0
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; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr2
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; CHECK-NEXT: xvneg.b $xr2, $xr1
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; CHECK-NEXT: xvmax.b $xr1, $xr1, $xr2
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; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%va = load <32 x i8>, ptr %a
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%vb = load <32 x i8>, ptr %b
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%conda = icmp slt <32 x i8> %va, zeroinitializer
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%nega = sub <32 x i8> zeroinitializer, %va
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%absa = select <32 x i1> %conda, <32 x i8> %nega, <32 x i8> %va
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%condb = icmp slt <32 x i8> %vb, zeroinitializer
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%negb = sub <32 x i8> zeroinitializer, %vb
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%absb = select <32 x i1> %condb, <32 x i8> %negb, <32 x i8> %vb
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%add = add <32 x i8> %absa, %absb
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store <32 x i8> %add, ptr %res
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ret void
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}
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define void @vadda_h(ptr %res, ptr %a, ptr %b) nounwind {
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; CHECK-LABEL: vadda_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvneg.h $xr2, $xr0
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; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr2
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; CHECK-NEXT: xvneg.h $xr2, $xr1
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; CHECK-NEXT: xvmax.h $xr1, $xr1, $xr2
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; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%va = load <16 x i16>, ptr %a
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%vb = load <16 x i16>, ptr %b
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%conda = icmp slt <16 x i16> %va, zeroinitializer
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%nega = sub <16 x i16> zeroinitializer, %va
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%absa = select <16 x i1> %conda, <16 x i16> %nega, <16 x i16> %va
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%condb = icmp slt <16 x i16> %vb, zeroinitializer
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%negb = sub <16 x i16> zeroinitializer, %vb
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%absb = select <16 x i1> %condb, <16 x i16> %negb, <16 x i16> %vb
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%add = add <16 x i16> %absa, %absb
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store <16 x i16> %add, ptr %res
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ret void
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}
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define void @vadda_w(ptr %res, ptr %a, ptr %b) nounwind {
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; CHECK-LABEL: vadda_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvneg.w $xr2, $xr0
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; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr2
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; CHECK-NEXT: xvneg.w $xr2, $xr1
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; CHECK-NEXT: xvmax.w $xr1, $xr1, $xr2
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; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%va = load <8 x i32>, ptr %a
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%vb = load <8 x i32>, ptr %b
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%conda = icmp slt <8 x i32> %va, zeroinitializer
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%nega = sub <8 x i32> zeroinitializer, %va
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%absa = select <8 x i1> %conda, <8 x i32> %nega, <8 x i32> %va
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%condb = icmp slt <8 x i32> %vb, zeroinitializer
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%negb = sub <8 x i32> zeroinitializer, %vb
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%absb = select <8 x i1> %condb, <8 x i32> %negb, <8 x i32> %vb
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%add = add <8 x i32> %absa, %absb
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store <8 x i32> %add, ptr %res
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ret void
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}
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define void @vadda_d(ptr %res, ptr %a, ptr %b) nounwind {
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; CHECK-LABEL: vadda_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvld $xr0, $a1, 0
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; CHECK-NEXT: xvld $xr1, $a2, 0
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; CHECK-NEXT: xvneg.d $xr2, $xr0
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; CHECK-NEXT: xvmax.d $xr0, $xr0, $xr2
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; CHECK-NEXT: xvneg.d $xr2, $xr1
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; CHECK-NEXT: xvmax.d $xr1, $xr1, $xr2
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; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
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; CHECK-NEXT: xvst $xr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%va = load <4 x i64>, ptr %a
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%vb = load <4 x i64>, ptr %b
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%conda = icmp slt <4 x i64> %va, zeroinitializer
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%nega = sub <4 x i64> zeroinitializer, %va
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%absa = select <4 x i1> %conda, <4 x i64> %nega, <4 x i64> %va
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%condb = icmp slt <4 x i64> %vb, zeroinitializer
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%negb = sub <4 x i64> zeroinitializer, %vb
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%absb = select <4 x i1> %condb, <4 x i64> %negb, <4 x i64> %vb
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%add = add <4 x i64> %absa, %absb
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store <4 x i64> %add, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/adda.ll‎

Lines changed: 107 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @vadda_b(ptr %res, ptr %a, ptr %b) nounwind {
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; CHECK-LABEL: vadda_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vneg.b $vr2, $vr0
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; CHECK-NEXT: vmax.b $vr0, $vr0, $vr2
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; CHECK-NEXT: vneg.b $vr2, $vr1
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; CHECK-NEXT: vmax.b $vr1, $vr1, $vr2
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; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%va = load <16 x i8>, ptr %a
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%vb = load <16 x i8>, ptr %b
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%conda = icmp slt <16 x i8> %va, zeroinitializer
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%nega = sub <16 x i8> zeroinitializer, %va
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%absa = select <16 x i1> %conda, <16 x i8> %nega, <16 x i8> %va
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%condb = icmp slt <16 x i8> %vb, zeroinitializer
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%negb = sub <16 x i8> zeroinitializer, %vb
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%absb = select <16 x i1> %condb, <16 x i8> %negb, <16 x i8> %vb
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%add = add <16 x i8> %absa, %absb
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store <16 x i8> %add, ptr %res
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ret void
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}
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define void @vadda_h(ptr %res, ptr %a, ptr %b) nounwind {
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; CHECK-LABEL: vadda_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vneg.h $vr2, $vr0
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; CHECK-NEXT: vmax.h $vr0, $vr0, $vr2
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; CHECK-NEXT: vneg.h $vr2, $vr1
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; CHECK-NEXT: vmax.h $vr1, $vr1, $vr2
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; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%va = load <8 x i16>, ptr %a
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%vb = load <8 x i16>, ptr %b
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%conda = icmp slt <8 x i16> %va, zeroinitializer
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%nega = sub <8 x i16> zeroinitializer, %va
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%absa = select <8 x i1> %conda, <8 x i16> %nega, <8 x i16> %va
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%condb = icmp slt <8 x i16> %vb, zeroinitializer
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%negb = sub <8 x i16> zeroinitializer, %vb
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%absb = select <8 x i1> %condb, <8 x i16> %negb, <8 x i16> %vb
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%add = add <8 x i16> %absa, %absb
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store <8 x i16> %add, ptr %res
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ret void
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}
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define void @vadda_w(ptr %res, ptr %a, ptr %b) nounwind {
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; CHECK-LABEL: vadda_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vneg.w $vr2, $vr0
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; CHECK-NEXT: vmax.w $vr0, $vr0, $vr2
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; CHECK-NEXT: vneg.w $vr2, $vr1
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; CHECK-NEXT: vmax.w $vr1, $vr1, $vr2
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; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%va = load <4 x i32>, ptr %a
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%vb = load <4 x i32>, ptr %b
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%conda = icmp slt <4 x i32> %va, zeroinitializer
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%nega = sub <4 x i32> zeroinitializer, %va
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%absa = select <4 x i1> %conda, <4 x i32> %nega, <4 x i32> %va
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%condb = icmp slt <4 x i32> %vb, zeroinitializer
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%negb = sub <4 x i32> zeroinitializer, %vb
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%absb = select <4 x i1> %condb, <4 x i32> %negb, <4 x i32> %vb
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%add = add <4 x i32> %absa, %absb
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store <4 x i32> %add, ptr %res
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ret void
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}
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define void @vadda_d(ptr %res, ptr %a, ptr %b) nounwind {
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; CHECK-LABEL: vadda_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vld $vr1, $a2, 0
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; CHECK-NEXT: vneg.d $vr2, $vr0
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; CHECK-NEXT: vmax.d $vr0, $vr0, $vr2
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; CHECK-NEXT: vneg.d $vr2, $vr1
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; CHECK-NEXT: vmax.d $vr1, $vr1, $vr2
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; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%va = load <2 x i64>, ptr %a
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%vb = load <2 x i64>, ptr %b
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%conda = icmp slt <2 x i64> %va, zeroinitializer
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%nega = sub <2 x i64> zeroinitializer, %va
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%absa = select <2 x i1> %conda, <2 x i64> %nega, <2 x i64> %va
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%condb = icmp slt <2 x i64> %vb, zeroinitializer
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%negb = sub <2 x i64> zeroinitializer, %vb
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%absb = select <2 x i1> %condb, <2 x i64> %negb, <2 x i64> %vb
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%add = add <2 x i64> %absa, %absb
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store <2 x i64> %add, ptr %res
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ret void
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}

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