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[NFC][PowerPC] Consolidate predicate definitions into PPC.td (llvm#160579)
Consolidate predicate definitions into top level entry point for PowerPC target `PPC.td` and remove duplicate definitions for 32/64 bit sub-target checks.
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+66
-71
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7 files changed

+66
-71
lines changed

‎llvm/lib/Target/PowerPC/PPC.td‎

Lines changed: 33 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -360,8 +360,11 @@ def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
360360

361361
//===----------------------------------------------------------------------===//
362362
// PowerPC Instruction Predicate Definitions.
363-
def In32BitMode : Predicate<"!Subtarget->isPPC64()">;
364-
def In64BitMode : Predicate<"Subtarget->isPPC64()">;
363+
364+
def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
365+
def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
366+
def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
367+
def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
365368
def IsBookE : Predicate<"Subtarget->isBookE()">;
366369
def IsNotBookE : Predicate<"!Subtarget->isBookE()">;
367370
def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
@@ -379,27 +382,50 @@ def NaNsFPMath
379382
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
380383
def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
381384
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
385+
def HasFPU : Predicate<"Subtarget->hasFPU()">;
386+
def HasHTM : Predicate<"Subtarget->hasHTM()">;
387+
def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
388+
def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;
389+
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
390+
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
391+
def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
392+
def MMA : Predicate<"Subtarget->hasMMA()">;
393+
394+
// Vector support predicates
395+
def HasVSX : Predicate<"Subtarget->hasVSX()">;
396+
def NoP8Vector : Predicate<"!Subtarget->hasP8Vector()">;
397+
def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
398+
def HasAltivec : Predicate<"Subtarget->hasAltivec()">;
399+
def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;
400+
def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
401+
def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
402+
def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
403+
def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;
404+
def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
405+
def NoP10Vector : Predicate<"!Subtarget->hasP10Vector()">;
406+
def HasP10Vector : Predicate<"Subtarget->hasP10Vector()">;
407+
408+
// Predicates used to differenciate between different ISAs.
382409
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
383410
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
384411
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
385-
def HasFPU : Predicate<"Subtarget->hasFPU()">;
386-
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
412+
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
387413
def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;
414+
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
415+
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
388416

389417
// AIX assembler may not be modern enough to support some extended mne.
390418
def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,
391419
AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
392420
def IsAIX : Predicate<"Subtarget->isAIXABI()">;
393421
def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
394-
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
395-
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
396422

397423
//===----------------------------------------------------------------------===//
398424
// HwModes
399425
//===----------------------------------------------------------------------===//
400426

401427
defvar PPC32 = DefaultMode;
402-
def PPC64 : HwMode<[In64BitMode]>;
428+
def PPC64 : HwMode<[IsPPC64]>;
403429

404430
// Since new processors generally contain a superset of features of those that
405431
// came before them, the idea is to make implementations of new processors

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -76,23 +76,23 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
7676
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
7777
let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in
7878
def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
79-
[(PPCretglue)]>, Requires<[In64BitMode]>;
79+
[(PPCretglue)]>, Requires<[IsPPC64]>;
8080
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
8181
let isPredicable = 1 in
8282
def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
8383
[]>,
84-
Requires<[In64BitMode]>;
84+
Requires<[IsPPC64]>;
8585
def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),
8686
"b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
8787
[]>,
88-
Requires<[In64BitMode]>;
88+
Requires<[IsPPC64]>;
8989

9090
def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
9191
"bcctr 12, $BI, 0", IIC_BrB, []>,
92-
Requires<[In64BitMode]>;
92+
Requires<[IsPPC64]>;
9393
def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
9494
"bcctr 4, $BI, 0", IIC_BrB, []>,
95-
Requires<[In64BitMode]>;
95+
Requires<[IsPPC64]>;
9696
}
9797
}
9898

@@ -160,20 +160,20 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
160160
let isPredicable = 1 in
161161
def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
162162
"bctrl", IIC_BrB, [(PPCbctrl)]>,
163-
Requires<[In64BitMode]>;
163+
Requires<[IsPPC64]>;
164164

165165
let isCodeGenOnly = 1 in {
166166
def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
167167
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
168168
[]>,
169-
Requires<[In64BitMode]>;
169+
Requires<[IsPPC64]>;
170170

171171
def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),
172172
"bcctrl 12, $BI, 0", IIC_BrB, []>,
173-
Requires<[In64BitMode]>;
173+
Requires<[IsPPC64]>;
174174
def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),
175175
"bcctrl 4, $BI, 0", IIC_BrB, []>,
176-
Requires<[In64BitMode]>;
176+
Requires<[IsPPC64]>;
177177
}
178178
}
179179
}
@@ -207,7 +207,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0,
207207
let isPredicable = 1 in
208208
def BCTRL8_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
209209
"bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
210-
Requires<[In64BitMode]>;
210+
Requires<[IsPPC64]>;
211211
}
212212
}
213213

@@ -218,7 +218,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
218218
(ins (memrix $D, $RA):$src),
219219
"bctrl\n\tld 2, $src", IIC_BrB,
220220
[(PPCbctrl_load_toc iaddrX4:$src)]>,
221-
Requires<[In64BitMode]>;
221+
Requires<[IsPPC64]>;
222222
}
223223

224224
let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
@@ -228,7 +228,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
228228
(ins (memrix $D, $RA):$src),
229229
"bctrl\n\tld 2, $src", IIC_BrB,
230230
[(PPCbctrl_load_toc_rm iaddrX4:$src)]>,
231-
Requires<[In64BitMode]>;
231+
Requires<[IsPPC64]>;
232232
}
233233

234234
} // Interpretation64Bit
@@ -449,7 +449,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
449449
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
450450
def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
451451
[]>,
452-
Requires<[In64BitMode]>;
452+
Requires<[IsPPC64]>;
453453

454454
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
455455
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
@@ -516,15 +516,15 @@ let hasSideEffects = 1 in {
516516
def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
517517
"#EH_SJLJ_SETJMP64",
518518
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
519-
Requires<[In64BitMode]>;
519+
Requires<[IsPPC64]>;
520520
}
521521

522522
let hasSideEffects = 1, isBarrier = 1 in {
523523
let isTerminator = 1 in
524524
def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
525525
"#EH_SJLJ_LONGJMP64",
526526
[(PPCeh_sjlj_longjmp addr:$buf)]>,
527-
Requires<[In64BitMode]>;
527+
Requires<[IsPPC64]>;
528528
}
529529

530530
def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR),
@@ -1948,7 +1948,7 @@ def : Pat<(atomic_load_nonext_64 XForm:$src), (LDX memrr:$src)>;
19481948
def : Pat<(atomic_store_64 i64:$val, DSForm:$ptr), (STD g8rc:$val, memrix:$ptr)>;
19491949
def : Pat<(atomic_store_64 i64:$val, XForm:$ptr), (STDX g8rc:$val, memrr:$ptr)>;
19501950

1951-
let Predicates = [IsISA3_0, In64BitMode] in {
1951+
let Predicates = [IsISA3_0, IsPPC64] in {
19521952
def : Pat<(i64 (int_ppc_cmpeqb g8rc:$a, g8rc:$b)),
19531953
(i64 (SETB8 (CMPEQB $a, $b)))>;
19541954
def : Pat<(i64 (int_ppc_setb g8rc:$a, g8rc:$b)),
@@ -1961,7 +1961,7 @@ def : Pat<(i64 (int_ppc_maddld g8rc:$a, g8rc:$b, g8rc:$c)),
19611961
(i64 (MADDLD8 $a, $b, $c))>;
19621962
}
19631963

1964-
let Predicates = [In64BitMode] in {
1964+
let Predicates = [IsPPC64] in {
19651965
def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)),
19661966
(i64 (MULHD $a, $b))>;
19671967
def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)),

‎llvm/lib/Target/PowerPC/PPCInstrAltivec.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -343,7 +343,6 @@ class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
343343
//===----------------------------------------------------------------------===//
344344
// Instruction Definitions.
345345

346-
def HasAltivec : Predicate<"Subtarget->hasAltivec()">;
347346
let Predicates = [HasAltivec] in {
348347

349348
def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
@@ -1193,8 +1192,6 @@ class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
11931192
let PS = 0;
11941193
}
11951194

1196-
def HasP8Altivec : Predicate<"Subtarget->hasP8Altivec()">;
1197-
def HasP8Crypto : Predicate<"Subtarget->hasP8Crypto()">;
11981195
let Predicates = [HasP8Altivec] in {
11991196

12001197
let isCommutable = 1 in {
@@ -1420,7 +1417,6 @@ def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
14201417
} // HasP8Crypto
14211418

14221419
// The following altivec instructions were introduced in Power ISA 3.0
1423-
def HasP9Altivec : Predicate<"Subtarget->hasP9Altivec()">;
14241420
let Predicates = [HasP9Altivec] in {
14251421

14261422
// Vector Multiply-Sum

‎llvm/lib/Target/PowerPC/PPCInstrHTM.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,6 @@
1111
//
1212
//===----------------------------------------------------------------------===//
1313

14-
15-
16-
def HasHTM : Predicate<"Subtarget->hasHTM()">;
17-
1814
def HTM_get_imm : SDNodeXForm<imm, [{
1915
return getI32Imm (N->getZExtValue(), SDLoc(N));
2016
}]>;

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td‎

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1282,7 +1282,7 @@ def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F),
12821282
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
12831283
let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in
12841284
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1285-
[(PPCretglue)]>, Requires<[In32BitMode]>;
1285+
[(PPCretglue)]>, Requires<[IsPPC32]>;
12861286
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
12871287
let isPredicable = 1 in
12881288
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
@@ -1455,7 +1455,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
14551455
let isPredicable = 1 in
14561456
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
14571457
"bctrl", IIC_BrB, [(PPCbctrl)]>,
1458-
Requires<[In32BitMode]>;
1458+
Requires<[IsPPC32]>;
14591459

14601460
let isCodeGenOnly = 1 in {
14611461
def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond),
@@ -1541,7 +1541,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in {
15411541
let isPredicable = 1 in
15421542
def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
15431543
"bctrl", IIC_BrB, [(PPCbctrl_rm)]>,
1544-
Requires<[In32BitMode]>;
1544+
Requires<[IsPPC32]>;
15451545
}
15461546
}
15471547

@@ -1567,7 +1567,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
15671567
def BCTRL_LWZinto_toc:
15681568
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
15691569
(ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
1570-
[(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>;
1570+
[(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[IsPPC32]>;
15711571

15721572
}
15731573

@@ -1576,7 +1576,7 @@ let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
15761576
def BCTRL_LWZinto_toc_RM:
15771577
XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs),
15781578
(ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
1579-
[(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>;
1579+
[(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[IsPPC32]>;
15801580

15811581
}
15821582

@@ -1585,7 +1585,7 @@ let isCodeGenOnly = 1, hasSideEffects = 0 in {
15851585
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
15861586
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
15871587
def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1588-
[]>, Requires<[In32BitMode]>;
1588+
[]>, Requires<[IsPPC32]>;
15891589

15901590
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
15911591
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
@@ -1608,15 +1608,15 @@ let hasSideEffects = 1 in {
16081608
def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf),
16091609
"#EH_SJLJ_SETJMP32",
16101610
[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1611-
Requires<[In32BitMode]>;
1611+
Requires<[IsPPC32]>;
16121612
}
16131613

16141614
let hasSideEffects = 1, isBarrier = 1 in {
16151615
let isTerminator = 1 in
16161616
def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf),
16171617
"#EH_SJLJ_LONGJMP32",
16181618
[(PPCeh_sjlj_longjmp addr:$buf)]>,
1619-
Requires<[In32BitMode]>;
1619+
Requires<[IsPPC32]>;
16201620
}
16211621

16221622
// This pseudo is never removed from the function, as it serves as
@@ -3438,8 +3438,6 @@ def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>;
34383438
def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>;
34393439
def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>;
34403440

3441-
def MMA : Predicate<"Subtarget->hasMMA()">;
3442-
34433441
// Prefixed instructions may require access to the above defs at a later
34443442
// time so we include this after the def.
34453443
include "PPCInstrP10.td"
@@ -5144,9 +5142,9 @@ def RotateInsertByte1 {
51445142
}
51455143

51465144
// Clear the upper half of the register when in 64-bit mode
5147-
let Predicates = [In64BitMode] in
5145+
let Predicates = [IsPPC64] in
51485146
def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
5149-
let Predicates = [In32BitMode] in
5147+
let Predicates = [IsPPC32] in
51505148
def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>;
51515149

51525150
// Fast 64-bit reverse bits algorithm:

‎llvm/lib/Target/PowerPC/PPCInstrP10.td‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,6 @@
5151
// Moreover, the order of operands reflects the order of operands
5252
// in the encoding.
5353

54-
//-------------------------- Predicate definitions ---------------------------//
55-
def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
56-
57-
5854
//===----------------------------------------------------------------------===//
5955
// PowerPC ISA 3.1 specific type constraints.
6056
//
@@ -634,9 +630,6 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
634630
}
635631
}
636632

637-
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
638-
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
639-
def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
640633
def RCCp {
641634
dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
642635
dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);

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