Skip to content

Commit ab98b98

Browse files
toppercmahesh-attarde
topperc
authored and
mahesh-attarde
committed
[RISCV] Merge some of the C_*_HINT instruction into the regular C_* instructions. (llvm#150710)
Register classes and immediate predicates in a CompressPat no longer need to match the compressed instruction. We can now merge most of the C_*_HINT instructions into their non-HINT equivalents. I've left c.slli64/srli64/srai6 out to avoid conflict with llvm#150689. C_NOP_HINT is left out because the spec refers to C_NOP as a separate instruction from C_ADDI. C_NOP does not allow an immediate operand but C_NOP_HINT does.
1 parent 7d272b5 commit ab98b98

File tree

6 files changed

+33
-174
lines changed

6 files changed

+33
-174
lines changed

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 6 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -193,21 +193,19 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
193193
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
194194
uint64_t Address,
195195
const MCDisassembler *Decoder) {
196-
if (RegNo == 0) {
196+
if (RegNo == 0)
197197
return MCDisassembler::Fail;
198-
}
199198

200199
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
201200
}
202201

203-
static DecodeStatus
204-
DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
205-
const MCDisassembler *Decoder) {
206-
if (RegNo == 2) {
202+
static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo,
203+
uint32_t Address,
204+
const MCDisassembler *Decoder) {
205+
if (RegNo == 2)
207206
return MCDisassembler::Fail;
208-
}
209207

210-
return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
208+
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
211209
}
212210

213211
static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo,
@@ -536,31 +534,6 @@ static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
536534
return MCDisassembler::Success;
537535
}
538536

539-
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
540-
uint64_t Address,
541-
const MCDisassembler *Decoder);
542-
543-
static DecodeStatus decodeRVCInstrRdSImm6(MCInst &Inst, uint32_t Insn,
544-
uint64_t Address,
545-
const MCDisassembler *Decoder);
546-
547-
static DecodeStatus decodeRVCInstrRdCLUIImm(MCInst &Inst, uint32_t Insn,
548-
uint64_t Address,
549-
const MCDisassembler *Decoder);
550-
551-
static DecodeStatus
552-
decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst &Inst, uint32_t Insn,
553-
uint64_t Address,
554-
const MCDisassembler *Decoder);
555-
556-
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
557-
uint64_t Address,
558-
const MCDisassembler *Decoder);
559-
560-
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
561-
uint64_t Address,
562-
const MCDisassembler *Decoder);
563-
564537
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
565538
uint64_t Address,
566539
const MCDisassembler *Decoder);
@@ -579,18 +552,6 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
579552

580553
#include "RISCVGenDisassemblerTables.inc"
581554

582-
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
583-
uint64_t Address,
584-
const MCDisassembler *Decoder) {
585-
DecodeStatus S = MCDisassembler::Success;
586-
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
587-
if (!Check(S, DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder)))
588-
return MCDisassembler::Fail;
589-
Inst.addOperand(Inst.getOperand(0));
590-
Inst.addOperand(MCOperand::createImm(0));
591-
return S;
592-
}
593-
594555
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
595556
uint64_t Address,
596557
const MCDisassembler *Decoder) {
@@ -601,66 +562,6 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
601562
return MCDisassembler::Success;
602563
}
603564

604-
static DecodeStatus decodeRVCInstrRdSImm6(MCInst &Inst, uint32_t Insn,
605-
uint64_t Address,
606-
const MCDisassembler *Decoder) {
607-
Inst.addOperand(MCOperand::createReg(RISCV::X0));
608-
uint32_t Imm =
609-
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
610-
[[maybe_unused]] DecodeStatus Result =
611-
decodeSImmOperand<6>(Inst, Imm, Address, Decoder);
612-
assert(Result == MCDisassembler::Success && "Invalid immediate");
613-
return MCDisassembler::Success;
614-
}
615-
616-
static DecodeStatus decodeRVCInstrRdCLUIImm(MCInst &Inst, uint32_t Insn,
617-
uint64_t Address,
618-
const MCDisassembler *Decoder) {
619-
Inst.addOperand(MCOperand::createReg(RISCV::X0));
620-
uint32_t Imm =
621-
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
622-
return decodeCLUIImmOperand(Inst, Imm, Address, Decoder);
623-
}
624-
625-
static DecodeStatus
626-
decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst &Inst, uint32_t Insn,
627-
uint64_t Address,
628-
const MCDisassembler *Decoder) {
629-
Inst.addOperand(MCOperand::createReg(RISCV::X0));
630-
Inst.addOperand(Inst.getOperand(0));
631-
632-
uint32_t UImm6 =
633-
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
634-
return decodeUImmLog2XLenNonZeroOperand(Inst, UImm6, Address, Decoder);
635-
}
636-
637-
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
638-
uint64_t Address,
639-
const MCDisassembler *Decoder) {
640-
DecodeStatus S = MCDisassembler::Success;
641-
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
642-
uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
643-
if (!Check(S, DecodeGPRRegisterClass(Inst, Rd, Address, Decoder)))
644-
return MCDisassembler::Fail;
645-
if (!Check(S, DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder)))
646-
return MCDisassembler::Fail;
647-
return S;
648-
}
649-
650-
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
651-
uint64_t Address,
652-
const MCDisassembler *Decoder) {
653-
DecodeStatus S = MCDisassembler::Success;
654-
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
655-
uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
656-
if (!Check(S, DecodeGPRRegisterClass(Inst, Rd, Address, Decoder)))
657-
return MCDisassembler::Fail;
658-
Inst.addOperand(Inst.getOperand(0));
659-
if (!Check(S, DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder)))
660-
return MCDisassembler::Fail;
661-
return S;
662-
}
663-
664565
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
665566
uint64_t Address,
666567
const MCDisassembler *Decoder) {

‎llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -293,7 +293,7 @@ void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
293293

294294
MCInst Hint;
295295
if (STI->hasStdExtZca())
296-
Hint.setOpcode(RISCV::C_ADD_HINT);
296+
Hint.setOpcode(RISCV::C_ADD);
297297
else
298298
Hint.setOpcode(RISCV::ADD);
299299

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Lines changed: 12 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -402,7 +402,7 @@ def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,
402402

403403
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
404404
def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
405-
(ins GPRNoX0:$rd, simm6nonzero:$imm),
405+
(ins GPRNoX0:$rd, simm6:$imm),
406406
"c.addi", "$rd, $imm">,
407407
Sched<[WriteIALU, ReadIALU]> {
408408
let Constraints = "$rd = $rd_wb";
@@ -430,7 +430,7 @@ def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
430430
}
431431

432432
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
433-
def C_LI : RVInst16CI<0b010, 0b01, (outs GPRNoX0:$rd), (ins simm6:$imm),
433+
def C_LI : RVInst16CI<0b010, 0b01, (outs GPR:$rd), (ins simm6:$imm),
434434
"c.li", "$rd, $imm">,
435435
Sched<[WriteIALU]>;
436436

@@ -449,7 +449,7 @@ def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
449449
}
450450

451451
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
452-
def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd),
452+
def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX2:$rd),
453453
(ins c_lui_imm:$imm),
454454
"c.lui", "$rd, $imm">,
455455
Sched<[WriteIALU]>;
@@ -497,8 +497,8 @@ def C_BEQZ : Bcz<0b110, "c.beqz">, Sched<[WriteJmp, ReadJmp]>;
497497
def C_BNEZ : Bcz<0b111, "c.bnez">, Sched<[WriteJmp, ReadJmp]>;
498498

499499
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
500-
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
501-
(ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
500+
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb),
501+
(ins GPR:$rd, uimmlog2xlennonzero:$imm),
502502
"c.slli", "$rd, $imm">,
503503
Sched<[WriteShiftImm, ReadShiftImm]> {
504504
let Constraints = "$rd = $rd_wb";
@@ -544,7 +544,7 @@ def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
544544

545545
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
546546
isAsCheapAsAMove = 1 in
547-
def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
547+
def C_MV : RVInst16CR<0b1000, 0b10, (outs GPR:$rs1), (ins GPRNoX0:$rs2),
548548
"c.mv", "$rs1, $rs2">,
549549
Sched<[WriteIALU, ReadIALU]>;
550550

@@ -557,8 +557,8 @@ def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
557557
"c.jalr", "$rs1">, Sched<[WriteJalr, ReadJalr]>;
558558

559559
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
560-
def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rd),
561-
(ins GPRNoX0:$rs1, GPRNoX0:$rs2),
560+
def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPR:$rd),
561+
(ins GPR:$rs1, GPRNoX0:$rs2),
562562
"c.add", "$rs1, $rs2">,
563563
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
564564
let Constraints = "$rs1 = $rd";
@@ -616,54 +616,6 @@ def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
616616
let rd = 0;
617617
}
618618

619-
def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
620-
(ins GPRNoX0:$rd, immzero:$imm),
621-
"c.addi", "$rd, $imm">,
622-
Sched<[WriteIALU, ReadIALU]> {
623-
let Constraints = "$rd = $rd_wb";
624-
let imm = 0;
625-
let DecoderMethod = "decodeRVCInstrRdRs1ImmZero";
626-
}
627-
628-
def C_LI_HINT : RVInst16CI<0b010, 0b01, (outs GPRX0:$rd), (ins simm6:$imm),
629-
"c.li", "$rd, $imm">,
630-
Sched<[WriteIALU]> {
631-
let Inst{11-7} = 0;
632-
let DecoderMethod = "decodeRVCInstrRdSImm6";
633-
}
634-
635-
def C_LUI_HINT : RVInst16CI<0b011, 0b01, (outs GPRX0:$rd),
636-
(ins c_lui_imm:$imm),
637-
"c.lui", "$rd, $imm">,
638-
Sched<[WriteIALU]> {
639-
let Inst{11-7} = 0;
640-
let DecoderMethod = "decodeRVCInstrRdCLUIImm";
641-
}
642-
643-
def C_MV_HINT : RVInst16CR<0b1000, 0b10, (outs GPRX0:$rs1), (ins GPRNoX0:$rs2),
644-
"c.mv", "$rs1, $rs2">, Sched<[WriteIALU, ReadIALU]> {
645-
let Inst{11-7} = 0;
646-
let DecoderMethod = "decodeRVCInstrRdRs2";
647-
}
648-
649-
def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rd),
650-
(ins GPRX0:$rs1, GPRNoX0:$rs2),
651-
"c.add", "$rs1, $rs2">,
652-
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
653-
let Constraints = "$rs1 = $rd";
654-
let Inst{11-7} = 0;
655-
let DecoderMethod = "decodeRVCInstrRdRs1Rs2";
656-
}
657-
658-
def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
659-
(ins GPRX0:$rd, uimmlog2xlennonzero:$imm),
660-
"c.slli", "$rd, $imm">,
661-
Sched<[WriteShiftImm, ReadShiftImm]> {
662-
let Constraints = "$rd = $rd_wb";
663-
let Inst{11-7} = 0;
664-
let DecoderMethod = "decodeRVCInstrRdRs1UImmLog2XLenNonZero";
665-
}
666-
667619
def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
668620
"c.slli64", "$rd">,
669621
Sched<[WriteShiftImm, ReadShiftImm]> {
@@ -704,10 +656,10 @@ def : InstAlias<"c.addi x0, $imm", (C_NOP_HINT simm6nonzero:$imm), 0>;
704656
}
705657

706658
let Predicates = [HasStdExtC, HasStdExtZihintntl] in {
707-
def : InstAlias<"c.ntl.p1", (C_ADD_HINT X0, X2)>;
708-
def : InstAlias<"c.ntl.pall", (C_ADD_HINT X0, X3)>;
709-
def : InstAlias<"c.ntl.s1", (C_ADD_HINT X0, X4)>;
710-
def : InstAlias<"c.ntl.all", (C_ADD_HINT X0, X5)>;
659+
def : InstAlias<"c.ntl.p1", (C_ADD X0, X2)>;
660+
def : InstAlias<"c.ntl.pall", (C_ADD X0, X3)>;
661+
def : InstAlias<"c.ntl.s1", (C_ADD X0, X4)>;
662+
def : InstAlias<"c.ntl.all", (C_ADD X0, X5)>;
711663
} // Predicates = [HasStdExtC, HasStdExtZihintntl]
712664

713665
let EmitPriority = 0 in {

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -268,6 +268,11 @@ def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)> {
268268
let DiagnosticString = "register must be a GPR excluding zero (x0)";
269269
}
270270

271+
def GPRNoX2 : GPRRegisterClass<(sub GPR, X2)> {
272+
let DiagnosticType = "InvalidRegClassGPRNoX2";
273+
let DiagnosticString = "register must be a GPR excluding sp (x2)";
274+
}
275+
271276
def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)> {
272277
let DiagnosticType = "InvalidRegClassGPRNoX0X2";
273278
let DiagnosticString = "register must be a GPR excluding zero (x0) and sp (x2)";

‎llvm/test/MC/RISCV/rv32c-invalid.s

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -26,8 +26,8 @@ c.jalr zero # CHECK: :[[@LINE]]:9: error: register must be a GPR excluding zero
2626
c.mv ra, x0 # CHECK: :[[@LINE]]:11: error: register must be a GPR excluding zero (x0)
2727
c.add ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
2828

29-
## GPRNoX0X2
30-
c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding zero (x0) and sp (x2){{$}}
29+
## GPRNoX2
30+
c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: register must be a GPR excluding sp (x2){{$}}
3131

3232
## SP
3333
c.addi4spn a0, a0, 12 # CHECK: :[[@LINE]]:17: error: register must be sp (x2)
@@ -49,13 +49,14 @@ c.andi a0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in th
4949
c.andi a0, foo # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
5050
c.andi a0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
5151
c.andi a0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
52+
c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
53+
c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
54+
c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
55+
c.addi t0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
56+
c.addi t0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
5257

5358
## simm6nonzero
54-
c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
55-
c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
56-
c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
57-
c.addi t0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
58-
c.addi t0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
59+
c.nop 32 # CHECK: :[[@LINE]]:7: error: immediate must be non-zero in the range [-32, 31]
5960

6061
## c_lui_imm
6162
c.lui t0, 0 # CHECK: :[[@LINE]]:11: error: immediate must be in [0xfffe0, 0xfffff] or [1, 31]

‎llvm/test/MC/RISCV/rve-invalid.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ auipc t6, 32
115115
# CHECK: :[[@LINE+1]]:8: error: register must be a GPR excluding zero (x0)
116116
c.addi x31, 0
117117
# CHECK-DIS: 9846 <unknown>
118-
# CHECK: :[[@LINE+1]]:7: error: register must be a GPR excluding zero (x0)
118+
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction
119119
c.add x16, x17
120120
# CHECK-DIS: 8046 <unknown>
121121
# CHECK: :[[@LINE+1]]:10: error: register must be a GPR excluding zero (x0)

0 commit comments

Comments
 (0)