@@ -52,15 +52,6 @@ namespace RISCV {
5252#include " RISCVGenSearchableTables.inc"
5353} // namespace RISCV
5454
55- // Report an error but don't ask the user to report a bug.
56- // TODO: Remove these wrappers.
57- [[noreturn]] static void reportError (const char *Reason) {
58- reportFatalUsageError (Reason);
59- }
60- [[noreturn]] static void reportError (Error Err) {
61- reportFatalUsageError (std::move (Err));
62- }
63-
6455namespace RISCVABI {
6556ABI computeTargetABI (const Triple &TT, const FeatureBitset &FeatureBits,
6657 StringRef ABIName) {
@@ -97,15 +88,15 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
9788 if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
9889 (TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
9990 FeatureBits[RISCV::FeatureStdExtD])
100- reportError (" ILP32E cannot be used with the D ISA extension" );
91+ reportFatalUsageError (" ILP32E cannot be used with the D ISA extension" );
10192
10293 if (TargetABI != ABI_Unknown)
10394 return TargetABI;
10495
10596 // If no explicit ABI is given, try to compute the default ABI.
10697 auto ISAInfo = RISCVFeatures::parseFeatureBits (IsRV64, FeatureBits);
10798 if (!ISAInfo)
108- reportError (ISAInfo.takeError ());
99+ reportFatalUsageError (ISAInfo.takeError ());
109100 return getTargetABI ((*ISAInfo)->computeDefaultABI ());
110101}
111102
@@ -137,12 +128,12 @@ namespace RISCVFeatures {
137128
138129void validate (const Triple &TT, const FeatureBitset &FeatureBits) {
139130 if (TT.isArch64Bit () && !FeatureBits[RISCV::Feature64Bit])
140- reportError (" RV64 target requires an RV64 CPU" );
131+ reportFatalUsageError (" RV64 target requires an RV64 CPU" );
141132 if (!TT.isArch64Bit () && !FeatureBits[RISCV::Feature32Bit])
142- reportError (" RV32 target requires an RV32 CPU" );
133+ reportFatalUsageError (" RV32 target requires an RV32 CPU" );
143134 if (FeatureBits[RISCV::Feature32Bit] &&
144135 FeatureBits[RISCV::Feature64Bit])
145- reportError (" RV32 and RV64 can't be combined" );
136+ reportFatalUsageError (" RV32 and RV64 can't be combined" );
146137}
147138
148139llvm::Expected<std::unique_ptr<RISCVISAInfo>>
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