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1 parent 7018877 commit c4b8d3bCopy full SHA for c4b8d3b
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -3808,6 +3808,7 @@ class AMDGPUCooperativeAtomicLoad<LLVMType Ty> : Intrinsic <
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[SDNPMemOperand, SDNPMayLoad]
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>;
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+// TODO: We may want to drop _relaxed and use an atomic ordering operand instead.
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def int_amdgcn_cooperative_atomic_load_32x4B : AMDGPUCooperativeAtomicLoad<llvm_i32_ty>;
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def int_amdgcn_cooperative_atomic_store_32x4B : AMDGPUCooperativeAtomicStore<llvm_i32_ty>;
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def int_amdgcn_cooperative_atomic_load_16x8B : AMDGPUCooperativeAtomicLoad<llvm_v2i32_ty>;
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