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AMDGPU: Support V_PK_MAXIMUM3_F16 and V_PK_MINIMUM3_F16 on gfx1250 (llvm#150307)
Co-authored-by: Stanislav Mekhanoshin <[email protected]>
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‎llvm/lib/Target/AMDGPU/VOP3PInstructions.td‎

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Original file line numberDiff line numberDiff line change
@@ -2235,6 +2235,8 @@ defm V_PK_ADD_BF16 : VOP3P_Real_gfx1250<0x23>;
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defm V_PK_MUL_BF16 : VOP3P_Real_gfx1250<0x2a>;
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defm V_PK_MIN_NUM_BF16 : VOP3P_Real_gfx1250<0x2b>;
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defm V_PK_MAX_NUM_BF16 : VOP3P_Real_gfx1250<0x2c>;
2238+
defm V_PK_MINIMUM3_F16 : VOP3P_Real_gfx1250<0x36>;
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defm V_PK_MAXIMUM3_F16 : VOP3P_Real_gfx1250<0x37>;
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defm V_PK_MINIMUM_F16 : VOP3P_Real_gfx12<0x1d>;
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defm V_PK_MAXIMUM_F16 : VOP3P_Real_gfx12<0x1e>;

‎llvm/test/CodeGen/AMDGPU/fmaximum3.v2f16.ll‎

Lines changed: 99 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-SDAG %s
3+
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-GISEL %s
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define <2 x half> @fmaximum3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
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; GFX1250-SDAG-LABEL: fmaximum3_v2f16:
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; GFX1250-SDAG: ; %bb.0: ; %entry
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
9+
; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: v_pk_maximum3_f16 v0, v2, v0, v1
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; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: fmaximum3_v2f16:
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; GFX1250-GISEL: ; %bb.0: ; %entry
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v0, v0, v1, v1
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v0, v2, v0, v0
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%min = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
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%res = call <2 x half> @llvm.maximum.v2f16(<2 x half> %c, <2 x half> %min)
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ret <2 x half> %res
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}
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define <2 x half> @fmaximum3_v2f16_vss(<2 x half> %a, <2 x half> inreg %b, <2 x half> inreg %c) {
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; GFX1250-SDAG-LABEL: fmaximum3_v2f16_vss:
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; GFX1250-SDAG: ; %bb.0: ; %entry
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: v_pk_maximum3_f16 v0, s1, v0, s0
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; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: fmaximum3_v2f16_vss:
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; GFX1250-GISEL: ; %bb.0: ; %entry
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v0, v0, s0, s0
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v0, s1, v0, v0
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%min = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b)
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%res = call <2 x half> @llvm.maximum.v2f16(<2 x half> %c, <2 x half> %min)
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ret <2 x half> %res
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}
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define <3 x half> @fmaximum3_v3f16(<3 x half> %a, <3 x half> %b, <3 x half> %c) {
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; GFX1250-SDAG-LABEL: fmaximum3_v3f16:
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; GFX1250-SDAG: ; %bb.0: ; %entry
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: v_pk_maximum3_f16 v0, v4, v0, v2
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; GFX1250-SDAG-NEXT: v_pk_maximum3_f16 v1, v5, v1, v3
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; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: fmaximum3_v3f16:
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; GFX1250-GISEL: ; %bb.0: ; %entry
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v0, v0, v2, v2
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; GFX1250-GISEL-NEXT: v_maximum_f16 v1, v1, v3
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v0, v4, v0, v0
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; GFX1250-GISEL-NEXT: v_maximum_f16 v1, v5, v1
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%min = call <3 x half> @llvm.maximum.v3f16(<3 x half> %a, <3 x half> %b)
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%res = call <3 x half> @llvm.maximum.v3f16(<3 x half> %c, <3 x half> %min)
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ret <3 x half> %res
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}
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define <4 x half> @fmaximum3_v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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; GFX1250-SDAG-LABEL: fmaximum3_v4f16:
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; GFX1250-SDAG: ; %bb.0: ; %entry
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: v_pk_maximum3_f16 v0, v4, v0, v2
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; GFX1250-SDAG-NEXT: v_pk_maximum3_f16 v1, v5, v1, v3
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; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: fmaximum3_v4f16:
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; GFX1250-GISEL: ; %bb.0: ; %entry
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v0, v0, v2, v2
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v1, v1, v3, v3
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v0, v4, v0, v0
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; GFX1250-GISEL-NEXT: v_pk_maximum3_f16 v1, v5, v1, v1
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%min = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b)
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%res = call <4 x half> @llvm.maximum.v4f16(<4 x half> %c, <4 x half> %min)
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ret <4 x half> %res
97+
}
98+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GFX1250: {{.*}}

‎llvm/test/CodeGen/AMDGPU/fminimum3.v2f16.ll‎

Lines changed: 99 additions & 0 deletions
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@@ -0,0 +1,99 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-GISEL %s
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define <2 x half> @fminimum3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c) {
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; GFX1250-SDAG-LABEL: fminimum3_v2f16:
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; GFX1250-SDAG: ; %bb.0: ; %entry
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: v_pk_minimum3_f16 v0, v2, v0, v1
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; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: fminimum3_v2f16:
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; GFX1250-GISEL: ; %bb.0: ; %entry
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v0, v0, v1, v1
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v0, v2, v0, v0
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%min = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)
23+
%res = call <2 x half> @llvm.minimum.v2f16(<2 x half> %c, <2 x half> %min)
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ret <2 x half> %res
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}
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define <2 x half> @fminimum3_v2f16_vss(<2 x half> %a, <2 x half> inreg %b, <2 x half> inreg %c) {
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; GFX1250-SDAG-LABEL: fminimum3_v2f16_vss:
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; GFX1250-SDAG: ; %bb.0: ; %entry
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: v_pk_minimum3_f16 v0, s1, v0, s0
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; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: fminimum3_v2f16_vss:
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; GFX1250-GISEL: ; %bb.0: ; %entry
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v0, v0, s0, s0
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v0, s1, v0, v0
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%min = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b)
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%res = call <2 x half> @llvm.minimum.v2f16(<2 x half> %c, <2 x half> %min)
46+
ret <2 x half> %res
47+
}
48+
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define <3 x half> @fminimum3_v3f16(<3 x half> %a, <3 x half> %b, <3 x half> %c) {
50+
; GFX1250-SDAG-LABEL: fminimum3_v3f16:
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; GFX1250-SDAG: ; %bb.0: ; %entry
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: v_pk_minimum3_f16 v0, v4, v0, v2
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; GFX1250-SDAG-NEXT: v_pk_minimum3_f16 v1, v5, v1, v3
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; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
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;
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; GFX1250-GISEL-LABEL: fminimum3_v3f16:
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; GFX1250-GISEL: ; %bb.0: ; %entry
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v0, v0, v2, v2
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; GFX1250-GISEL-NEXT: v_minimum_f16 v1, v1, v3
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v0, v4, v0, v0
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; GFX1250-GISEL-NEXT: v_minimum_f16 v1, v5, v1
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%min = call <3 x half> @llvm.minimum.v3f16(<3 x half> %a, <3 x half> %b)
70+
%res = call <3 x half> @llvm.minimum.v3f16(<3 x half> %c, <3 x half> %min)
71+
ret <3 x half> %res
72+
}
73+
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define <4 x half> @fminimum3_v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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; GFX1250-SDAG-LABEL: fminimum3_v4f16:
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; GFX1250-SDAG: ; %bb.0: ; %entry
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; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX1250-SDAG-NEXT: v_pk_minimum3_f16 v0, v4, v0, v2
80+
; GFX1250-SDAG-NEXT: v_pk_minimum3_f16 v1, v5, v1, v3
81+
; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31]
82+
;
83+
; GFX1250-GISEL-LABEL: fminimum3_v4f16:
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; GFX1250-GISEL: ; %bb.0: ; %entry
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; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v0, v0, v2, v2
88+
; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v1, v1, v3, v3
89+
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v0, v4, v0, v0
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; GFX1250-GISEL-NEXT: v_pk_minimum3_f16 v1, v5, v1, v1
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; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%min = call <4 x half> @llvm.minimum.v4f16(<4 x half> %a, <4 x half> %b)
95+
%res = call <4 x half> @llvm.minimum.v4f16(<4 x half> %c, <4 x half> %min)
96+
ret <4 x half> %res
97+
}
98+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
99+
; GFX1250: {{.*}}

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop3p.s‎

Lines changed: 144 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1025,3 +1025,147 @@ v_pk_fma_bf16 v5, src_scc, vcc_lo, -1 op_sel:[0,1,0] op_sel_hi:[1,0,1] neg_lo:[0
10251025
v_pk_fma_bf16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[1,1,1] neg_hi:[1,1,1] clamp
10261026
// GFX1250: v_pk_fma_bf16 v255, 0xfe0b, vcc_hi, null op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[1,1,1] neg_hi:[1,1,1] clamp ; encoding: [0xff,0xa7,0x11,0xcc,0xff,0xd6,0xf0,0xf9,0x0b,0xfe,0x00,0x00]
10271027
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1028+
1029+
v_pk_minimum3_f16 v8, v1, s1, v4
1030+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 ; encoding: [0x08,0x40,0x36,0xcc,0x01,0x03,0x10,0x1c]
1031+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1032+
1033+
v_pk_minimum3_f16 v8, v1, s1, v4
1034+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 ; encoding: [0x08,0x40,0x36,0xcc,0x01,0x03,0x10,0x1c]
1035+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1036+
1037+
v_pk_minimum3_f16 v8, v1, s1, v4
1038+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 ; encoding: [0x08,0x40,0x36,0xcc,0x01,0x03,0x10,0x1c]
1039+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1040+
1041+
v_pk_minimum3_f16 v8, v1, s1, v4
1042+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 ; encoding: [0x08,0x40,0x36,0xcc,0x01,0x03,0x10,0x1c]
1043+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1044+
1045+
v_pk_minimum3_f16 v8, v1, s1, v4 op_sel_hi:[0,0,0]
1046+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 op_sel_hi:[0,0,0] ; encoding: [0x08,0x00,0x36,0xcc,0x01,0x03,0x10,0x04]
1047+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1048+
1049+
v_pk_minimum3_f16 v8, v1, s1, v4 op_sel:[0,0,1] op_sel_hi:[0,0,1]
1050+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; encoding: [0x08,0x60,0x36,0xcc,0x01,0x03,0x10,0x04]
1051+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1052+
1053+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[1,1,1]
1054+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[1,1,1] ; encoding: [0x08,0x40,0x36,0xcc,0x01,0x03,0x10,0xfc]
1055+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1056+
1057+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_hi:[1,1,1]
1058+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_hi:[1,1,1] ; encoding: [0x08,0x47,0x36,0xcc,0x01,0x03,0x10,0x1c]
1059+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1060+
1061+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[1,1,1] neg_hi:[1,1,1]
1062+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[1,1,1] neg_hi:[1,1,1] ; encoding: [0x08,0x47,0x36,0xcc,0x01,0x03,0x10,0xfc]
1063+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1064+
1065+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[1,0,0]
1066+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[1,0,0] ; encoding: [0x08,0x40,0x36,0xcc,0x01,0x03,0x10,0x3c]
1067+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1068+
1069+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[0,1,0]
1070+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[0,1,0] ; encoding: [0x08,0x40,0x36,0xcc,0x01,0x03,0x10,0x5c]
1071+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1072+
1073+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[0,0,1]
1074+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_lo:[0,0,1] ; encoding: [0x08,0x40,0x36,0xcc,0x01,0x03,0x10,0x9c]
1075+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1076+
1077+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_hi:[1,0,0]
1078+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_hi:[1,0,0] ; encoding: [0x08,0x41,0x36,0xcc,0x01,0x03,0x10,0x1c]
1079+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1080+
1081+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_hi:[0,1,0]
1082+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_hi:[0,1,0] ; encoding: [0x08,0x42,0x36,0xcc,0x01,0x03,0x10,0x1c]
1083+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1084+
1085+
v_pk_minimum3_f16 v8, v1, s1, v4 neg_hi:[0,0,1]
1086+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 neg_hi:[0,0,1] ; encoding: [0x08,0x44,0x36,0xcc,0x01,0x03,0x10,0x1c]
1087+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1088+
1089+
v_pk_minimum3_f16 v8, v1, s1, v4 clamp
1090+
// GFX1250: v_pk_minimum3_f16 v8, v1, s1, v4 clamp ; encoding: [0x08,0xc0,0x36,0xcc,0x01,0x03,0x10,0x1c]
1091+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1092+
1093+
v_pk_minimum3_f16 v1, v4, v9, v16
1094+
// GFX1250: v_pk_minimum3_f16 v1, v4, v9, v16 ; encoding: [0x01,0x40,0x36,0xcc,0x04,0x13,0x42,0x1c]
1095+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1096+
1097+
v_pk_minimum3_f16 v1, v2, v5, 1.0
1098+
// GFX1250: v_pk_minimum3_f16 v1, v2, v5, 1.0 ; encoding: [0x01,0x40,0x36,0xcc,0x02,0x0b,0xca,0x1b]
1099+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1100+
1101+
v_pk_maximum3_f16 v8, v1, s1, v4
1102+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 ; encoding: [0x08,0x40,0x37,0xcc,0x01,0x03,0x10,0x1c]
1103+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1104+
1105+
v_pk_maximum3_f16 v8, v1, s1, v4
1106+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 ; encoding: [0x08,0x40,0x37,0xcc,0x01,0x03,0x10,0x1c]
1107+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1108+
1109+
v_pk_maximum3_f16 v8, v1, s1, v4
1110+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 ; encoding: [0x08,0x40,0x37,0xcc,0x01,0x03,0x10,0x1c]
1111+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1112+
1113+
v_pk_maximum3_f16 v8, v1, s1, v4
1114+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 ; encoding: [0x08,0x40,0x37,0xcc,0x01,0x03,0x10,0x1c]
1115+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1116+
1117+
v_pk_maximum3_f16 v8, v1, s1, v4 op_sel_hi:[0,0,0]
1118+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 op_sel_hi:[0,0,0] ; encoding: [0x08,0x00,0x37,0xcc,0x01,0x03,0x10,0x04]
1119+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1120+
1121+
v_pk_maximum3_f16 v8, v1, s1, v4 op_sel:[0,0,1] op_sel_hi:[0,0,1]
1122+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 op_sel:[0,0,1] op_sel_hi:[0,0,1] ; encoding: [0x08,0x60,0x37,0xcc,0x01,0x03,0x10,0x04]
1123+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1124+
1125+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[1,1,1]
1126+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[1,1,1] ; encoding: [0x08,0x40,0x37,0xcc,0x01,0x03,0x10,0xfc]
1127+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1128+
1129+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_hi:[1,1,1]
1130+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_hi:[1,1,1] ; encoding: [0x08,0x47,0x37,0xcc,0x01,0x03,0x10,0x1c]
1131+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1132+
1133+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[1,1,1] neg_hi:[1,1,1]
1134+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[1,1,1] neg_hi:[1,1,1] ; encoding: [0x08,0x47,0x37,0xcc,0x01,0x03,0x10,0xfc]
1135+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1136+
1137+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[1,0,0]
1138+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[1,0,0] ; encoding: [0x08,0x40,0x37,0xcc,0x01,0x03,0x10,0x3c]
1139+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1140+
1141+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[0,1,0]
1142+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[0,1,0] ; encoding: [0x08,0x40,0x37,0xcc,0x01,0x03,0x10,0x5c]
1143+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1144+
1145+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[0,0,1]
1146+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_lo:[0,0,1] ; encoding: [0x08,0x40,0x37,0xcc,0x01,0x03,0x10,0x9c]
1147+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1148+
1149+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_hi:[1,0,0]
1150+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_hi:[1,0,0] ; encoding: [0x08,0x41,0x37,0xcc,0x01,0x03,0x10,0x1c]
1151+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1152+
1153+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_hi:[0,1,0]
1154+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_hi:[0,1,0] ; encoding: [0x08,0x42,0x37,0xcc,0x01,0x03,0x10,0x1c]
1155+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1156+
1157+
v_pk_maximum3_f16 v8, v1, s1, v4 neg_hi:[0,0,1]
1158+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 neg_hi:[0,0,1] ; encoding: [0x08,0x44,0x37,0xcc,0x01,0x03,0x10,0x1c]
1159+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1160+
1161+
v_pk_maximum3_f16 v8, v1, s1, v4 clamp
1162+
// GFX1250: v_pk_maximum3_f16 v8, v1, s1, v4 clamp ; encoding: [0x08,0xc0,0x37,0xcc,0x01,0x03,0x10,0x1c]
1163+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1164+
1165+
v_pk_maximum3_f16 v1, v4, v9, v16
1166+
// GFX1250: v_pk_maximum3_f16 v1, v4, v9, v16 ; encoding: [0x01,0x40,0x37,0xcc,0x04,0x13,0x42,0x1c]
1167+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
1168+
1169+
v_pk_maximum3_f16 v1, v2, v5, 1.0
1170+
// GFX1250: v_pk_maximum3_f16 v1, v2, v5, 1.0 ; encoding: [0x01,0x40,0x37,0xcc,0x02,0x0b,0xca,0x1b]
1171+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

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