[LLVM][AMDGPU] add new sched strat

Author: makslevental

llvm/lib/IR/LegacyPassManager.cpp

@@ -55,7 +55,7 @@ static cl::opt<enum PassDebugLevel> PassDebugging(
                clEnumVal(Arguments, "print pass arguments to pass to 'opt'"),
                clEnumVal(Structure, "print pass structure before run()"),
                clEnumVal(Executions, "print pass name before it is executed"),
-               clEnumVal(Details, "print pass details when it is executed")));
+               clEnumVal(Details, "print pass details when it is executed")), cl::init(Disabled));
 
 /// isPassDebuggingExecutionsOrMore - Return true if -debug-pass=Executions
 /// or higher is specified.

llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

@@ -736,7 +736,7 @@ class MaxsOpt final : public IGLPStrategy {
 
   MaxsOpt(ScheduleDAGInstrs *DAG, const SIInstrInfo *TII)
       : IGLPStrategy(DAG, TII) {
-    IsBottomUp = true;
+    IsBottomUp = false;
   }
 };
 

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -580,6 +580,7 @@ createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
   ScheduleDAGMILive *DAG =
     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
+  // DAG->addMutation(createMaxsMaxsUnpackPackedF32OpsDAGMutation(*DAG));
   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
   if (ST.shouldClusterStores())
     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -520,6 +520,7 @@ GCNMaxOccupancySchedStrategy::GCNMaxOccupancySchedStrategy(
     const MachineSchedContext *C, bool IsLegacyScheduler)
     : GCNSchedStrategy(C) {
   SchedStages.push_back(GCNSchedStageID::OccInitialSchedule);
+  SchedStages.push_back(GCNSchedStageID::MaxsUnpackPackedF32OpsSchedule);
   SchedStages.push_back(GCNSchedStageID::UnclusteredHighRPReschedule);
   SchedStages.push_back(GCNSchedStageID::ClusteredLowOccupancyReschedule);
   SchedStages.push_back(GCNSchedStageID::PreRARematerialize);
@@ -783,6 +784,9 @@ GCNScheduleDAGMILive::createSchedStage(GCNSchedStageID SchedStageID) {
   case GCNSchedStageID::MemoryClauseInitialSchedule:
     return std::make_unique<MemoryClauseInitialScheduleStage>(SchedStageID,
                                                               *this);
+  case GCNSchedStageID::MaxsUnpackPackedF32OpsSchedule:
+    return std::make_unique<MaxsUnpackPackedF32OpsScheduleStage>(SchedStageID,
+                                                                 *this);
   }
 
   llvm_unreachable("Unknown SchedStageID.");
@@ -1130,6 +1134,31 @@ void UnclusteredHighRPStage::finalizeGCNSchedStage() {
   GCNSchedStage::finalizeGCNSchedStage();
 }
 
+struct MaxsUnpackPackedF32OpsDAGMutation : ScheduleDAGMutation {
+  GCNScheduleDAGMILive &DAG;
+
+  MaxsUnpackPackedF32OpsDAGMutation(GCNScheduleDAGMILive &DAG) : DAG(DAG) {}
+
+  void apply(ScheduleDAGInstrs *DAG) override {
+    const TargetInstrInfo &TII = *DAG->TII;
+    const GCNSubtarget &ST = DAG->MF.getSubtarget<GCNSubtarget>();
+    LLVM_DEBUG(dbgs() << "Completed MaxsUnpackPackedF32OpsDAGMutation\n");
+  }
+};
+
+namespace llvm {
+std::unique_ptr<ScheduleDAGMutation>
+createMaxsUnpackPackedF32OpsDAGMutation(GCNScheduleDAGMILive &DAG) {
+  return std::make_unique<MaxsUnpackPackedF32OpsDAGMutation>(DAG);
+}
+
+std::unique_ptr<ScheduleDAGMutation>
+createMaxsUnpackPackedF32OpsDAGMutation(ScheduleDAGMILive &DAG) {
+  return std::make_unique<MaxsUnpackPackedF32OpsDAGMutation>(reinterpret_cast<GCNScheduleDAGMILive &>(DAG));
+}
+
+}
+
 bool GCNSchedStage::initGCNRegion() {
   // Check whether this new region is also a new block.
   if (DAG.RegionBegin->getParent() != CurrentMBB)
@@ -1189,6 +1218,11 @@ bool GCNSchedStage::initGCNRegion() {
                        : AMDGPU::SchedulingPhase::PreRAReentry));
   }
 
+  if (StageID == GCNSchedStageID::MaxsUnpackPackedF32OpsSchedule) {
+    DAG.addMutation(createMaxsUnpackPackedF32OpsDAGMutation(DAG));
+    return true;
+  }
+
   return true;
 }
 
@@ -1548,6 +1582,11 @@ bool MemoryClauseInitialScheduleStage::shouldRevertScheduling(
   return mayCauseSpilling(WavesAfter);
 }
 
+bool MaxsUnpackPackedF32OpsScheduleStage::shouldRevertScheduling(
+    unsigned WavesAfter) {
+  return false;
+}
+
 bool GCNSchedStage::mayCauseSpilling(unsigned WavesAfter) {
   if (WavesAfter <= MFI.getMinWavesPerEU() && isRegionWithExcessRP() &&
       !PressureAfter.less(MF, PressureBefore)) {

llvm/lib/Target/AMDGPU/GCNSchedStrategy.h

@@ -30,7 +30,8 @@ enum class GCNSchedStageID : unsigned {
   ClusteredLowOccupancyReschedule = 2,
   PreRARematerialize = 3,
   ILPInitialSchedule = 4,
-  MemoryClauseInitialSchedule = 5
+  MemoryClauseInitialSchedule = 5,
+  MaxsUnpackPackedF32OpsSchedule = 6
 };
 
 #ifndef NDEBUG
@@ -490,6 +491,20 @@ class MemoryClauseInitialScheduleStage : public GCNSchedStage {
       : GCNSchedStage(StageID, DAG) {}
 };
 
+class MaxsUnpackPackedF32OpsScheduleStage : public GCNSchedStage {
+public:
+  bool shouldRevertScheduling(unsigned WavesAfter) override;
+
+  MaxsUnpackPackedF32OpsScheduleStage(GCNSchedStageID StageID,
+                                      GCNScheduleDAGMILive &DAG)
+      : GCNSchedStage(StageID, DAG) {}
+};
+
+std::unique_ptr<ScheduleDAGMutation>
+createMaxsMaxsUnpackPackedF32OpsDAGMutation(GCNScheduleDAGMILive &DAG);
+std::unique_ptr<ScheduleDAGMutation>
+createMaxsMaxsUnpackPackedF32OpsDAGMutation(ScheduleDAGMILive &DAG);
+
 class GCNPostScheduleDAGMILive final : public ScheduleDAGMI {
 private:
   std::vector<std::unique_ptr<ScheduleDAGMutation>> SavedMutations;