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RobertoFrescaRobertoFresca
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Super Cherry Master bootleg hardware improvements: [Roberto Fresca, Grull Osgo]
 Added 0Ch and 0Dh missing ports, hooked remaining DIP switches banks. New inputs from the scratch for New Cherry '96 and base for New Cherry '98. Switched the New Cherry '96 sets to this machine. Added buttons-lamps control panel layout. Defined parent-clone relationship. New working systems ------------------- New Cherry '98 (v4.3 1998/09/07, Gamemax bootleg, set 1) [Roberto Fresca, Grull Osgo, Ioannis Bampoulas] New working clones ------------------ New Cherry '98 (v4.3 1998/09/07, Gamemax bootleg, set 2) [Roberto Fresca, Grull Osgo, Ioannis Bampoulas] Systems promoted to working --------------------------- New Cherry '96 (1997/01/04, bootleg) [Roberto Fresca, Grull Osgo, Ioannis Bampoulas] Clones promoted to working -------------------------- New Cherry '96 (1996/06/01, bootleg) [Roberto Fresca, Grull Osgo, Ioannis Bampoulas]
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2 files changed

+205
-6
lines changed

2 files changed

+205
-6
lines changed

‎src/mame/igs/goldstar.cpp‎

Lines changed: 203 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4597,8 +4597,9 @@ void unkch_state::unkch_portmap(address_map &map)
45974597
void unkch_state::unkchx_map(address_map &map)
45984598
{
45994599
map(0x0000, 0x7fff).rom();
4600-
map(0x8000, 0xb9ff).bankr("bank1");
4601-
map(0xba00, 0xbfff).ram();
4600+
map(0x8000, 0xb7ff).bankr("bank1");
4601+
map(0xb800, 0xbfff).ram(); // fixed for cherry 98. tested and working for all family members.
4602+
46024603

46034604
map(0xc000, 0xc1ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
46044605
map(0xc800, 0xc9ff).ram().w(m_palette, FUNC(palette_device::write8_ext)).share("palette_ext");
@@ -4629,6 +4630,8 @@ void unkch_state::unkchx_portmap(address_map &map)
46294630
unkch_portmap(map);
46304631

46314632
map(0x03, 0x03).w(FUNC(unkch_state::bankswitch_w));
4633+
map(0x0c, 0x0c).portr("DSW5");
4634+
map(0x0d, 0x0d).portr("DSW6");
46324635
}
46334636

46344637

@@ -12022,6 +12025,167 @@ static INPUT_PORTS_START( unkch4 )
1202212025
PORT_DIPSETTING( 0x00, "x9 / x5" )
1202312026
INPUT_PORTS_END
1202412027

12028+
static INPUT_PORTS_START( unkch5 )
12029+
12030+
PORT_INCLUDE( unkch_controls )
12031+
12032+
PORT_START("DSW1")
12033+
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:1")
12034+
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
12035+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12036+
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:2")
12037+
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
12038+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12039+
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
12040+
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
12041+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12042+
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:4")
12043+
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
12044+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12045+
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:5")
12046+
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
12047+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12048+
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:6")
12049+
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
12050+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12051+
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:7")
12052+
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
12053+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12054+
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
12055+
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
12056+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12057+
12058+
PORT_START("DSW2")
12059+
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:1")
12060+
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
12061+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12062+
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:2")
12063+
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
12064+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12065+
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:3")
12066+
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
12067+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12068+
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:4")
12069+
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
12070+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12071+
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:5")
12072+
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
12073+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12074+
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:6")
12075+
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
12076+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12077+
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:7")
12078+
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
12079+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12080+
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8")
12081+
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
12082+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12083+
12084+
PORT_START("DSW3")
12085+
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:1")
12086+
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
12087+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12088+
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:2")
12089+
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
12090+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12091+
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:3")
12092+
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
12093+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12094+
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:4")
12095+
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
12096+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12097+
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:5")
12098+
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
12099+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12100+
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:6")
12101+
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
12102+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12103+
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:7")
12104+
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
12105+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12106+
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW3:8")
12107+
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
12108+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12109+
12110+
PORT_START("DSW4")
12111+
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:1")
12112+
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
12113+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12114+
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:2")
12115+
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
12116+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12117+
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:3")
12118+
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
12119+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12120+
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:4")
12121+
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
12122+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12123+
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:5")
12124+
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
12125+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12126+
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:6")
12127+
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
12128+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12129+
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7")
12130+
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
12131+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12132+
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:8")
12133+
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
12134+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12135+
12136+
PORT_START("DSW5")
12137+
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:1")
12138+
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
12139+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12140+
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:2")
12141+
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
12142+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12143+
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:3")
12144+
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
12145+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12146+
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:4")
12147+
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
12148+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12149+
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:5")
12150+
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
12151+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12152+
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:6")
12153+
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
12154+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12155+
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:7")
12156+
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
12157+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12158+
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:8")
12159+
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
12160+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12161+
12162+
PORT_START("DSW6")
12163+
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:1")
12164+
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
12165+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12166+
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:2")
12167+
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
12168+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12169+
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:3")
12170+
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
12171+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12172+
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:4")
12173+
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
12174+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12175+
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:5")
12176+
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
12177+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12178+
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:6")
12179+
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
12180+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12181+
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:7")
12182+
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
12183+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12184+
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:8")
12185+
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
12186+
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12187+
INPUT_PORTS_END
12188+
1202512189
static INPUT_PORTS_START( unkchx )
1202612190
PORT_INCLUDE( unkch_controls_alt )
1202712191

@@ -12128,6 +12292,14 @@ static INPUT_PORTS_START( unkchx )
1212812292
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:8")
1212912293
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1213012294
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
12295+
12296+
PORT_START("DSW5")
12297+
PORT_DIPNAME( 0xff, 0xff, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW5:1,2,3,4,5,6,7,8")
12298+
PORT_DIPSETTING( 0xff, DEF_STR( Off ) )
12299+
12300+
PORT_START("DSW6")
12301+
PORT_DIPNAME( 0xff, 0xff, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW6:1,2,3,4,5,6,7,8")
12302+
PORT_DIPSETTING( 0xff, DEF_STR( Off ) )
1213112303
INPUT_PORTS_END
1213212304

1213312305

@@ -25029,8 +25201,8 @@ ROM_START( rolling ) // Z80A + 95101 (AY8910) + Actel A40MX04 + 4 8-dip banks
2502925201
ROM_LOAD( "palce20v8h.u48", 0x800, 0x157, NO_DUMP )
2503025202
ROM_END
2503125203

25032-
25033-
ROM_START( cherry96 ) // all roms unique
25204+
// Cherry 96-98 bootlegs running in Super Cherry Master bootleg hardware.
25205+
ROM_START( cherry96 )
2503425206
ROM_REGION( 0x10000, "maincpu", 0 )
2503525207
ROM_LOAD( "new_96-16-3.u6", 0x00000, 0x10000, CRC(84d5f2fc) SHA1(e3ed0670350920c661c5a40581966671b8a8c7df) )
2503625208

@@ -25052,6 +25224,27 @@ ROM_START( cherry96a )
2505225224
ROM_LOAD( "nc96.u41", 0x00000, 0x20000, CRC(9ab19bdc) SHA1(2f34789729b5d12f6fa098a29253d5a80aef5b39) )
2505325225
ROM_END
2505425226

25227+
ROM_START( cherry98 )
25228+
ROM_REGION( 0x10000, "maincpu", 0 )
25229+
ROM_LOAD( "u6", 0x00000, 0x10000, CRC(dfa252f6) SHA1(a891a680845658c0cac1ae05f8b1185a62166335) )
25230+
25231+
ROM_REGION( 0x20000, "gfx1", 0 )
25232+
ROM_LOAD( "u29", 0x00000, 0x20000, CRC(978f4a23) SHA1(f57ab6b8afbf1703474a5856a4283a6ec7d2b488) )
25233+
25234+
ROM_REGION( 0x40000, "gfx2", 0 )
25235+
ROM_LOAD( "u41", 0x00000, 0x20000, CRC(e764a2e7) SHA1(00518dca368490f1a294ea97daa26666397479fa) )
25236+
ROM_END
25237+
25238+
ROM_START( cherry98a )
25239+
ROM_REGION( 0x10000, "maincpu", 0 )
25240+
ROM_LOAD( "u6", 0x00000, 0x10000, CRC(fecc04a2) SHA1(6ea8efdaba4d41b8b59cc69fc998ca92a645ce1a) )
25241+
25242+
ROM_REGION( 0x20000, "gfx1", 0 )
25243+
ROM_LOAD( "u29", 0x00000, 0x20000, CRC(978f4a23) SHA1(f57ab6b8afbf1703474a5856a4283a6ec7d2b488) )
25244+
25245+
ROM_REGION( 0x40000, "gfx2", 0 )
25246+
ROM_LOAD( "u41", 0x00000, 0x20000, CRC(e764a2e7) SHA1(00518dca368490f1a294ea97daa26666397479fa) )
25247+
ROM_END
2505525248

2505625249
// a Cherry Master 97 bootleg running on Super Cherry Master hardware
2505725250
ROM_START( cmast97bl18 )
@@ -30584,14 +30777,18 @@ GAMEL(1999, unkch2, scmaster, unkch, unkch, unkch_state, init_un
3058430777
GAMEL(1999, unkch3, scmaster, unkch, unkch3, unkch_state, init_unkch3, ROT0, "bootleg", "New Cherry Gold '99 (bootleg of Super Cherry Master) (set 2)", 0, layout_unkch ) // cards have been hacked to look like barrels, girl removed?
3058530778
GAMEL(1999, unkch4, scmaster, unkch, unkch4, unkch_state, init_unkch4, ROT0, "bootleg", "Grand Cherry Master (bootleg of Super Cherry Master)", 0, layout_unkch ) // by 'Toy System' Hungary
3058630779

30587-
GAME( 1996, cherry96, scmaster, unkch, unkch4, unkch_state, init_unkch4, ROT0, "bootleg", "New Cherry '96 (1997/01/04, bootleg of New Fruit Bonus?)", MACHINE_NOT_WORKING ) // need to be moved to another machine...
30588-
GAME( 1996, cherry96a, scmaster, unkch, unkch4, unkch_state, init_unkch4, ROT0, "bootleg", "New Cherry '96 (1996/06/01, bootleg of New Fruit Bonus?)", MACHINE_NOT_WORKING ) // need to be moved to another machine...
30780+
GAMEL(1996, cherry96, 0, unkchx, unkch5, unkch_state, init_unkch4, ROT0, "bootleg", "New Cherry '96 (1997/01/04, bootleg)", 0, layout_unkchx )
30781+
GAMEL(1996, cherry96a, cherry96, unkchx, unkch5, unkch_state, init_unkch4, ROT0, "bootleg", "New Cherry '96 (1996/06/01, bootleg)", 0, layout_unkchx )
3058930782

3059030783
GAME( 1998, rolling, scmaster, rolling, unkch4, unkch_state, empty_init, ROT0, "bootleg", "Rolling", MACHINE_NOT_WORKING ) // inputs, outputs
3059130784

3059230785
GAMEL(1997, cmast97bl18, cmast97, unkchx, unkchx, unkch_state, empty_init, ROT0, "bootleg", "Cherry Master '97 (v1.8, bootleg)", 0, layout_unkchx )
3059330786
GAMEL(1997, cmast97bl16, cmast97, unkchx, unkchx, unkch_state, empty_init, ROT0, "bootleg", "Cherry Master '97 (v1.6, bootleg)", 0, layout_unkchx )
3059430787

30788+
GAMEL(1998, cherry98, 0, unkchx, unkch5, unkch_state, empty_init, ROT0, "bootleg", "New Cherry '98 (v4.3 1998/09/07, Gamemax bootleg, set 1)", 0, layout_unkchx )
30789+
GAMEL(1998, cherry98a, cherry98, unkchx, unkch5, unkch_state, empty_init, ROT0, "bootleg", "New Cherry '98 (v4.3 1998/09/07, Gamemax bootleg, set 2)", 0, layout_unkchx )
30790+
30791+
3059530792

3059630793
// ******************* Stealth sets *******************
3059730794
// These have hidden games inside that can be switched

‎src/mame/mame.lst‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20609,6 +20609,8 @@ cbaai
2060920609
cbonus
2061020610
cherry96
2061120611
cherry96a
20612+
cherry98
20613+
cherry98a
2061220614
chry10
2061320615
chryangl
2061420616
chryangla

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